SM5330A

SM5330A NPC | Alldatasheet

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Technical content

SEIKO NPC CORPORATION —1 3-channel Video Filter with Built-in 4-system Switch OVERVIEW The SM5330A is a 4-system input switching 3-channel video filter with 5th-order lowpass filter built-in. The lowpass filter cutoff frequency range is 5MHz to 13MHz (SD mode) or 16MHz to 40MHz (HD mode), con- trolled using an I C BUS . The lowpass filter enables the device to be utilized in the analog input stage of video signal equipment, functioning as an ADC system anti-aliasing filter for 480i to 1080i signal systems. The signal input type and input system switching, in addition to the cutoff frequency, can be controlled using the I C BUS. The I C BUS slave address is set using the ADS pin (3-state input), allowing a maximum of three SM5330A devices to be controlled simultaneously. *1. I C BUS is a registered trademark of Philips Electronics N.V.

FEATURES

I Supply voltages

• Analog : 4.75 to 5.25V
• Digital : 3.0 to 5.5V I 4-system input switch function (3 channels) I Lowpass filter function with 64-level cutoff fre- quency setting for each of SD/HD modes
• Cutoff frequency range SD : 5MHz to 13MHz HD: 16MHz to 40MHz I Video input pins can be independently set to sync- tip clamp/bias/direct inputs I Output muting function I 8-bit D/A converters built-in for control of arbitrary external circuits I I C BUS interface control
• Slave address: 48h, 49h, 4Ah select (up to three devices can be used simultaneously, selected by ADS input)
• Data transfer rate: fast mode (400kbit/s) com- patible
• Control register write function, status register read function I Output gain: 6dB I Operating ambient temperature range: –20 to 70 C I Package: 48-pin LQFP

APPLICATIONS

I HDTVs I LCD TVs I PDPs I Projectors

ORDERING INFORMATION

(Top view) PACKAGE DIMENSION (Unit: mm) Weight: 0.18g Device Package SM5330AF 48-pin LQFP IN3_1 IN3_2 IN3_3 IN4_1 IN4_2 IN4_3 GND GND GND DAC_0 TEST DAC_1 YOUT GND OUT_3 VCC GND VCC OUT_2 GND OUT_1 VCC VCCD I/O_0 I/O_1 SCL ADS SDA VDD GND IREF VREF GND IN1_1 IN1_2 IN1_3 IN1_L1 IN1_L2 IIN1_L3 IN1_SW IN2_1 IN2_2 IN2_3 VCC IN2_L1 IN2_L2 IN2_L3 IN2_SW 0.50 0.19 ± 0.05 0.08 0.10 0 to 10 ° 0.10 ± 0.07 M + 0.20 1.50 − 0.10 9.00 ± 0.20 0.50 ± 0.10 7.00 ± 0.20 9.00 ± 0.20 7.00 ± 0.20 0.35MAX 0.17 ± 0.05 0.339TYP 1.00TYP

SEIKO NPC CORPORATION —2 BLOCK DIAGRAM SCL SDA VDD DGND OUT_1 I C BUS I/F IN1_L1 Control Logic IN1_L2 IN1_L3 IN1_SW Bias /off Bias /off Clamp /Bias /off Comparator VCCD ADS I/O_1 I/O_0 Reference IN1_1 IN1_2 IN1_3 IN2_L1 IN2_L2 IN2_L3 IN2_SW Bias /off Bias /off Clamp /Bias /off IN2_1 IN2_2 IN2_3 Bias /off Bias /off Clamp /Bias /off IN3_1 IN3_2 IN3_3 Bias /off Bias /off Clamp /Bias /off IN4_1 IN4_2 IN4_3 5th order LPF CH-3 6dB 5th order LPF CH-2 6dB 5th order LPF CH-1 6dB DAC DAC 0dB VCC DAC_1 DAC_0 OUT_2 OUT_3 GND YOUT VREF IREF TEST

SEIKO NPC CORPORATION —3 PIN DESCRIPTION Number Name I/O A/D

Description

1 IN3_1 I A System 3 channel 1 video signal input pin

2 IN3_2 I A System 3 channel 2 video signal input pin

3 IN3_3 I A System 3 channel 3 video signal input pin

4 GND GND A Analog ground pin

5 IN4_1 I A System 4 channel 1 video signal input pin

6 IN4_2 I A System 4 channel 2 video signal input pin

7 IN4_3 I A System 4 channel 3 video signal input pin

8 GND GND A Analog ground pin

9 DAC_0 O A DAC voltage output pin. Output voltage set using the I C BUS. 10 TEST I D Test pin. Connect to ground for normal operation. 11 DAC_1 O A DAC voltage output pin. Output voltage set using the I C BUS.

12 GND GND A Analog ground pin

13 YOUT O A Y signal output pin. The channel 3 video signal is output without filtering.

14 GND GND A Analog ground pin

15 OUT_3 O A Channel 3 video signal output pin. The output system is selected using the I C BUS.

16 VCC P A Analog supply pin

17 GND GND A Analog ground pin

18 VCC P A Analog supply pin

19 OUT_2 O A Channel 2 video signal output pin. The output system is selected using the I C BUS.

20 GND GND A Analog ground pin

21 OUT_1 O A Channel 1 video signal output pin. The output system is selected using the I C BUS.

22 VCC P A Analog supply pin

23 VCCD P D Logic supply pin. Connect to the same potential as VCC. 24 I/O_0 I/O D Logic I/O pins. Outputs are open-drain. Connect pull-up to VCCD. The open-drain outputs are turned ON/OFF using I C BUS settings. The input state can be read out via the I C BUS.25 I/O_1 I/O D 26 ADS I D Address select pin. 3-state input Select the I C BUS slave address. (L: 48h, H: 49h, Z: 4Ah)

27 SCL I D I

C BUS clock signal pin. Connect pull-up to VDD.

28 SDA I/O D I

C BUS data signal pin. Connect pull-up to VDD. The output is open-drain.

29 VDD P D I

C BUS interface-stage supply pin. 3.0V to 5.5V

30 DGND GND D Logic ground pin

31 IREF O A

Cutoff frequency control pin. Connect a 1.8k Ω ±1% resistor between this pin and GND. The current that flows in the resistor sets the internal filter reference current.

32 VREF O A Internal reference voltage pin

33 GND GND A Analog ground pin

34 IN1_1 I A System 1 channel 1 video signal input pin

35 IN1_2 I A System 1 channel 2 video signal input pin

36 IN1_3 I A System 1 channel 3 video signal input pin

SEIKO NPC CORPORATION —4 37 IN1_L1 I D System 1 D-terminal signal discriminator input pin. 3-state input

38 IN1_L2 I D System 1 D-terminal signal discriminator input pin

39 IN1_L3 I D System 1 D-terminal signal discriminator input pin. 3-state input

40 IN1_SW I D System 1 D-terminal signal discriminator input pin

41 IN2_1 I A System 2 channel 1 video signal input pin

42 IN2_2 I A System 2 channel 2 video signal input pin

43 IN2_3 I A System 2 channel 3 video signal input pin

44 VCC P A Analog supply pin

45 IN2_L1 I D System 2 D-terminal signal discriminator input pin. 3-state input

46 IN2_L2 I D System 2 D-terminal signal discriminator input pin

47 IN2_L3 I D System 2 D-terminal signal discriminator input pin. 3-state input

48 IN2_SW I D System 2 D-terminal signal discriminator input pin

*1. I: input, O: output, P: Power supply, GND: Ground *2. A: analog, D: digital Number Name I/O A/D

SEIKO NPC CORPORATION —5 PIN EQUIVALENT CIRCUITS Number Name I/O Equivalent circuit IN1_1 IN1_2 IN1_3 IN2_1 IN2_2 IN2_3 IN3_1 IN3_2 IN3_3 IN4_1 IN4_2 IN4_3 I DAC_0 DAC_1 O

10 TEST I

13 YOUT O

INn_n GND 45Ω 20kΩ VCC GND DAC_n 5kΩ 5kΩ VCCD TEST GND 180Ω VCC GND YOUT 200Ω

SEIKO NPC CORPORATION —6 OUT_3 OUT_2 OUT_1 O I/O_0 I/O_1 I/O

26 ADS I

27 SCL I

OUT_n GND 671Ω 500Ω VCCD I/O_n DGND 180Ω VCCD DGND 180Ω 100kΩ 100kΩ ADS VDD SCL DGND 180Ω

SEIKO NPC CORPORATION —7

28 SDA I/O

31 IREF O

32 VREF O

IN1_L1 IN1_L2 IN1_L3 IN1_SW IN2_L1 IN2_L2 IN2_L3 IN2_SW I *1. I: input, O: output Number Name I/O Equivalent circuit VDD SDA DGND 180Ω VCC GND IREF 200Ω70Ω VCC GND VREF INn_Ln 180Ω VCC GND

SEIKO NPC CORPORATION —8 SPECIFICATIONS Absolute Maximum Ratings GND = 0V , VCC = VDD = VCCD Recommended Operating Conditions

Electrical Characteristics

V CC = 5.0V , V DD = 3.0 to 5.5V , Ta = 25 C, fin = 100kHz, V IN = 1.0Vp-p, R ISET = 1.8k Ω , R L = 75k Ω CH-1 and CH-2 bias inputs, CH-3 clamp input, FCM = H, FCSET = 3Fh, unless otherwise noted. Parameter Symbol Condition Rating Unit Supply voltage V CC VCC, VDD, VCCD 0.3 to 7.0 V Input voltage V IN GND – 0.3 to V CC + 0.3 V Storage temperature range T STG 55 to 125 C Power dissipation P D θ ja = 60 C/W (at Ta = 25 C, PCB wiring density: 100%, 0.5m/s air flow) 0.91 W Junction temperature T J 125 C Parameter Symbol Condition Rating Unit Supply voltage 1 V CC VCC, VCCD 4.75 to 5.25 V Supply voltage 2 V DD VDD 3.0 to 5.5 V Operating ambient temperature Ta Wiring density: 100%, air flow: 0.5m/s –20 to 70 C Parameter Symbol Condition Rating Unit Test levelmin typ max Current consumption I CC1 V CC = 5.25V, V IN = 0.0V P–P – 112 154 mA I HIGH-level input voltage 1 V IH1 SDA, SCL 0.7 V DD ––V I LOW-level Input voltage 1 V IL1 – – 0.3 V DD VI HIGH-level input voltage 2 V IH2 ADS 0.8 V CC ––V I Middle-level input voltage 2 V IM2 V CC 0.2 – V CC 0.2 VI LOW-level input voltage 2 V IL2 – – 0.2 V CC VI HIGH-level input voltage 3 V IH3 IN1_L1, IN1_L3, IN2_L1, IN2_L3 3.5 – – V I Middle-level input voltage 3 V IM3 1.4 – 2.4 V I LOW-level input voltage 3 V IL3 – – 0.8 V I HIGH-level input voltage 4 V IH4 IN1_L2, IN2_L2 3.5 – – V I LOW-level Input voltage 4 V IL4 – – 2.4 V I HIGH-level input voltage 5 V IH5 IN1_SW, IN2_SW 3.2 – – V I LOW-level Input voltage 5 V IL5 – – 1.8 V I HIGH-level input voltage 6 V IH6 I/O_0, I/O_1 3.0 – – V I LOW-level Input voltage 6 V IL6 – – 1.5 V I HIGH-level input leakage current 1 I LH1 SDA, SCL at input voltage = V DD – – ± 1.0 µ AI LOW-level input leakage current 1 I LL1 SDA, SCL at input voltage = 0V – – ± 1.0 µ AI HIGH-level input leakage current 2 I LH2 I/O_0, I/O_1 at input voltage = V CC – – ± 1.0 µ AI LOW-level input leakage current 2 I LL2 I/O_0, I/O_1 at input voltage = 0V – – ± 1.0 µ AI LOW-level output voltage V OL SDA, I/O_0, I/O_1 at output current = 3mA 0.0 – 0.4 V I

SEIKO NPC CORPORATION —9 I2C BUS AC Characteristics VCC = 5.0V , VDD = 3.0 to 5.5V , Ta = 25°C, unless otherwise noted. Analog Input Characteristics FCM = H, FCSET = 3Fh, unless otherwise noted. Parameter Symbol Condition Rating Unit Test levelmin typ max SCL clock frequency f SCL 0 – 400 kHz II SCL hold time (start condition) t HD;STA 0.6 – – µsI I SCL LOW-level clock pulsewidth t LOW 1.3 – – µsI I SCL HIGH-level clock pulsewidth t HIGH 0.6 – – µsI I SCL setup time (start condition) t SU;STA 0.6 – – µsI I SDA data hold time t HD;DAT 0 – 0.9 µsI I SDA data setup time t SU;DAT 100 – – ns II SDA, SCL rise time t r − – 300 ns II SDA, SCL fall time t f − – 300 ns II SCL setup time (stop condition) t SU;STO 0.6 – – µsI I Bus free time (stop condition to start condition) tBUF 1.3 – – µsI I SDA, SCL input capacitance C i – – 10 pF II Note. S, Sr: start condition, P: stop condition Parameter Symbol Condition Rating Unit Test levelmin typ max Clamp voltage V CLAMP Clamp input 1.65 1.85 2.05 V I Bias voltage V BIAS Bias input 2.15 2.35 2.55 V I Input resistance R IBIAS Bias input – 20 – k Ω II Input amplitude 1 V AI1 Clamp input, THD < 1.0% – – 1.2 Vp-p I Input amplitude 2 V AI2 Bias input, THD < 1.0% – – 1.2 Vp-p I Input DC voltage range V IDC Direct input 1.5 – 3.0 V I SCL SDA tBUF tSU;STO tr tLOW tSU;DAT tf tHIGH tSU;STA tHD;STA tHD;STA tHD;DAT SS r P tf tr

SEIKO NPC CORPORATION —10 Analog Output Characteristics FCM = H, FCSET = 3Fh, unless otherwise noted. Filter Frequency Characteristics CH-1 and CH-2 bias inputs, CH-3 clamp input, unless otherwise noted. Parameter Symbol Condition Rating Unit Test levelmin typ max Output gain A V OUT_1, OUT_2, OUT_3 5.5 6.0 6.5 dB I Gain error between channels dA V Between OUT_1, OUT_2, and OUT_3 – – ± 0.2 dB I Output amplitude 1 V OUT1 Clamp input, THD < 1.0% – – 2.4 Vp-p I Output amplitude 2 V OUT2 Bias input, THD < 1.0% – – 2.4 Vp-p I Crosstalk between channels XTLK CH 0.5Vp-p input, fin = 1MHz, between 2 channels – −70 – dB II Crosstalk between input systems XTLKMUX 0.5Vp-p input, fin = 1MHz, between each input system – −70 – dB II Drive load resistance R L OUT_1, OUT_2, OUT_3 75 – – Ω I I2C response time t IIC Response time from ACK bit output when changing settings using I2C BUS ––1 µsI I Parameter Symbol Condition Rating Unit Test levelmin typ max Cutoff frequency fC1 FCM = 0, FCSET = 00h 4.50 5.11 5.72 MHz I fC2 FCM = 0, FCSET = 3Fh 11.71 13.30 14.89 MHz I fC3 FCM = 1, FCSET = 00h 13.74 15.61 17.48 MHz I fC4 FCM = 1, FCSET = 32h 30.96 35.18 39.40 MHz I fC5 FCM = 1, FCSET = 3Fh – 40.27 – MHz II 4fc attenuation A SB fin = 4fc, attenuation from fin = 100kHz − 60 − dB II

SEIKO NPC CORPORATION —11 DAC Characteristics VCC = 5.0V , VDD = 3.0 to 5.5V , Ta = 25°C, unless otherwise noted. Test Level The definition of “Test Level” shown in the electric characteristic table is as follows. I : 100% of products tested at Ta = + 25 °C. II : Guaranteed as result of design and characteristics evaluation. Measurement Circuit Parameter Symbol Condition Rating Unit Test levelmin typ max Differential linearity DLE DAC_0, DAC_1, Vn: output voltage at resister value set “n” −1 0 +1 LSB I DAC HIGH-level output voltage V OH–DAC DAC_0, DAC_1, DAC0 = DAC1 = FFh 4.30 4.45 4.60 V I DAC LOW-level output voltage V OL–DAC DAC_0, DAC_1, DAC0 = DAC1 = 00h 0.25 0.35 0.45 V I DAC output current I O–DAC DAC0 = DAC1 = FFh –0.5 − +0.5 mA I Note. This is a circuit only for the evaluation board of an electric characteristics. (It is not a recommended application circuit.) Vn – Vn–1 (V191 – V63)/128 – 1, n = 1 to 255 IN3_1 IN3_2 IN3_3 IN4_1 IN4_2 IN4_3 GND GND GND DAC_0 TEST DAC_1 YOUT GND OUT_3 VCC GND VCC OUT_2 GND OUT_1 VCC VCCD I/O_0I/O_1 SCL ADS SDA VDD GND IREF VREF GND IN1_1 IN1_2 IN1_3IN1_L1 IN1_L2 IIN1_L3 IN1_SW IN2_1 IN2_2 IN2_3 VCC IN2_L1 IN2_L2 IN2_L3 IN2_SW 75Ω/50Ω 75Ω/50Ω 75Ω/50ΩIN2_Y IN2_PB IN2_PR IN1_SW IN1_L3 IN1_L2 IN1_L1 1µF 1µF 1µF IN2_L1 IN2_L2 IN2_L3 IN2_SW 75Ω/50Ω 75Ω/50Ω 75Ω/50ΩIN3_Y IN3_PB IN3_PR 1µF 1µF 1µF 75Ω/50Ω 75Ω/50Ω 75Ω/50ΩIN4_Y IN4_PB IN4_PR 1µF 1µF 1µF 1.8kΩ±1% 1µF 75Ω/50Ω 75Ω/50Ω 75Ω/50ΩIN1_Y IN1_PB IN1_PR 1µF 1µF 1µF 2.2kΩ 2.2kΩ 10kΩ 10kΩ 0Ω1000µF 0Ω1000µF 0Ω1000µF 75Ω 75Ω 75Ω OUT_PB OUT_PR OUT_Y I/O_0 I/O_1 SCL SDA DAC_1 DAC_0 YOUT VDD VCC

SEIKO NPC CORPORATION —13 Slave Address The 7-bit slave address is selected using the ADS pin. When ADS = “L” the address is 48h, when ADS = “H” the address is 49h, and when ADS = “Z” (open) the address is 4Ah. A maximum of three SM5330A devices can be connected to one I 2C BUS simultaneously, and controlled independently by setting the slave address of each using the ADS pin. Control Register The SM5330A has a 5-byte control register. The function of each byte in the control register is described in the following tables. Sets the cutoff frequency. When FCM = “0” the filter is set to SD mode, and when FCM = “1” the filter is set to HD mode. The relationship between the register value and the cutoff frequency is described in section “Low- pass Filter”. SLAVE ADDRESS for control register write bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) 10010000 9 0 h Indicate to write when device's slave address is 48h (ADS = "L") 10010010 9 2 h Indicate to write when device's slave address is 49h (ADS = "H") 10010100 9 4 h Indicate to write when device's slave address is 4Ah (ADS = "Z") SLAVE ADDRESS for status register read bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) 10010001 9 1 h Indicate to read when device's slave address is 48h (ADS = "L") 10010011 9 3 h Indicate to read when device's slave address is 49h (ADS = "H") 10010101 9 5 h Indicate to read when device's slave address is 4Ah (ADS = "Z") CONTROL REGISTER MAP Addr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Description 00h FCM − FCSET Filter fc setting 01h IM1 IM2 IM3 IM4 Input mode setting 02h − INSEL −− I/O1 I/O0 Input switch select, I/O output control 03h DAC0 DAC_0 output control 04h DAC1 DAC_1 output control SUB ADDRESS: 00h − Filter fc setting bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) Name FCM − FCSET default 00000000 0 0 h Value

0 Set filter to SD mode (default)

1 Set filter to HD mode

00 000000 00h fc = 5.11MHz (default) 00 : : : 00 111111 3Fh fc = 13.30MHz 10 000000 80h fc = 15.61MHz 10 : : : 10 111111 BFh fc = 40.27MHz

SEIKO NPC CORPORATION —14 Sets the video signal input pin operating mode. Sets the video signal input switching and logic I/O pin output settings. The input can be switched between 4 systems (3-channels). This setting also determines the system that performs status register D-terminal discrim- ination. The I/O_0 and I/O_1 pins are n-channel MOS open-drain outputs. When the I/O pins are used as inputs, these bits are set to “1” so that the output is high impedance. SUB ADDRESS: 01h − Input mode setting bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex)

00 IN1_3: synctip clamp input, IN1_2 and IN1_1:

bias input (default)

01 IN1_3, IN1_2 and IN1_1: bias input

10 IN1_3, IN1_2 and IN1_1: synctip clamp input

11 IN1_3, IN1_2 and IN1_1: direct (DC) input

00 IN2_3: synctip clamp input, IN2_2 and IN2_1:

bias input (default)

01 IN2_3, IN2_2 and IN2_1: bias input

10 IN2_3, IN2_2 and IN2_1: synctip clamp input

11 IN2_3, IN2_2 and IN2_1: direct (DC) input

00 IN3_3: synctip clamp input, IN3_2 and IN3_1:

bias input (default)

01 IN3_3, IN3_2 and IN3_1: bias input

10 IN3_3, IN3_2 and IN3_1: synctip clamp input

11 IN3_3, IN3_2 and IN3_1: direct (DC) input

00 IN4_3: synctip clamp input, IN4_2 and IN4_1:

bias input (default)

01 IN4_3, IN4_2 and IN4_1: bias input

10 IN4_3, IN4_2 and IN4_1: synctip clamp input

11 IN4_3, IN4_2 and IN4_1: direct (DC) input

SUB ADDRESS: 02h − Input switch select, I/O output control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) Name − INSEL −− I/O1 I/O0 default 01000011 4 3 h Value 0 0 ×× 0 0 Mute 0 100 0 0 IN1_n select (default) 0 101 0 0 IN2_n select 0 110 0 0 IN3_n select 0 111 0 0 IN4_n select 00 0 0 I/O_1 output "L" 00 0 1 I/O_1 output off (input available) (default) 00 0 0 I/O_0 output "L" 00 0 1 I/O_0 output off (input available) (default)

SEIKO NPC CORPORATION —15 Sets the DAC_0 and DAC_1 pins output voltage, respectively. Status Register The SM5330A has a 3-byte status register. The function of each byte in the status register is described in the following tables. Returns the input state of the logic I/O pins. The I/O_0 and I/O_1 pins are n-channel MOS open-drain outputs. When the I/O pins are used as inputs, set the outputs “1” (high impedance) in the control register. SUB ADDRESS: 03h − DAC_0 output control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) 00000000 00h DAC_0 output 0.35V (default) :: : 11111111 FFh DAC_0 output 4.45V SUB ADDRESS: 04h − DAC_1 output control bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (Hex) 00000000 00h DAC_1 output 0.35V (default) :: : 11111111 FFh DAC_1 output 4.45V STATUS REGISTER MAP Addr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Description 00h −−−−−− IN1 IN0 I/O input status 01h L1 L2 L3 D-terminal input status 02h −−−−−− SW1 SW2 D-terminal connection status SUB ADDRESS: 00h − I/O input status bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000000 0 I/O_1 input "L" (< 1.5V) 000000 1 I/O_1 input "H" (> 3.0V) 000000 0 I/O_0 input "L" (< 1.5V) 000000 1 I/O_0 input "H" (> 3.0V)

SEIKO NPC CORPORATION —16 Returns the D-terminal discrimination result for the system determined by the INSEL register. Returns the D-terminal connection status information. SUB ADDRESS: 01h − D-terminal input status bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Decode INn_Ln input selected series via INSEL register (L1: screen ruling) 001 INn_L1 input "L" (< 0.8V) means "480" 010 INn_L1 input "M" (1.4 to 2.4V) means "720" 100 INn_L1 input "H" (> 3.5V) means "1080" (L2: I/P) 01 INn_L2 input "L" (< 2.4V) means "60i" 10 INn_L2 input "H" (> 3.5V) means "60p" (L3: aspect ratio) 001 INn_L3 input "L" (< 0.8V) means "4 : 3" 010 INn_L3 input "M" (1.4 to 2.4V) means "Letter Box" 100 INn_L3 input "H" (> 3.5V) means "16 : 9" SUB ADDRESS: 02h − D-terminal connection status bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Name − SW1 SW2 Value 000000 0 IN1_SW input "L" (< 1.8V) means "connected" 000000 1 IN1_SW input "H" (> 3.2V) means "unconnected" 000000 0 IN2_SW input "L" (< 1.8V) means "connected" 000000 1 IN2_SW input "H" (> 3.2V) means "unconnected"

ter and the output pins are DC level. Table 1. Input mode combination

Figure 3. FCSET setting vs. Cutoff frequency Table 2. Cutoff frequency vs. FCDATA (RISET = 1.8kΩ)

SEIKO NPC CORPORATION —19 YOUT Pin The YOUT pin is the unfiltered output of the selected system input pin (IN1_3, IN2_3, IN3_3, or IN4_3). The output gain is approximately 0dB. IREF Pin The IREF pin controls the built-in lowpass filter reference current, using a 1.8k Ω ± 1% control resistor that must be connected. The current flows into the IREF pin in normal operating mode and during output muting. VREF Pin The VREF pin is the internal reference voltage output. It is recommended that a capacitor be connected between VREF and GND to ensure SM5330A operating stability. The recommended value is 1µF. The voltage on VREF is output in normal operating mode and during output muting. D-Terminal Discrimination Function The D-terminal signal discrimination result can be read using the I2C BUS. The status register SW1 bit returns the state of IN1_SW, and the SW2 bit returns the state of IN2_SW. When IN1_n is selected by control register settings (INSEL = 100b), the status register L1, L2, L3 bits return the IN1_L1, IN1_L2, IN1_L3 pin states, respectively. Similarly, when IN2_n is selected (INSEL = 101b), the status register bits return the IN2_L1, IN2_L2, IN2_L3 pin states, respectively. DAC The SM5330A has two D/A converters controlled using the I 2C BUS. The control register DAC0 bit controls the DAC_0 pin output voltage, and the DAC1 bit controls the DAC_1 output voltage. I/O The I/O_0 and I/O_1 I/O pins in output mode are n-channel MOS open-drain outputs. Connect pull-up resis- tance between respective pins and the VCCD pin. Recommendation value of pull-up resistance is 10kΩ. When these pins are used as inputs, set the outputs “1” (high impedance) in the control register. When these pins are not used, they should have pull-up connections to VCCD or be connected to DGND. Power-ON Reset When power is applied, an internal power-ON reset circuit operates, initializing all internal register settings to their default settings. Power should be applied simultaneously on all supply pins.

nals should have a pull-up connection to VDD. Figure 4. Slave address 49h setting

30 VSS

26 ADS

29 VDD

SEIKO NPC CORPORATION —22 NC0501AE 2006.06 Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales @npc.co.jp