SM3320A NPC | Alldatasheet
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S E I K O N P C C O R P O R A T I O N - 1 OVERVIEW The SM3320A is an image sensor IC with a built-in single element photodiode of 1mm2 and programmable signal conditioning circuit. The IC can detect wider range of light wave from ultraviolet to infrared. The SM3320 integrates all the elements required for optical sensor into an ultra-miniature package. The signal condition circuit has a programmable gain amplifier with dark current compensation circuit, so that it can operate in wider temperature range. With 3 addressing bits, up to 8 SM3320A can be paralleled. FEATURES PACKAGE DIMENSIONS ▪ High-sensitivity preamplifier for ultraviolet to infrared detection using (Unit: mm) a single IC ▪ Dark current compensation circuit built-in for stable signal output ▪ Gain setting and output control function using serial interface (DATA, SE, CLK, OE) ▪ Connection up to 8 devices in parallel according to 3-bit address setting ▪ Transimpedance range: 500k to 240M ▪ Photodiode detector size: 2.3mm×0.6mm (1.0mm2 photodetector surface area) ▪Anti-reflection film coating with little sensitivity changing by wavelength ▪ Supply voltage range: 2.7 to 5.5V (single supply) ▪ Current consumption: 1.5mA (typ)@VDD=5V , no load ▪ Operating temperature range: -40 to +85°C ▪ Package: 12 pin HCOB
ORDERING INFORMATION
TYPICAL APPLICATION CIRCUIT Photodiode detector A B 3.2±0.1 X Y 1.15 ±0.2 0.35 0.25 0.6 5.5±0.1 A B Photodiode detector dimensions(Origin:Package center) XY -1.15 1.15 -0.7 -0.1 Package type : 12pin HCOB Package size : 3.2mm×5.5mm Photodiode detector size : 2.3mm×0.6mm (1.0mm 2 photo detector surface area) 0.5 ±0.1 ±0.05 VSS REF OUT CLK SE VDD ADC CPU SM3320A IC1 OE DATA VSS REF OUT CLK SE VDD SM3320A IC2 OE DATA VSS REF OUT CLK SE VDD SM3320A IC3 OE DATA ADC
(Top view) 123456 7 8 9101112 VSS REF OUT VDD SE CLK OE DATA NC PIN DESCRIPTION No. Name I/O Function
1 VSS S Ground
2 REF O Reference voltage
3 A0 I Address setting input 0
4 A1 I Address setting input 1
5 A2 I Address setting input 2
6 OUT O Analog output
7 VDD S Supply voltage
8 SE I Serial I/F enable input
9 CLK I Serial I/F clock input
10 OE I Output enable control
11 DA TA I/O Serial I/F data input/output
12 NC - Leave open-circuit for normal use
*. I/O: Input/Output pin I: Input pin O: Output pin S: Supply pin BLOCK DIAGRAM Photodiode Preamplifier + Postamplifier Offset Cancel Drak Current Compensation Sample Hold Buffer Timing Generator Reference Voltage Source Serial Interface REF SE OE CLK DATA GND VDD OUT
VSS=0V Parameter Symbol Condition Rating Unit Supply voltage*1 V DD VDD pin -0.3 to +7.0 V Input voltage*1*2 V IN DATA, CLK, SE, OE, A0, A1, A2 pins -0.3 to VDD+0.3 V Output voltage*1*2 V OUT OUT, REF pins -0.3 to VDD+0.3 V Storage temperature*3 T STG -55 to +90 °C *1. This parameter rating is the values that must never exceed even for a moment. This product may suffer breakdown if this parameter rating is exceeded. Operation and characteristics are guaranteed only when the product is operated at recommended operating conditions. *2. VDD is a VDD value of recommended operating conditions. *3. When stored in nitrogen or vacuum atmosphere applied to IC itself only (excluding packaging materials). Recommended Operating Conditions Recommended operating conditions guarantee the electrical characteristic. V SS=0V Rating Parameter Symbol Condition MIN TYP MAX Unit Supply voltage VDD 2.7 5.0 5.5 V OUT output load*1 100 pF REF output load*1 100 pF Operating temperature Ta -40 85 °C *1. The output load of the OUT and REF outputs presumes capacitive load only. For current load, an error in the output voltage occurs, so the outputs must be used under high-impedance conditions. Note. Since it may influence the reliability if it is used out of range of recommended operating conditions, this product should be used within this range.
Electrical Characteristics
Recommended operating conditions by standard circuit, unless otherwise noted. Rating Parameter Symbol Condition MIN TYP MAX Unit Current consumption IDD OE=0V , No output load 1.5 3.0 mA VIH1 0.8V DD Logic input voltage 1 VIL1 DATA,CLK,SE,A0,A1,A2 pins 0.2VDD V VIH2 0.8V DD Logic input voltage 2 VIL2 OE pin 0.2V DD V IIH1 1 Logic input current 1 IIL1 DATA,CLK,SE,A0,A1,A2 pins -1 A IIH2 10 20 Logic input current 2 IIL2 OE pin, VDD=5.0V -20 -10 A Logic output impedance ZDATA DATA pin, read mode 400 Ω REF output voltage VREF Load capacitance < 100pF*1 0.08V DD 0.10V DD 0.12V DD V OUT maximum output voltage VOUTH 0.65VDD 0.70V DD V Output impedance ZO OUT pin *2 400 1000 Ω *1. If a large load capacitance is connected to REF, the REF voltage may begin to oscillate. Accordingly, the load capacitance connected to the REF output should be 100pF or lower. *2. The output impedance ZO is given by the following equation, where V10 is the output voltage for 10kΩ load resistance and V0 is the output voltage with no load. ZO = (V0/V10-1)*10 [kΩ]
Photodiode Characteristics Recommended operating conditions by standard circuit, unless otherwise noted. Rating Parameter*1 Symbol Condition MIN TYP MAX Unit Photodetector sensitivity 1 470nm 0.17 A/W Photodetector sensitivity 2 525nm 0.26 A/W Photodetector sensitivity 3 680nm 0.46 A/W Photodetector sensitivity 4 870nm 0.45 A/W Photodetector sensitivity 5 940nm 0.29 A/W Photodetector sensitivity temperature characteristics 1 470nm -1600 ppm/°C Photodetector sensitivity temperature characteristics 2 525nm -1000 ppm/°C Photodetector sensitivity temperature characteristics 3 680nm -300 ppm/°C Photodetector sensitivity temperature characteristics 4 870nm 500 ppm/°C Photodetector sensitivity temperature characteristics 5 940nm 3500 ppm/°C *1. It is a characteristic decided by the device unit. P D受光感度特性 （代表特性） 0.0 0.1 0.6 300 400 500 600 700 800 900 1000 1100 1200 P h o t o d e t e c t o r s e n s i t i v i t y c h a r a c t e r i s t i c P h o t o d e t e c t o r s e n s i t i v i t y t e m p e r a t u r e c h a r a c t e r i s t i c 0.受光感度 [A/W] 波長 [nm] Photodiode Spectral response Photo sensitivity [A/W] Wavelength [nm] PD受光感度温度特性 （代表特性） 000 000 1000 2000 3000 4000 300 400 500 600 700 800 900 1000 1100 1200 -1受光感度温度特性 [ppm/℃] 波長 [nm] Photo sensitivity temperature [ppm/°C] Wavelength [nm] Photodiode Spectral response
Analog Electrical Characteristics Recommended operating conditions by standard circuit, unless otherwise noted. Rating Parameter Symbol Condition MIN TYP MAX Unit CS[00] 0.5 MΩ CS[01] 1.0 MΩ CS[10] 2.0 MΩ CS[11] TS[00]
4.0 M Ω
CS[00] 1.5 MΩ CS[01] 3.0 MΩ CS[10] 6.0 MΩ CS[11] TS[01]
12.0 M Ω
CS[00] 3.5 MΩ CS[01] 7.0 MΩ CS[10] 14.0 MΩ CS[11] TS[10]
28.0 M Ω
CS[00] 7.5 MΩ CS[01] 15.0 MΩ CS[10] 30.0 MΩ Preamplifier transimpedance*1 CS[11] TS[11]
60.0 M Ω
TS[00] 20 30 s TS[01] 40 60 s TS[10] 80 120 s Preamplifier conversion time TS[11] 160 240 s Postamplifier gain error ±1 dB REF reference, [01111111] below -40 40 mV Dark voltage REF reference, [11111111] below -40 40 mV *1. Design value: The preamplifier transimpedance can be set by specifying the preamplifier feedback capacitance (CS[1:0]) and the preamplifier conversion time (TS[1:0]). The preamplifier outputs the voltage proportional to the photocurrent of the photodiode. This is considered to be virtual impedance, and it calls preamplifier transimpedance. The preamplifier transimpedance (Rti) is calculated using the following equation. The sample and hold circuit operate in sync with the preamplifier conversion time. In order to determine the output voltage, the sample and hold circuit must complete a full cycle after optical irradiation. The irradiation time should be set to [Twice the maximum value at preamplifier conversion time (detection time) + Analog output loaded time] or longer. When optical irradiation is completed before analog output load, output voltage may become a fall or zero. It is necessary to irradiate the optical irradiation continuously until the analog output load is completed. Irradiation time Detection time Serial Interface Light Source Gain setting time Analog output loaded time Output control time Analog output load Pr eamplifier conversion time TS[00] TS[01] TS[10] TS[11] Detection time ≥60s ≥120s ≥240s ≥480s Output voltage = VREF + (Rti × Photodiode photocurrent × Postamplifier gain)
Recommended operating conditions by standard current, unless otherwise noted. Rating Parameter Symbol Condition MIN TYP MAX Unit Clock LOW-level pulse width twlw CLK pin 40 ns Clock HIGH-level pulse width twhw CLK pin 40 ns Data setup time 1 tsu1 Between SE-CLK 40 ns Data setup time 2 tsu2 Between DATA-CLK 40 ns Data hold time 1 th1 Between SE-CLK 140 ns Data hold time 2 th2 Between DATA-CLK 40 ns Clock frequency fclkw 10 MHz Settling time tst OUT pin, 100pF load, 1V output amplitude variation, time to reach 95% level 2 s Output disable time*1 tz OUT pin 0.1 s Input capacitance*2 C I SE,OE,CLK,DA TA pins 5 pF Output capacitance*2 C O OUT pin 5 pF Interface wait time tsi 100 ns *1. Design value: The output control time is described as a standard. *2. Design value: The terminal capacitance per one terminal is described. The substrate design is described as a standard. 0.5VDD base, unless otherwise noted. OE SE DATA CLK twlw twhw tsu1 tsu2 th1th2 1/fclkw tztst OUT 95% 100% R/W A2 123 1 5 1 6 A1 GS1 GS0 tsi Rea d mode Recommended operating conditions by standard current, unless otherwise noted. Rating Parameter Symbol Condition MIN TYP MAX Unit Clock LOW-level pulse width twlr CLK pin 100 ns Clock HIGH-level pulse width twhr CLK pin 100 ns Clock frequency fclkr 1 MHz SE hold time tse Between SE-CLK 500 ns Data conflict avoidance time tZZ 0 ns Read-out data delay time tRD DATA pin, load capacitance=100pF 400 ns 0.5VDD base, unless otherwise noted. SE DATA CLK twlrtwhr 1/fclkr A2R/W A1 123 8 91 5 1 6 tZZ tRD GS0GS1CS1 CS0- - tse
The SM3320A detects the current generated from a photodiode and outputs a voltage signal. The transimpedance of the preamplifier can be adjusted for coarse adjustment of the sensitivity. The transimpedance adjustment range is 0.5MΩ to 60MΩ, set using 4 adjustment bits. Also, a dark current compensation circuit is used to compensate photodiode output under dark lighting conditions for output voltage stability with low temperature variation. The gain of the postamplifier can be adjusted for fine adjustment of the sensitivity. The gain adjustment range is 1 to 4 times, set using 4 adjustment bits. Also, a built-in offset cancel circuit is used to provide low offset voltage at the output. The output voltage at the time of optical irradiation nothing outputs 0.1VDD, and calls this dark voltage. The maximum output voltage at the time of optical irradiation is 0.7VDD. The device can be addressed using address pin control. This function allows the transimpedance and gain settings to be adjusted for each device independently, when multiple devices are connected in parallel. An output enable control (OE) is used for output control. [Address and A[2:0] setting] Address A2 setting A1 setting A0 setting [000] VSS VSS VSS [001] VSS VSS VDD [010] VSS VDD VSS [011] VSS VDD VDD [100] VDD VSS VSS [101] VDD VSS VDD [110] VDD VDD VSS [111] VDD VDD VDD Serial Interface The SM3320A use a 3-wire serial interface (SE, CLK, DATA) to access the device and to set an internal register to control device operation. Note that extraneous signal input on the serial interface pins must be avoided when not reading/writing data to the device to prevent incorrect operation. Internal Register Structure The device read/write mode, address, preamplifier transimpedance, and postamplifier gain are set in the internal register. The device can be accessed for writing data to the register when the A[2:0] address write data bits match the setting of the address control inputs (A2 to A0). RW A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ---- CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 Preamplifier transimpedance Postamplifier gain Feedback capacitance Conversion timeR/W DataAdre ss Don't care 1 ) R W R e a d / W r i t e m o d e s e t b i t . S e t to “1” for read mode, and to “0” for write mode. ( 2 ) A d d r e s s A [ 2 : 0 ] ( A 2 t o A 0 ) A d d r e s s b i t s . (3) Preamplifier transimpedance CS[1:0] (D7 to D6) and TS[1:0] (D5 to D4) P r e a m p l i f i e r t r a n s i m p e d a n c e s e t t i n g b i t s (4) Postamplifier gain GS[3:0] (D3 to D0) P o s t a m p l i f i e r g a i n s e t t i n g b i t s Adress Address Address
[Adjustment bit assignment] GS3 GS2 GS1 GS0 0 0 0 0 1.00 CS1 CS0 0 0 0 1 1.08 0 0 20.0 0 0 1 0 1.17 0 1 10.0 0 0 1 1 1.27 1 0 5.0 0 1 0 0 1.38 1 1 2.5 0 1 0 1 1.50 0 1 1 0 1.63 0 1 1 1 1.78 1 0 0 0 1.94 1 0 0 1 2.13 TS1 TS0 1 0 1 0 2.33 0 0 20 1 0 1 1 2.57 0 1 40 1 1 0 0 2.85 1 0 80 1 1 0 1 3.17 1 1 160 1 1 1 0 3.55 1 1 1 1 4.00 Postamplifier gain Gain (times）Capacitance (pF) Preamplifier feedback capacitance CS[1:0] Time (µs) TS[1:0] GS[3:0]Preamplifier conversion time OUT pin Control The OUT pin is controlled by the level of the OE control pin. OE pin OUT pin Condition ≥ 0.8VDD Output enable Normal operation output when A[2:0] write data matches the setting of the address control inputs. Open Output enable Normal operation output ≤ 0.2VDD Output disable
SEIKO NPC CORPORATION - 10 Gain Setting (Writing Data to the Register, OE = LOW or Open) If OE is LOW or open circuit, serial interface operation starts for setting all data bits in the register when SE goes HIGH. 1 read/write mode bit (write mode=0), 3 address bits, and 12 write data bits are transferred in sequence. If the address data bits match the address control pin settings, the write data is loaded into the register, the write data becomes valid, and then serial interface operation ends when SE goes LOW. Note that data will be corrupted if there are less than or more than 16 clock pulses received during serial data transfer. Register write (OE = LOW) OE SE DATA CLK A2 A1 A0R/W - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 1234 5 6 7 8 9 10 11 12 13 14 15 16 "L" - - - Register write (OE = Open) OE SE DATA CLK OUT A2 A1 A0R/W - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 "L" (OPEN) (Hi-Z) - - - Ana log Output Control (Writing Data to the Register, OE = HIGH) If OE is HIGH, serial interface operation starts when SE goes HIGH. 1 read/write mode bit (write mode=0), 3 address bits, and 4 dummy data bits are transferred in sequence. The address data becomes valid and serial interface operation ends when SE goes LOW. If the address data bits match the address control pin settings, the output of the addressed device is enabled. If the output was already enabled and the address data does not match the address pin setting, the output is disabled. It is judged as address disagreement and be output disable state if there are less than or more than 8 clock pulses received during serial data transfer. In addition, sequential write cycles to the register are permitted while OE is HIGH. Register write (OE = HIGH) OE SE DATA CLK OUT A2 A1 A0R/W - 1234 5 6 78 (Hi-Z) - - -
SEIKO NPC CORPORATION - 11 Reading Data from the Register (OE = LOW or Open) The serial interface operation starts when SE goes HIGH. If OE is open circuit or LOW, 1 read/write mode bit (read mode=1), 3 address bits, and 4 dummy data bits are transferred in sequence. The address control pin setting is compared with the address register setting on the falling edge of the CLK8. If the settings match, the data in the 8-bit analog adjustment code register is read out in sequence. On the serial interface, the GS0 data bit is transferred on the CLK15 falling edge of the clock, and then any data bits transferred between the CLK16 falling edge of the clock and the falling edge on SE are undefined data. Serial interface operation ends when SE goes LOW, and the DATA terminal reverts to an input. Make sure there are not less than nor more than 16 input pulses on the CLK clock. If the number of clock pulses is incorrect, incorrect data may be written to the register or read from the register. Register read SE DATA CLK A2 A1 A0R/W - CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 1234 567891 0 1 1 1 2 1 3 1 4 1 5 1 6 -- - -
SEIKO NPC CORPORATION - 12 STANDARD CIRCUIT VSS REF OUT CLK SE VDD SM3320A OE DATA ADC 10μF CPU In the case of address [000] setting Mount a ceramic chip capacitor that is larger than 10μF proximal to IC between VDD and VSS. The rating value of electrical characteristics each parameter corresponds to the result measured in the standard circuit.
SEIKO NPC CORPORATION - 13 TYPICAL APPLICATION CIRCUIT These typical application circuits are reference circuit diagram on use, and are not circuits which our company guarantees. This company accepts no responsibility for use of products in any way about the damage etc. Devices should only be used after thorough evaluation under actual operating conditions. Circuit 1 VSS REF OUT CLK SE VDD ADC CPU SM3320A IC1 OE DATA VSS REF OUT CLK SE VDD SM3320A IC2 OE DATA VSS REF OUT CLK SE VDD SM3320A IC3 OE DATA ADC Timing Diagram OE SE DATA CLK （光照射） Rti OUT(IC1) OUT(IC2) OUT(IC3) OUT合成 IC1 IC2 IC3 (OFF) (ON) (Hi-Z) (Hi-Z) (Hi-Z) (Hi-Z) IC1 IC2 IC3 (Optical irradiation) OUT(ALL)
SEIKO NPC CORPORATION - 14 Circuit 2 CPU VSS REF OUT CLK SE VDD SM3320A IC A1 OE DATA VSS REF OUT CLK SE VDD SM3320A IC B1 OE DATA VSS REF OUT CLK SE VDD SM3320A IC B2 OE DATA VSS REF OUT CLK SE VDD SM3320A IC B8 OE DATA VSS REF OUT CLK SE VDD SM3320A IC A2 OE DATA VSS REF OUT CLK SE VDD SM3320A IC A8 OE DATA ADC ADC Timing Diagram OE(B) SE(B) DATA CLK （光照射） Rti OUT(IC A1) OUT(IC A2) OUT(IC B1) IC A1 (OFF) (ON) (Hi-Z) (Hi-Z) (Hi-Z) IC A1IC A8 IC B1 IC B8 SE(A) OE(A) IC A2 IC A3 IC A1 IC A2 IC A3 OUT(IC B2) (Hi-Z) (Optical irradiation)
SEIKO NPC CORPORATION - 15 Please pay your attention to the following points at time of using the products shown in this document. 1. The products shown in this document (hereinafter ”Products”) are designed and manufactured to the generally accepted standards of reliability as expected for use in general electronic and electrical equipment, such as personal equipment, machine tools and measurement equipment. The Products are not designed and manufactured to be used in any other special equipment requiring extremely high level of reliability and safety, such as aerospace equipment, nuclear power control equipment, medical equipment, transportation equipment, disaster prevention equipment, security equipment. The Products are not designed and manufactured to be used for the apparatus that exerts harmful influence on the human lives due to the defects, failure or malfunction of the Products. If you wish to use the Products in that apparatus, please contact our sales section in advance. In the event that the Products are used in such apparatus without our prior approval, we assume no responsibility whatsoever for any damages resulting from the use of that apparatus. 2. NPC reserves the right to change the specifications of the Products in order to improve the characteristics or reliability thereof. 3. The information described in this document is presented only as a guide for using the Products. No responsibility is assumed by us for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of the third parties. Then, we assume no responsibility whatsoever for any damages resulting from that infringements. 4. The constant of each circuit shown in this document is described as an example, and it is not guaranteed about its value of the mass production products. 5. In the case of that the Products in this document falls under the foreign exchange and foreign trade control law or other applicable laws and regulations, approval of the export to be based on those laws and regulations are necessary. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 1-9-9, Hatchobori, Chuo-ku, Tokyo 104-0032, Japan Telephone: +81-3-5541-6501 Facsimile: +81-3-5541-6510 http://www.npc.co.jp/ Email:sales@npc.co.jp ND13001-E-00 2013.01