SM320C6201GJCA20EP

SM320C6201-EP TI1 | Alldatasheet

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Technical content

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 1POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 D Controlled Baseline - - One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of -- 4 0°C to 105°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D High-Performance Fixed-Point Digital Signal Processor (DSP) SM320C6201 - - 5-ns Instruction Cycle Time - - 200-MHz Clock Rate - - Eight 32-Bit Instructions/Cycle - - 1600 MIPS D VelociTI™ Advanced Very Long Instruction Word (VLIW) TMS320C62x™ DSP CPU Core - - Eight Independent Functional Units: - - Six Arithmetic Logic Units (ALUs) (32-/40-Bit) - - Two 16-Bit Multipliers (32-Bit Results) - - Load-Store Architecture With 32 32-Bit General-Purpose Registers - - Instruction Packing Reduces Code Size - - All Instructions Conditional D Instruction Set Features - - Byte-Addressable (8-, 16-, 32-Bit Data) - - 32-Bit Address Range - - 8-Bit Overflow Protection - - Saturation - - Bit-Field Extract, Set, Clear - - Bit-Counting - - Normalization D 1M-Bit On-Chip SRAM - - 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) - - 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) - - Glueless Interface to Asynchronous Memories: SRAM and EPROM - - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel D 16-Bit Host-Port Interface (HPI) - - Access to Entire Memory Map D Two Multichannel Buffered Serial Ports (McBSPs) - - Direct Interface to T1/E1, MVIP, SCSA Framers - - ST-Bus-Switching Compatible - - Up to 256 Channels Each - - AC97-Compatible - - Serial Peripheral Interface (SPI) Compatible (Motorola™) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG‡) Boundary-Scan Compatible D 352-Pin BGA Package (GJC Suffix) D CMOS Technology - - 0.18-μm/5-Level Metal Process D 3.3-V I/Os, 1.8-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI and TMS320C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. ‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright © 2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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352-PIN BALL GRID ARRAY (BGA) PACKAGES (BOTTOM VIEW) AF AD AB AA AC W Y U V AE R N P L H J K M F G D E B A C T 2622 19 211715 1612 14 1810 11 1 Table of Contents absolute maximum ratings over operating case electrical characteristics over recommended ranges of supply voltage and operating case temperature 26....

description

The TMS320C62x™ DSPs (including the SM320C6201-EP †) are the fixed-point DSP family in the TMS320C6000™ DSP platform. The C6201 device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1600 MIPS at a clock rate of 200 MHz, the C6201 offers cost-effective solutions to high-performance DSP programming challenges. The C6201 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201 can produce two multiply-accumulates (MACs) per cycle—for a total of 466 million MACs per second (MMACS). The C62x™ DSP also has application-specific hardware logic,on-chip memory, and additional on-chip peripherals. TMS320C6000, C6000, and C62x are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. † The SM320C6201-EP device shall be referred to as C6201 throughout the remainder of this document.

memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the C6201 Processor C6000 is a trademark of Texas Instruments.

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functional and CPU (DSP core) block diagram Multichannel Buffered Serial Port 1 Direct Memory Access Controller (DMA) (4 Channels) Test C62x CPU (DSP Core) Data Path B B Register File Program Access/Cache Controller Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File PLL (x1, x4) Data Access Controller Power- Down Logic ROM/FLASH SRAM I/O Devices Synchronous FIFOs I/O Devices Timer 0 Timer 1 External Memory Interface (EMIF) Multichannel Buffered Serial Port 0 Host Port Interface (HPI) Internal Program Memory (64K Bytes) Control Registers Control Logic Internal Data Memory (64K Bytes) In-Circuit Emulation Interrupt Control Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs HOST CONNECTION Master /Slave TI PCI2040 Power PC 683xx 960 C6201 Digital Signal Processors Peripheral Control Bus DMA Bus Boot Configuration Interrupt Selector SBSRAM SDRAM

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 5POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 CPU (DSP core) description The CPU fetches VelociTI™advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of theCPU [see functional and CPU (DSP core) block diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. Theinstructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in thenext execute packet. If an execute packet crosses the fetch packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

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Figure 1. TMS320C62x CPU (DSP Core) Data Paths

Figure 2. CPU (DSP Core) and Peripheral Signals

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Figure 3. Peripheral Signals

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 9POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 Signal Descriptions SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION CLOCK/PLL CLKIN C10 I Clock Input CLKOUT1 AF22 O Clock output at full device speed CLKOUT2 AF20 O Clock output at half of device speed CLKMODE1 C6 I Clock mode selects

• Selects whether the CPU clockfrequency =i nput clockfrequency x4 or x1 CLKMODE0 C5 I • Selects whether the CPU clock frequency = input clock frequency x4 or x1 For more details on the GJC and GJL CLKMODE pins and the PLL multiply factors, see theClock PLLsection of this data sheet. PLLFREQ3 A9 PLL frequency range (3, 2, and 1) PLLFREQ2 D11 I PLL frequency range (3, 2, and 1)
• The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ1 B10 I The target range for CLKOUT1 frequency is determined by the 3 bit value of the PLLFREQ pins. PLLV‡ D12 A§ PLL analog VCC connection for the low-pass filter PLLG‡ C12 A§ PLL analog GND connection for the low-pass filter PLLF A11 A§ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS L3 I JTAG test port mode select (features an internal pullup) TDO W2 O/Z JTAG test port data out TDI R4 I JTAG test port data in (features an internal pullup) TCK R3 I JTAG test port clock TRST T1 I JTAG test port reset (features an internal pulldown) EMU1 Y1 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶ EMU0 W3 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶ RESET AND INTERRUPTS RESET K2 I Device reset NMI L2 I Nonmaskable interrupt
• Edge-driven (rising edge) EXT_INT7 U3 External interrupts EXT_INT6 V2 I External interrupts
• Edge-driven EXT_INT5 W1 I • Edge-driven
• Polarity independently selected via the external interrupt polarity register bits (EXTPOL [3 0])EXT_INT4 U4 y p y p p y g (EXTPOL.[3:0]) IACK Y2 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 AA1 INUM2 W4 O Active interrupt identification number
• Valid during IACK for all active interrupts (not just external) INUM1 AA2 O • Valid during IACK for all active interrupts (not just external)
• Encoding order follows the interrupt-service fetch-packet ordering INUM0 AB1
• Encoding order follows the interrupt-service fetch-packet ordering LITTLE ENDIAN/BIG ENDIAN LENDIAN H3 I If high, LENDIAN selects little-endian byte/half-word addressing order within a word If low, LENDIAN selects big-endian addressing POWER-DOWN STATUS PD D3 O Power-down mode 2 or 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG are not part of external voltage supply or ground. See theclock PLLsection for information on how to connect these pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩresistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor.

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Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION HOST-PORT INTERFACE (HPI) HINT H26 O Host interrupt (from DSP to host) HCNTL1 F23 I Host control - - selects between control, address, or data registers HCNTL0 D25 I Host control - - selects between control, address, or data registers HHWIL C26 I Host half-word select - - first or second half-word (not necessarily high or low order) HBE1 E23 I Host byte select within word or half-word HBE0 D24 I Host byte select within word or half-word HR/W C23 I Host read or write select HD15 B13 HD14 B14 HD13 C14 HD12 B15 HD11 D15 HD10 B16 HD9 A17 HD8 B17 I/O/Z Host port data ( sed for transfer of data address and control)HD7 D16 I/O/Z Host-port data (usedfor transfer of data, address, and control) HD6 B18 HD5 A19 HD4 C18 HD3 B19 HD2 C19 HD1 B20 HD0 B21 HAS C22 I Host address strobe HCS B23 I Host chip select HDS1 D22 I Host data strobe 1 HDS2 A24 I Host data strobe 2 HRDY J24 O Host ready (from DSP to host) BOOT MODE BOOTMODE4 D8 BOOTMODE3 B4 BOOTMODE2 A3 I Boot mode BOOTMODE1 D5 I Boot mode BOOTMODE0 C4 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 11POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION EMIF - - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 AE22 CE2 AD26 O/Z Memory space enables

• Enabled by bits 24 and 25 of the word address CE1 AB24 O/Z • Enabled by bits 24 and 25 of the word address
• Only one asserted during any external data access CE0 AC26
• Only one asserted during any external data access BE3 AB25 Byte-enable control BE2 AA24 O/Z Byte-enable control
• Decoded from the two lowest bits of the internal address BE1 Y23 O/Z • Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory C b di tl t d t SDRAM d d it k i l (SDQM)BE0 AA26 y yp y
• Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF - - ADDRESS EA21 J26 EA20 K25 EA19 L24 EA18 K26 EA17 M26 EA16 M25 EA15 P25 EA14 P24 EA13 R25 EA12 T26 O/Z External address (word address)EA11 R23 O/Z External address (word address) EA10 U26 EA9 U25 EA8 T23 EA7 V26 EA6 V25 EA5 W26 EA4 V24 EA3 W25 EA2 Y26 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION EMIF - - DATA ED31 AB2 ED30 AC1 ED29 AA4 ED28 AD1 ED27 AC3 ED26 AD4 ED25 AF3 ED24 AE4 ED23 AD5 ED22 AF4 ED21 AE5 ED20 AD6 ED19 AE6 ED18 AD7 ED17 AC8 ED16 AF7 I/O/Z External dataED15 AD9 I/O/Z External data ED14 AD10 ED13 AF9 ED12 AC11 ED11 AE10 ED10 AE11 ED9 AF11 ED8 AE14 ED7 AF15 ED6 AE15 ED5 AF16 ED4 AC15 ED3 AE17 ED2 AF18 ED1 AF19 ED0 AC17 EMIF - - ASYNCHRONOUS MEMORY CONTROL ARE Y24 O/Z Asynchronous memory read enable AOE AC24 O/Z Asynchronous memory output enable AWE AD23 O/Z Asynchronous memory write enable ARDY W23 I Asynchronous memory ready input † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 13POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION EMIF - - SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SSADS AC20 O/Z SBSRAM address strobe SSOE AF21 O/Z SBSRAM output enable SSWE AD19 O/Z SBSRAM write enable SSCLK AD17 O SBSRAM clock EMIF - - SYNCHRONOUS DRAM (SDRAM) CONTROL SDA10 AD21 O/Z SDRAM address 10 (separate for deactivate command) SDRAS AF24 O/Z SDRAM row-address strobe SDCAS AD22 O/Z SDRAM column-address strobe SDWE AF23 O/Z SDRAM write enable SDCLK AE20 O SDRAM clock EMIF - - BUS ARBITRATION HOLD AA25 I Hold request from the host HOLDA A7 O Hold-request acknowledge to the host TIMER1 TOUT1 H24 O Timer 1 or general-purpose output TINP1 K24 I Timer 1 or general-purpose input TIMER0 TOUT0 M4 O Timer 0 or general-purpose output TINP0 K4 I Timer 0 or general-purpose input DMA ACTION COMPLETE STATUS DMAC3 D2 DMAC2 F4 O DMA action completeDMAC1 D1 O DMA action complete DMAC0 E2 MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 E25 I External clock source (as opposed to internal) CLKR1 H23 I/O/Z Receive clock CLKX1 F26 I/O/Z Transmit clock DR1 D26 I Receive data DX1 G23 O/Z Transmit data FSR1 E26 I/O/Z Receive frame sync FSX1 F25 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 L4 I External clock source (as opposed to internal) CLKR0 M2 I/O/Z Receive clock CLKX0 L1 I/O/Z Transmit clock DR0 J1 I Receive data DX0 R1 O/Z Transmit data FSR0 P4 I/O/Z Receive frame sync FSX0 P3 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 T2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV1 G2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 C11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 B9 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV4 A6 I Reserved for testing,pulldown with a dedicated 20-kΩ resistor RSV5 C8 O Reserved (leave unconnected,do notconnect to power or ground) RSV6 C21 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV7 B22 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV8 A23 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV9 E4 O Reserved (leave unconnected,do notconnect to power or ground) UNCONNECTED PINS D10 D21 NC G1 Unconnected pinsNC Unconnected pins † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 15POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION 3.3-V SUPPLY VOLTAGE PINS A10 A15 A18 A21 A22 D17 G24 G25 H25 J25 L25 N23 R26 T24 DV U24 S 3 3 V supply voltageDVDD W24 S 3.3-V supply voltage AB3 AB4 AB26 AC6 AC10 AC19 AC21 AC22 AC25 AD11 AD13 AD15 AD18 AE18 AE21 AF5 AF6 AF17 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION 1.8-V SUPPLY VOLTAGE PINS A12 A16 A20 B11 B12 B25 C15 C20 C24 D14 CV D18 S 1 8 V supply voltageCVDD D20 S 1.8-V supply voltage D23 J23 K23 M24 N25 P23 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 17POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION 1.8-V SUPPLY VOLTAGE PINS (CONTINUED) V23 AC4 AC9 AC12 AC13 AC18 AC23 AD3 CV AD8 S 1 8 V supply voltageCVDD AD14 S 1.8-V supply voltage AD24 AE2 AE8 AE12 AE25 AF12 GROUND PINS A13 A14 A25 A26 VSS B5 GND Ground pinsVSS B24 GND Ground pins B26 C13 C16 C17 C25 D13 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION GROUND PINS (CONTINUED) D19 E24 F24 G26 L23 L26 M23 N24 N26 P26 V R24 GND Ground pinsVSS T25 GND Ground pins U23 Y25 AA3 AA23 AB23 AC2 AC5 AC7 AC14 AC16 AD2 AD12 AD16 AD20 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 19POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 Signal Descriptions (Continued) SIGNAL PIN NO. TYPE† DESCRIPTIONSIGNAL NAME GJC TYPE† DESCRIPTION GROUND PINS (CONTINUED) AD25 AE1 AE3 AE7 AE9 AE13 AE16 AE19 AE23 VSS AE24 GND Ground pinsVSS AE26 GND Ground pins AF1 AF2 AF8 AF10 AF13 AF14 AF25 AF26 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000™ DSP-based applications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE) including Editor C/C++/Assembly Code Generation, andDebug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320™ DSP family member devices, including documentation. See this document for further information on TMS320™DSP documentation or any TMS320™DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320™DSP-related products from other companies in the industry. To receive TMS320™ DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000™ DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under “Development Tools”, select “Digital Signal Processors”.For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 21POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 device and development support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™DSP family devices and support tools. Each TMS320™DSP member has one of three prefixes: TMX, TMP , or TMS, and each SMJ320™DSP member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product developmentfrom engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below. Device development evolutionary flow: SMX Experimental device that is not necessarily repr esentative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SM/SMJ Fully-qualified production device Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS as well as SM/SMJ devices and TMDS development support tools have been characterized fully, and the quality and reliability of the device has been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP)have a greater failure rate than the standard production devices. Texas Instruments recommends that thesedevices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GNM) and temperature range (for example, M). Figure 4 provides a legend for reading the complete device name for many TMS320™ DSP family members. TMS320 is a trademark of Texas Instruments.

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6000 DSP:

NOTE: Not all speed, package, process, and temperature combinations are available. Figure 4. TMS320C6000™ Device Nomenclature (Including SM320C6201-EP) MicroStar BGA is a trademark of Texas Instruments.

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 23POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 documentation support Extensive documentation supports all TMS320™ DSP family devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware andsoftware applications. The following is a brief, descriptive list of support documentation specific to the C6000™ DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide(literature number SPRU189) describes the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide(literature number SPRU190) describes the functionality of the peripherals available on the C6000™DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access(EDMA) controller, expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Technical Brief(literature number SPRU197) gives an introduction to the C62x™/C67x™ devices, associated development tools, and third-party support. The tools support documentation is electronicallyavailable within the Code Composer Studio™ IDE. For a complete listing of the latest C6000™ DSP documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). C67x is a trademark of Texas Instruments.

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drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock. that for C6201, the EMI filter must be powered by the I/O voltage (3.3 V). a single clean power supply should power both the C62x™DSP device and the external clock oscillator circuit. input clock timing requirements.

000 PLLFREQ3

CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT. to be connected to a clean supply and the PLLGand PLLF terminals should be tied together. 000b, 001b, and 010b are reserved. Figure 5. PLL Block Diagram

Table 2. PLL Component Selection Table typical lock time is specified as 100μs, the maximum value may be as long as 250μs. supply is below the proper operating voltage. output buffers are powered up, thus, preventing bus contention with other chips on the board. between the core supply power up and the I/O supply power up can minimize the effects of this current draw. core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

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absolute maximum ratings over operating case temperature ranges (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT CVDD Supply voltage 1.71 1.8 1.89 V DVDD Supply voltage 3.14 3.30 3.46 V VSS Supply ground 0 0 0 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IOH High-level output current -- 1 2 mA IOL Low-level output current 12 mA TC Operating case temperature A version -- 4 0 105 _C electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage DVDD =M I N , IOH =M A X 2.4 V VOL Low-level output voltage DVDD =M I N , IOL =M A X 0.6 V II Input current‡ VI =V SS to DVDD ±10 uA IOZ Off-state output current VO =D VDD or 0 V ±10 uA IDD2V Supply current, CPU + CPU memory access§ CVDD =N O M , CPU clock = 167 MHz 380 mA IDD2V Supply current, peripherals§ CVDD =N O M , CPU clock = 167 MHz 240 mA IDD3V Supply current, I/O pins§ DVDD =N O M , CPU clock = 167 MHz 90 mA Ci Input capacitance 10 pF Co Output capacitance 10 pF ‡ TMS and TDI are not included due to internal pullups. TRSTis not included due to internal pulldown. § Measured with average activity(50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see theTMS320C6000 Power Consumption Summaryapplication report (literature number SPRA486).

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† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. Figure 9. CLKIN Timing Diagram § P = 1/CPU clock frequency in ns. ¶ The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. # PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. Figure 10. CLKOUT1 Timing Diagram

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ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 13 and Figure 14) NO - -200 UNITNO. MIN MAX UNIT 6 tsu(EDV-CKO1H) Setup time, read EDx valid before CLKOUT1 high 4 ns 7 th(CKO1H-EDV) Hold time, read EDx valid after CLKOUT1 high 0.8 ns 10 tsu(ARDY-CKO1H) Setup time, ARDY valid before CLKOUT1 high 3 ns 11 th(CKO1H-ARDY) Hold time, ARDY valid after CLKOUT1 high 1.8 ns † To ensure data setup time, simply program the strobe width wide enough.ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics over recommended operating conditions for asynchronous memory cycles‡ (see Figure 13 and Figure 14) NO PARAMETER - -200 UNITNO. PARAMETER MIN MAX UNIT 1 td(CKO1H-CEV) Delay time, CLKOUT1 high to CExvalid -- 0 . 2 4 ns 2 td(CKO1H-BEV) Delay time, CLKOUT1 high to BExvalid 4 ns 3 td(CKO1H-BEIV) Delay time, CLKOUT1 high to BExinvalid -- 0 . 2 ns 4 td(CKO1H-EAV) Delay time, CLKOUT1 high to EAx valid 4 ns 5 td(CKO1H-EAIV) Delay time, CLKOUT1 high to EAx invalid -- 0 . 2 ns 8 td(CKO1H-AOEV) Delay time, CLKOUT1 high to AOEvalid -- 0 . 2 4 ns 9 td(CKO1H-AREV) Delay time, CLKOUT1 high to AREvalid -- 0 . 2 4 ns 12 td(CKO1H-EDV) Delay time, CLKOUT1 high to EDx valid 4 ns 13 td(CKO1H-EDIV) Delay time, CLKOUT1 high to EDx invalid -- 0 . 2 ns 14 td(CKO1H-AWEV) Delay time, CLKOUT1 high to AWEvalid -- 0 . 2 4 ns ‡ The minimum delay is also the minimum output hold after CLKOUT1 high.

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SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15) NO - -200 UNITNO. MIN MAX UNIT 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 1.5 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 15 and Figure 16) NO PARAMETER - -200 UNITNO. PARAMETER MIN MAX UNIT 1 tosu(CEV-SSCLKH) Output setup time, CExvalid before SSCLK high 0.5P - - 1.3 ns 2 toh(SSCLKH-CEV) Output hold time, CExvalid after SSCLK high 0.5P - - 2.3 ns 3 tosu(BEV-SSCLKH) Output setup time, BExvalid before SSCLK high 0.5P - - 1.3 ns 4 toh(SSCLKH-BEIV) Output hold time, BExinvalid after SSCLK high 0.5P - - 2.3 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high 0.5P - - 1.3 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high 0.5P - - 2.3 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADSvalid before SSCLK high 0.5P - - 1.3 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADSvalid after SSCLK high 0.5P - - 2.3 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOEvalid before SSCLK high 0.5P - - 1.3 ns 12 toh(SSCLKH-OEV) Output hold time, SSOEvalid after SSCLK high 0.5P - - 2.3 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high 0.5P - - 1.3 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 0.5P - - 2.3 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWEvalid before SSCLK high 0.5P - - 1.3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWEvalid after SSCLK high 0.5P - - 2.3 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times.

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SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17) NO - -200 UNITNO. MIN MAX UNIT 7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 2.5 ns 8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 17 and Figure 18) NO PARAMETER - -200 UNITNO. PARAMETER MIN MAX UNIT 1 tosu(CEV-SSCLKH) Output setup time, CExvalid before SSCLK high 1.5P - - 3 ns 2 toh(SSCLKH-CEV) Output hold time, CExvalid after SSCLK high 0.5P - - 1.5 ns 3 tosu(BEV-SSCLKH) Output setup time, BExvalid before SSCLK high 1.5P - - 3 ns 4 toh(SSCLKH-BEIV) Output hold time, BExinvalid after SSCLK high 0.5P - - 1.5 ns 5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high 1.5P - - 3 ns 6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high 0.5P - - 1.5 ns 9 tosu(ADSV-SSCLKH) Output setup time, SSADSvalid before SSCLK high 1.5P - - 3 ns 10 toh(SSCLKH-ADSV) Output hold time, SSADSvalid after SSCLK high 0.5P - - 1.5 ns 11 tosu(OEV-SSCLKH) Output setup time, SSOEvalid before SSCLK high 1.5P - - 3 ns 12 toh(SSCLKH-OEV) Output hold time, SSOEvalid after SSCLK high 0.5P - - 1.5 ns 13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high 1.5P - - 3 ns 14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 0.5P - - 1.5 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWEvalid before SSCLK high 1.5P - - 3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWEvalid after SSCLK high 0.5P - - 1.5 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.

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timing requirements for synchronous DRAM cycles (see Figure 19) NO - -200 UNITNO. MIN MAX UNIT 7 tsu(EDV-SDCLKH) Setup time, read EDx valid before SDCLK high 0.5 ns 8 th(SDCLKH-EDV) Hold time, read EDx valid after SDCLK high 3 ns switching characteristics over recommended operating conditions for synchronous DRAM cycles† (see Figure 19- -Figure 24) NO PARAMETER - -200 UNITNO. PARAMETER MIN MAX UNIT 1 tosu(CEV-SDCLKH) Output setup time, CExvalid before SDCLK high 1.5P - - 3.5 ns 2 toh(SDCLKH-CEV) Output hold time, CExvalid after SDCLK high 0.5P - - 1 ns 3 tosu(BEV-SDCLKH) Output setup time, BExvalid before SDCLK high 1.5P - - 3.5 ns 4 toh(SDCLKH-BEIV) Output hold time, BExinvalid after SDCLK high 0.5P - - 1 ns 5 tosu(EAV-SDCLKH) Output setup time, EAx valid before SDCLK high 1.5P - - 3.5 ns 6 toh(SDCLKH-EAIV) Output hold time, EAx invalid after SDCLK high 0.5P - - 1 ns 9 tosu(SDCAS-SDCLKH) Output setup time, SDCASvalid before SDCLK high 1.5P - - 3.5 ns 10 toh(SDCLKH-SDCAS) Output hold time, SDCASvalid after SDCLK high 0.5P - - 1 ns 11 tosu(EDV-SDCLKH) Output setup time, EDx valid before SDCLK high 1.5P - - 3.5 ns 12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high 0.5P - - 1 ns 13 tosu(SDWE-SDCLKH) Output setup time, SDWEvalid before SDCLK high 1.5P - - 3.5 ns 14 toh(SDCLKH-SDWE) Output hold time, SDWEvalid after SDCLK high 0.5P - - 1 ns 15 tosu(SDA10V-SDCLKH) Output setup time, SDA10 valid before SDCLK high 1.5P - - 3.5 ns 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P - - 1 ns 17 tosu(SDRAS-SDCLKH) Output setup time, SDRASvalid before SDCLK high 1.5P - - 3.5 ns 18 toh(SDCLKH-SDRAS) Output hold time, SDRASvalid after SDCLK high 0.5P - - 1 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.

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Figure 21. SDRAM ACTV Command Figure 22. SDRAM DCAB Command

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† HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLDcan be an asynchronous input. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. ¶ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE,A O E,A W E, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE,A O E,A W E, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 25. HOLD/HOLDA Timing

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 41POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 RESET TIMING timing requirements for reset (see Figure 26) NO - -200 UNITNO. MIN MAX UNIT 1 tw(RST) Width of the RESETpulse (PLL stable)† 10 CLKOUT1 cycles1 tw(RST) Width of the RESETpulse (PLL needs to sync up)‡ 250 μs † This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. ‡ This parameter only applies to CLKMODE x4. The RESETsignal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250μs to stabilize following device power up or after PLLconfiguration has been changed. During that time, RESETmust be asserted to ensure proper device operation. See theClock PLLsection for PLL lock times. switching characteristics over recommended operating conditions during reset§¶ (see Figure 26) NO PARAMETER - -200 UNITNO. PARAMETER MIN MAX UNIT 2 tR(RST) Response time to change of value in RESETsignal 2 CLKOUT1 cycles 3 td(CKO1H-CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid -- 1 ns 4 td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 valid 10 ns 5 td(CKO1H-SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid -- 1 ns 6 td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK valid 10 ns 7 td(CKO1H-SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid -- 1 ns 8 td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK valid 10 ns 9 td(CKO1H-LOWIV) Delay time, CLKOUT1 high to low group invalid -- 1 ns 10 td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group valid 10 ns 11 td(CKO1H-HIGHIV) Delay time, CLKOUT1 high to high group invalid -- 1 ns 12 td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group valid 10 ns 13 td(CKO1H-ZHZ) Delay time, CLKOUT1 high to Z group high impedance -- 1 ns 14 td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group valid 10 ns § Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 High group consists of: HINT Z group consists of: EA[21:2], ED[31:0], CE[3:0] , BE[3:0],A R E,A W E,A O E, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE,H D [ 1 5 : 0 ] ,C L K X 0 ,C L K X 1 ,F S X 0 ,F S X 1 ,D X 0 ,D X 1 ,C L K R 0 ,C L K R 1 ,F S R 0 ,a n dF S R 1 . ¶ HRDY is gated by input HCS. If HCS= 0 at device reset, HRDYbelongs to the high group. If HCS= 1 at device reset, HRDYbelongs to the low group.

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‡ HRDY is gated by input HCS. If HCS= 0 at device reset, HRDYbelongs to the high group. If HCS= 1 at device reset, HRDYbelongs to the low group. Figure 26. Reset Timing

be connected to asynchronous inputs. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2× CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. Figure 27. Interrupt Timing

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HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 28, Figure 29, Figure 30, and Figure 31) NO - -200 UNITNO. MIN MAX UNIT 1 tsu(SEL-HSTBL) Setup time, select signals§ valid before HSTROBElow 4 ns 2 th(HSTBL-SEL) Hold time, select signals§ valid after HSTROBElow 2 ns 3 tw(HSTBL) Pulse duration, HSTROBElow 2P ns 4 tw(HSTBH) Pulse duration, HSTROBEhigh between consecutive accesses 2P ns 10 tsu(SEL-HASL) Setup time, select signals§ valid before HASlow 4 ns 11 th(HASL-SEL) Hold time, select signals§ valid after HASlow 2 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBEhigh 3 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBEhigh 2 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBElow after HRDYlow. HSTROBEshould not be inactivated until HRDYis active (low); otherwise, HPI writes will not complete properly. 1 ns 18 tsu(HASL-HSTBL) Setup time, HASlow before HSTROBElow 2 ns 19 th(HSTBL-HASL) Hold time, HASlow after HSTROBElow 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1XOR HDS2)] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need toadjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics over recommended operating conditions during host-port interface cycles†‡ (see Figure 28, Figure 29, Figure 30, and Figure 31) NO PARAMETER - -200 UNITNO. PARAMETER MIN MAX UNIT 5 td(HCS-HRDY) Delay time, HCSto HRDY¶ 1 9 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBElow to HRDYhigh# 3 12 ns 7 toh(HSTBL-HDLZ) Output hold time, HD low impedance after HSTROBElow for an HPI read 4 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDYlow P- -3 P+3 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBEhigh 2 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBEhigh to HD high impedance 3 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBElow to HD valid 2 12 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBEhigh to HRDYhigh|| 3 12 ns 20 td(HASL-HRDYH) Delay time, HASlow to HRDYhigh 3 12 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1XOR HDS2)] OR HCS. ‡ The effects of internal clock jitter are included at test. There is no need toadjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ HCS enables HRDY, and HRDYis always low when HCSis high. The case where HRDYgoes high when HCSfalls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDYremains high until the DMA auxiliary channel loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDYremains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDYsignal.

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† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1XOR HDS2)] OR HCS. Figure 30. HPI Write Timing (HASNot Used, Tied High) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1XOR HDS2)] OR HCS. Figure 31. HPI Write Timing (HASUsed)

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 47POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡(see Figure 32) NO - -200 UNITNO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P- -1¶ ns 5 t Setup time external FSR high before CLKR low CLKR int 9 ns5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 2 ns 6 t Hold time external FSR high after CLKR low CLKR int 6 ns6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3 ns 7 t Setup time DR valid before CLKR low CLKR int 8 ns7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0 ns 8 t Hold time DR valid after CLKR low CLKR int 3 ns8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4 ns 10 t Setup time external FSX high before CLKX low CLKX int 9 ns10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 2 ns 11 t Hold time external FSX high after CLKX low CLKX int 6 ns11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. § The maximum bit rate for the C6202/02B/03 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. ¶ The minimum CLKR/X pulse duration is either (P- -1) or 4 ns, whicheveris larger. For example, when running parts at 200 MHz (P = 5 ns), use 4 ns as the minimum CLKR/X pulse duration. When running parts at100 MHz (P = 10 ns), use (P- -1) = 9 ns as the minimum CLKR/X pulse duration.

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004

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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP†‡§ (see Figure 32) NO PARAMETER - -200 UNITNO. PARAMETER MIN MAX UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 3 10 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P¶ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C- -1 . 3# C+1 # ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -- 2 3 ns 9 t Dela time CLKX high to internal FSX alid CLKX int -- 2 3 ns9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 9 ns 12 t Disable time, DX highi mpedance following last data bitfrom CLKX int -- 1 4 ns12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX ext 3 9 ns 13 t Dela time CLKX high to DX alid CLKX int -- 1 4 ns13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 3 9 ns 14 t Delay time, FSX high to DX valid FSX int -- 1 3 ns14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ¶ The maximum bit rate for the C6202/02B/03 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C= H o r L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

Figure 32. McBSP Timing Diagram

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Figure 33. FSR Timing When GSYNC = 1 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A - - MAY 2003 - - REVISED JANUARY 2004 51POST OFFICE BOX 1443•HOUSTON, TEXAS 77251- -1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34) - -200 NO. PARAMETER MASTER§ SLAVE UNITNO. PARAMETER MIN MAX MIN MAX UNIT 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ T- -2 T+3 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# L- -2 L+3 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid -- 2 4 3P + 4 5P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low L- -2 L+3 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

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Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally.

Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally.

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Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally.

Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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Figure 38. DMAC Timing Diagram † P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. Figure 39. Timer Timing Diagram Figure 40. Power-Down Timing

Figure 41. JTAG Test-Port Timing Diagram

www.ti.com 24-May-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SM320C6201GJCA20EP ACTIVE FCBGA GJC 352 21 TBD SNPB Level-4-220C-72 HR V62/04606-01XA ACTIVE FCBGA GJC 352 21 TBD SNPB Level-4-220C-72 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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