SM320C6000PYP167

TMS320C6713_05 TI | Alldatasheet

Document overview

• Manufacturer or author: pROVIDED bY alldatasheet.com(free datasheet download site)
• PDF pages: 148

Technical content

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Highest-Performance Floating-Point Digital Signal Processor (DSP) − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word − 225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock Rates − 4.4-, 5-, 6-Instruction Cycle Times − 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS − Rich Peripheral Set, Optimized for Audio − Highly Optimized C/C++ Compiler − Extended Temperature Devices Available /C0068Advanced Very Long Instruction Word (VLIW) TMS320C67x  DSP Core − Eight Independent Functional Units: − Two ALUs (Fixed-Point) − Four ALUs (Floating- and Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional /C0068Instruction Set Features − Native Instructions for IEEE 754 − Single- and Double-Precision − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization /C0068L1/L2 Memory Architecture − 4K-Byte L1P Program Cache (Direct-Mapped) − 4K-Byte L1D Data Cache (2-Way) − 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM /C0068Device Configuration − Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot − Endianness: Little Endian, Big Endian /C006832-Bit External Memory Interface (EMIF) − Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM − 512M-Byte Total Addressable External Memory Space /C0068Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) /C006816-Bit Host-Port Interface (HPI) /C0068Two McASPs − Two Independent Clock Zones Each (1 TX and 1 RX) − Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones − Each Clock Zone Includes: − Programmable Clock Generator − Programmable Frame Sync Generator − TDM Streams From 2-32 Time Slots − Support for Slot Size: 8, 12, 16, 20, 24, 28, 32 Bits − Data Formatter for Bit Manipulation − Wide Variety of I2S and Similar Bit Stream Formats − Integrated Digital Audio Interface Transmitter (DIT) Supports: − S/PDIF, IEC60958-1, AES-3, CP-430 Formats − Up to 16 transmit pins − Enhanced Channel Status/User Data − Extensive Error Checking and Recovery /C0068Two Inter-Integrated Circuit Bus (I2C Bus) Multi-Master and Slave Interfaces /C0068Two Multichannel Buffered Serial Ports: − Serial-Peripheral-Interface (SPI) − High-Speed TDM Interface − AC97 Interface /C0068Two 32-Bit General-Purpose Timers /C0068Dedicated GPIO Module With 16 pins (External Interrupt Capable) /C0068Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module /C0068IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible /C0068208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) /C0068272-BGA Packages (GDP) /C00680.13-µm/6-Level Copper Metal Process − CMOS Technology /C00683.3-V I/Os, 1.2-V‡ Internal (GDP & PYP) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated TMS320C67x and PowerPAD are trademarks of Texas Instruments. I2C Bus is a trademark of Philips Electronics N.V. Corporation /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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absolute maximum ratings over operating case electrical characteristics over recommended ranges of supply voltage and operating case temperature 98. general-purpose input/output (GPIO) port timing 141. . . .

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS186J device-specific data sheet to make it an SPRS186K revision. It also highlights technical changes made to SPRS186K to generate SPRS186L; these changes are marked by “[Revision L]” in the Revision History table below. Removed device−specific information/data for TMS320C6713B from this document. For information/data on the TMS320C6713B device, see the TMS320C6713B Floating−Point Digital Signal Processor Data Manual SPRS294. Scope: Applicable updates to the C67x device family, specifically relating to the C6713 device, have been incor- porated. This device is now at the Production Data (PD) stage of development. Updated information on McASP, McBSP and JTAG for clarification. Changed Pin Description for A12 and B11 (Revisions K and L). TI Recom- mends for new designs that the following pins be configured as such: /C0068Pin A12 connected directly to CVDD (core power) /C0068Pin B11 connected directly to Vss (ground) PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 6 Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) table: Updated Signal Name for Ball No. A12 Updated Signal Name for Ball No. B11

10 PYP PowerPAD QFP package (top view):

33 Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section: Removed “CE1 width 32−bit” from Functional Description for “00” in HD4:3 Configuration Pin

37 Table 22 Peripheral Pin Selection Matrix:

Updated/changed MCBSP0DIS (DEVCFG bit) from “ACLKKO” to “ACLKXO”

46 Configuration Example F (1 McBSP + HPI + 1 McASP)

Updated from “McBSP1DIS = 1” to “McBSP1DIS = 0”

50 Terminal Functions, Host Port Interface section:

Associated footnote with HD15/GP[15] pin Removed “CE1 width 32−bit” from Description for “00” in Bootmode HD[4:3]

55 Terminal Functions table, Timer 1 section:

Updated Description for TINP1/AHCLKX0 Signal Name

57 Terminal Functions table, Reserved for Test section:

Updated Description for RSV, 181 (PYP), A12 (GDP) Updated Description for RSV, 180 (PYP), B11 (GDP)

57 Terminal Functions, Reserved for Test section:

Updated/changed Description for RSV Signal Name, A12 GDP (to “recommended” ) − [Revision L] Updated/changed Description for RSV Signal Name, B11 GDP (to “recommended” ) − [Revision L]

66 Device support, device and development-support tool nomenclature section:

Updated figure for clarity

67 Device Support, document support section:

Updated paragraphs for clarity

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 94 IEEE 1149.1 JTAG Compatibility Statement section: Updated/added paragraphs for clarity

97 Recommended Operating Conditions:

Added VOS, Maximum voltage during overshoot row and associated footnote Added VUS, Maximum voltage during undershoot row and associated footnote

100 Parameter Measurement Information, AC transient rise/fall time specifications section:

Added AC Transient Specification Rise Time figure Added AC Transient Specification Fall Time figure

122 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING:

timing requirements for McASP section: Updated Parameter No. 3, tc(ACKRX), from “33” to “greater of 2P or 33 ns” and added associated footnote switching characteristics over recommended operating conditions for McASP section: Updated Parameter No. 11, tc(ACKRX), from “33” to “greater of 2P or 33 ns” and added associated footnote 123−124 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING section: Updated McASP Input and Output drawings 132 MULTICHANNEL BUFFERED SERIAL PORT TIMING, switching characteristics over recommended operating conditions for McBSP section: Updated McBSP Timings figure

144 Mechanical Data section:

Added statement to the Packaging Information section

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 GDP 272-Ball BGA package (bottom view) /C0086/C0083/C0083/C0086/C0083/C0083 /C0067/C0076/C0075/C0073/C0078 /C0067/C0086/C0068/C0068 /C0086/C0083/C0083/C0086/C0083/C0083 /C0086/C0083/C0083/C0067/C0086/C0068/C0068/C0068/C0086/C0068/C0068 /C0067/C0069/C0050/C0069/C0065/C0052 /C0068/C0086/C0068/C0068/C0069/C0068/C0049/C0055 /C0069/C0065/C0054 /C0068/C0086 /C0068/C0068 /C0069/C0065/C0049/C0051/C0086/C0083/C0083/C0069/C0065/C0049/C0053/C0069/C0065/C0049/C0057/C0067/C0069/C0049/C0067/C0086/C0068/C0068/C0086/C0083/C0083 /C0071/C0080/C0091/C0053/C0093 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/C0086/C0083/C0083/C0068/C0086/C0068/C0068/C0067/C0086/C0068/C0068/C0068/C0086/C0068/C0068/C0086/C0083/C0083/C0086/C0083/C0083/C0067/C0086/C0068/C0068/C0067/C0086/C0068/C0068/C0068/C0086/C0068/C0068/C0086/C0083/C0083/C0067/C0086/C0068/C0068/C0067/C0086/C0068/C0068/C0068/C0086/C0068/C0068/C0086/C0083/C0083/C0069/C0065/C0050/C0049 /C0066/C0069/C0049/C0086/C0083/C0083 /C0086/C0083/C0083/C0067/C0086/C0068/C0068/C0067/C0086/C0068/C0068/C0082/C0083/C0086 /C0086/C0083/C0083/C0069/C0077/C0085/C0048 /C0067/C0076/C0075/C0079/C0085/C0084/C0051 /C0067/C0086/C0068/C0068/C0082/C0083/C0086 /C0086/C0083/C0083/C0067/C0086/C0068/C0068/C0067/C0086/C0068/C0068/C0068/C0086/C0068/C0068/C0086/C0083/C0083/C0072/C0068/C0050/C0047 /C0065/C0070/C0083/C0088/C0049/C0068/C0086/C0068/C0068/C0072/C0068/C0049/C0047 /C0065/C0088/C0082/C0049/C0091/C0055/C0093 /C0069/C0068/C0050/C0050 /C0069/C0068/C0050/C0049 /C0069/C0068/C0050/C0051 /C0071/C0080/C0091/C0054/C0093 /C0040/C0069/C0088/C0084/C0095/C0073/C0078/C0084/C0054/C0041 /C0067/C0076/C0075/C0083/C0049/C0047 /C0083/C0067/C0076/C0049/C0086/C0083/C0083/C0071/C0080/C0091/C0055/C0093 /C0040/C0069/C0088/C0084/C0095/C0073/C0078/C0084/C0055/C0041 /C0086/C0083/C0083 /C0086/C0083/C0083 /C0069/C0068/C0049/C0051 /C0069/C0068/C0049/C0053 /C0069/C0068/C0049/C0052/C0086/C0083/C0083 /C0086/C0083/C0083 /C0072/C0068/C0083/C0049/C0047 /C0065/C0088/C0082/C0049/C0091/C0054/C0093 /C0072/C0065/C0083/C0047 /C0065/C0067/C0076/C0075/C0088/C0049 /C0072/C0068/C0048/C0047 /C0065/C0088/C0082/C0049/C0091/C0052/C0093 /C0069/C0068/C0050/C0052 /C0069/C0068/C0050/C0053 /C0068/C0086/C0068/C0068 /C0067/C0086/C0068/C0068/C0068/C0086/C0068/C0068/C0069/C0068/C0050/C0055 /C0069/C0068/C0050/C0054 /C0067/C0086/C0068/C0068 /C0072/C0068/C0083/C0050/C0047 /C0065/C0088/C0082/C0049/C0091/C0053/C0093/C0086/C0083/C0083 /C0072/C0067/C0083/C0047 /C0065/C0088/C0082/C0049/C0091/C0050/C0093 /C0084/C0079/C0085/C0084/C0049/C0047 /C0065/C0088/C0082/C0048/C0091/C0052/C0093 /C0084/C0073/C0078/C0080/C0049/C0047 /C0065/C0072/C0067/C0076/C0075/C0088/C0048/C0068/C0086/C0068/C0068/C0067/C0086/C0068/C0068 /C0067/C0086/C0068/C0068/C0068/C0086/C0068/C0068/C0069/C0068/C0049/C0049 /C0069/C0068/C0049/C0050 /C0084/C0079/C0085/C0084/C0048/C0047 /C0065/C0088/C0082/C0048/C0091/C0050/C0093 /C0084/C0073/C0078/C0080/C0048/C0047 /C0065/C0088/C0082/C0048/C0091/C0051/C0093 /C0067/C0076/C0075/C0088/C0048/C0047 /C0065/C0067/C0076/C0075/C0088/C0048/C0086/C0083/C0083 /C0086/C0083/C0083/C0069/C0068/C0057 /C0086/C0083/C0083/C0069/C0068/C0049/C0048/C0086/C0083/C0083/C0069/C0068/C0050/C0056 /C0069/C0068/C0050/C0057 /C0069/C0068/C0051/C0048 /C0086/C0083/C0083/C0072/C0067/C0078/C0084/C0076/C0048/C0047 /C0065/C0088/C0082/C0049/C0091/C0051/C0093 /C0072/C0067/C0078/C0084/C0076/C0049/C0047 /C0065/C0088/C0082/C0049/C0091/C0049/C0093 /C0072/C0082/C0047/C0087/C0047 /C0065/C0088/C0082/C0049/C0091/C0048/C0093 /C0070/C0083/C0088/C0048/C0047 /C0065/C0070/C0083/C0088/C0048 /C0083/C0068/C0065/C0048 /C0086/C0083/C0083 /C0086/C0083/C0083/C0069/C0068/C0054 /C0069/C0068/C0055 /C0069/C0068/C0056 /C0067/C0076/C0075/C0082/C0048/C0047 /C0065/C0067/C0076/C0075/C0082/C0048/C0086/C0083/C0083 /C0068/C0088/C0048/C0047 /C0065/C0088/C0082/C0048/C0091/C0049/C0093 /C0083/C0067/C0076/C0048 /C0069/C0068/C0051/C0049 /C0086/C0083/C0083/C0068/C0086/C0068/C0068 /C0072/C0082/C0068/C0089/C0047 /C0065/C0067/C0076/C0075/C0082/C0049 /C0072/C0072/C0087/C0073/C0076/C0047 /C0065/C0070/C0083/C0082/C0049 /C0070/C0083/C0082/C0048/C0047 /C0065/C0070/C0083/C0082/C0048 /C0067/C0076/C0075/C0082/C0049/C0047 /C0065/C0088/C0082/C0048/C0091/C0054/C0093 /C0068/C0082/C0049/C0047 /C0083/C0068/C0065/C0049/C0086/C0083/C0083 /C0086/C0083/C0083/C0068/C0086/C0068/C0068/C0069/C0068/C0052 /C0069/C0068/C0053 /C0068/C0082/C0048/C0047 /C0065/C0088/C0082/C0048/C0091/C0048/C0093/C0068/C0086/C0068/C0068 /C0086/C0083/C0083 /C0070/C0083/C0082/C0049/C0047 /C0065/C0088/C0082/C0048/C0091/C0055/C0093 /C0072/C0079/C0076/C0068/C0072/C0079/C0076/C0068/C0065/C0066/C0085/C0083 /C0082/C0069/C0081 /C0072/C0073/C0078/C0084/C0047 /C0071/C0080/C0091/C0049/C0093 /C0070/C0083/C0088/C0049/C0068/C0088/C0049/C0047 /C0065/C0088/C0082/C0048/C0091/C0053/C0093 /C0067/C0076/C0075/C0088/C0049/C0047 /C0065/C0077/C0085/C0084/C0069/C0048/C0067/C0086/C0068/C0068 /C0067/C0086/C0068/C0068/C0069/C0068/C0050 /C0069/C0068/C0051 /C0067/C0086/C0068/C0068 /C0067/C0086/C0068/C0068/C0086/C0083/C0083 /C0067/C0076/C0075/C0083/C0048/C0047 /C0065/C0072/C0067/C0076/C0075/C0082/C0048/C0067/C0086/C0068/C0068 /C0067/C0086/C0068/C0068/C0069/C0068/C0048 /C0069/C0068/C0049 /C0086/C0083/C0083 /C0083/C0104/C0097/C0100/C0105/C0110/C0103 /C0100/C0101/C0110/C0111/C0116/C0101/C0115 /C0116/C0104/C0101 /C0071/C0068/C0080 /C0112/C0097/C0099/C0107/C0097/C0103/C0101 /C0112/C0105/C0110 /C0102/C0117/C0110/C0099/C0116/C0105/C0111/C0110/C0115 /C0116/C0104/C0097/C0116 /C0100/C0114/C0111/C0112 /C0111/C0117/C0116 /C0111/C0110 /C0116/C0104/C0101 /C0080/C0089/C0080 /C0112/C0097/C0099/C0107/C0097/C0103/C0101/C0046

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Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) Shading denotes the GDP package pin functions that drop out on the PYP package.

Table 1. Terminal Assignments for the 272-Ball GDP Package (in Order of Ball No.) (Continued) Shading denotes the GDP package pin functions that drop out on the PYP package.

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Shading denotes the GDP package pin functions that drop out on the PYP package.

Shading denotes the GDP package pin functions that drop out on the PYP package.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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PYP PowerPAD  QFP package (top view) TRST HD5/AHCLKX1 HD8/GP[8] HD6/AHCLKR1 HD7/GP[3] HD9/GP[9] HD10/GP[10] HD11/GP[11] HD12/GP[12] HD13/GP[13] HD14/GP[14] HD15/GP[15] NMI RSV RSV EMU1 EMU0 TDO TDI TMS TCK RSV RSV CLKIN CLKMODE0 HD4/GP[0] HD2/AFSX1 HD3/AMUTE1 HD1/AXR1[7] HD0/AXR1[4] HCNTL0/AXR1[3] HCNTL1/AXR1[1] HR/ HHWIL/AFSR1 BUSREQ HINT ED0 ED1 ED2 ED3 ED5 ED4 ED8 ED7 ED6 ED10 ED9 ED12 ED11 ED14 ED15 ED13 EA21 EA20 EA19 EA17 EA18 EA15 EA12 EA16 EA13 EA14 EA11 CLKOUT2/GP[2] ECLKIN ECLKOUT EA10 EA9 EA7 EA8 EA6 EA5 EA4 EA3 EA2 ARDY 104 103 102 101 100 53 52 GP4/AMUTEIN1 GP6 GP5/AMUTEIN0 DD GP7 CLKS1/SCL1 TINP1/AHCLKX0 TOUT1/AXR0[4] CLKX0/ACLKX0 TINP0/AXR0[3] TOUT0/AXR0[2] CLKR0/ACLKR0 DX0/AXR0[1] FSX0/AFSX0 FSR0/AFSR0 DR0/AXR0[0] CLKS0/AHCLKR0 FSX1 DX1/AXR0[5] CLKX1/AMUTE0 CLKR1/AXR0[6] DR1/SDA1 FSR1/AXR0[7] SCL0 SDA0 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 RESET /GP[1] W/AXR1[0] HAS/ACLKX1 HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 CE3 CE2 CE1 CE0 BE1 BE0 HOLDA HOLD ARE /SDCAS /SSADS AOE /SDRAS /SSOE AWE /SDWE /SSWE DV DD DV DD RSV PLLHV CLKOUT3 DV DV DD DDDV DDDV DDDV DDDV DDDV DV DD DV DD DV DD DV DD DDCV CV DD DV DD DV DD CV DD CV DD CV DD CV DD DDCV DDCV DDCV CV DD CV DD DDCV CV DD DDCV DDCV DDCV DDCV CV DD CV DD DDCV DDCV CV DD CV DD VSS VSS VSS SSV VSS SSV SSV SSV SSV SSV SSV SSV SSV SSV SSV VSS SSV VSS VSS SSV VSS SSV SSV VSS VSS VSS SSV VSS RSV VSS SSV DDCV DV DD DDDV DDCV DDCV DDDV SSV DDCV DV DD VSS CV DD DDDV DDCV VSS CV DD CV DD PYP 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) (TOP VIEW) VSS CV DD VSS NOTE: All linear dimensions are in millimeters. This pad is electrically and thermally connected to the backside of the die. For the TMS320C6713 208-Pin PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal pad is externally flush with the mold compound. 6,79 8,30 Exposed Thermal PAD 6,79 8,30

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

description

The TMS320C67x /C0116 DSPs (including the TMS320C6713 device†) compose the floating-point DSP generation in the TMS320C6000/C0116 DSP platform. The C6713 device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713 delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). The C6713 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-Byte memory space that is shared between program and data space. 64K Bytes of the 256K Bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K Bytes in L2 serves as mapped SRAM. The C6713 has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713 has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713 allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The TMS320C6713 device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSP/C0116 set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio/C0116 Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS/C0116 kernel. TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments. † Throughout the remainder of this document, the TMS320C6713 shall be referred to as C6713 or 13.

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details on the C67x DSP device part numbers and part numbering, see Figure 12. Table 2. Characteristics of the C6713 Processor BSDL File For the C6713 BSDL file, contact your Field Sales Representative. check (high-frequency) circuit. ‡ This value is compatible with existing 1.26−V designs. standard warranty. Production processing does not necessarily include testing of all parameters. C67x is a trademark of Texas Instruments.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block and CPU (DSP core) diagram Test C67x  CPU Data Path B B Register File Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File Power-Down Logic L1P Cache Direct Mapped 4K Bytes Total Control Registers Control Logic L1D Cache 2-Way Set Associative 4K Bytes In-Circuit Emulation Interrupt Control C6713 Digital Signal Processor † In addition to fixed-point instructions, these functional units execute floating-point instructions. Enhanced DMA Controller (16 channel) L2 Cache/ Memory

4 Banks

(up to 4-Way) Clock Generator and PLL x4 through x25 Multiplier /1 through /32 Dividers Memory 192K Bytes EMIF McASP1 McASP0 McBSP1 McBSP0 I2C1 I2C0 Timer 1 Timer 0 GPIO HPI Pin Multiplexing McBSPs interface to: −SPI Control Port −High-Speed TDM Codecs −AC97 Codecs −Serial EEPROM EMIF interfaces to: −SDRAM −SBSRAM −SRAM, −ROM/Flash, and −I/O devices McASPs interface to: −I2S Multichannel ADC, DAC, Codec, DIR −DIT : Multiple Outputs

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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CPU (DSP core) description The TMS320C6713 floating-point digital signal processor is based on the C67x CPU. The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

† In addition to fixed-point instructions, these functional units execute floating-point instructions. Figure 1. TMS320C67x CPU (DSP Core) Data Paths

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Table 3 shows the memory map address ranges of the C6713 device. Table 3. TMS320C6713 Memory Map Summary † The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.

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Overview Reference Guide (literature number SPRU190). Table 4. EMIF Registers Table 5. L2 Cache Registers

Table 6. Interrupt Selector Registers Table 7. Device Registers Allows the user to control peripheral selection. user control of device operation. Description section of this data sheet. Table 8. EDMA Parameter RAM† † The C6713 device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.

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For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 3. Figure 3. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event Table 9. EDMA Registers

Table 10. Quick DMA (QDMA) and Pseudo Registers† Table 11. PLL Controller Registers

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Table 12. McASP0 and McASP1 Registers allows transmit to be reset independently from receive. allows transmit to be reset independently from receive.

Table 12. McASP0 and McASP1 Registers (Continued)

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† The transmit buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register). ‡ The receive buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register). Table 13. I2C0 and I2C1 Registers

Table 14. HPI Registers Table 15. Timer 0 and Timer 1 Registers input clock cycles to count. Table 16. McBSP0 and McBSP1 Registers

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Table 17. GPIO Registers

† These external pins are applicable to the GDP package only. Reference Guide (literature number SPRU646). § All of these pins are external interrupt sources. For more details, see the External Interrupt Sources section of this data sheet. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 4. CPU (DSP Core) and Peripheral Signals

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NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources sections of this data sheet. Figure 5. Peripheral Signals

†These external pins are applicable to the GDP package only. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. Figure 5. Peripheral Signals (Continued)

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NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.

NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

On the C6713 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset. device configurations at device reset Table 18 describes the C6713 device configuration pins, which are set up via internal or external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8), and CLKMODE0 pin. These configuration pins must be in the desired state until reset is released. For proper device operation of the C6713 device, do not oppose the HD [15, 13:9, 7, 1, 0] pins with the external pullups/pulldowns at reset. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section of this data sheet.

Table 18. Device Configurations Pins at Device Reset (HD[4:3], HD8, and CLKMODE0)† bootmode section of this data sheet. This pin must be pulled to the correct level even after reset. not oppose these pins with external pullups/pulldowns at reset; however, the HD[6, 5, 2] pins can be opposed and driven during reset.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

DEVICE CONFIGURATIONS (CONTINUED) peripheral pin selection at device reset Some C6713 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:8, 3, 1, 0] and McASP1). /C0068HPI, McASP1, and GPIO peripherals The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or McASP1 peripheral pins and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 19). Table 19. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins)† 0 √ HPI_EN = 0 HPI pins are disabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as McASP1 and GPIO pins, respectively. To use the GPIO pins, the appropriate bits in the GPEN and GPDIR registers need to be configured. 1 √ HPI_EN = 1 HPI pins are enabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins function as HPI pins. † The HPI_EN (HD[14]) pin cannot be controlled via software.

Table 20. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 − 0x019C02FF] † Do not write non-zero values to these bit locations. Table 21. Device Configuration (DEVCFG) Register Selection Bit Descriptions 31:5 Reserved Reserved. Do not write non-zero values to these bit locations.

4 EKSRC

EMIF input clock source bit. Determines which clock signal is used as the EMIF input clock.

3 TOUT1SEL

Timer 1 output (TOUT1) pin function select bit. selection bits in the DEVCFG register. 1 = The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]). The Timer 1 module is still active.

2 TOUT0SEL

Timer 0 output (TOUT0) pin function select bit. selection bits in the DEVCFG register. 1 = The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]). The Timer 0 module is still active.

1 MCBSP0DIS

Multichannel Buffered Serial Port 0 (McBSP0) disable bit. Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled. ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default). ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled.

0 MCBSP1DIS

Multichannel Buffered Serial Port 1 (McBSP1) disable bit. Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled. peripheral pins (AXR0[7:5] and AMUTE0) are enabled.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of these pins are configured by software via the device configuration register (DEVCFG), and the others (specifically, the HPI pins) are configured by external pullup/pulldown resistors only at reset. The muxed pins that are configured by software can be programmed to switch functionalities at any time. The muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 22 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register. Table 23 identifies the multiplexed pins on the C6713 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure the specific multiplexed functions.

Table 22. Peripheral Pin Selection Matrix†

1 None All

0 None All

1 AXR0[2] NO

1 AXR0[4] NO

† Gray blocks indicate that the peripheral is not affected by the selection bit.

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Table 23. C6713 Device Multiplexed/Shared Pins McBSP0 peripheral pins).CLKX0/ACLKX0 16 G3 McBSP0 peripheral pins). (disabling the McBSP1 peripheral pins).

Table 23. C6713 Device Multiplexed/Shared Pins (Continued) McASP0 peripheral forces an output). peripheral output pin function).

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peripheral output pin function). Figure 6 through Figure 11 illustrate examples of peripheral selections that are configurable on this device.

Shading denotes a peripheral module not available for this configuration. Figure 6. Configuration Example A (2 I2C + 2 McASP + GPIO)

42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Shading denotes a peripheral module not available for this configuration. Figure 7. Configuration Example B (1 I2C + 1 McBSP + 2 McASP + GPIO)

Shading denotes a peripheral module not available for this configuration. Figure 8. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO]

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Shading denotes a peripheral module not available for this configuration. Figure 9. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers]

Shading denotes a peripheral module not available for this configuration. Figure 10. Configuration Example E (1 I2C + HPI + 1 McASP)

46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Shading denotes a peripheral module not available for this configuration. Figure 11. Configuration Example F (1 McBSP + HPI + 1 McASP)

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DEVICE CONFIGURATIONS (CONTINUED) debugging considerations It is recommended that external connections be provided to peripheral selection/device configuration pins, including HD[14, 8, 4, 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the HPI data bus (HD[15, 13:9, 7:5, 2:0]. For proper device operation of the HD[15, 13:9, 7, 1, 0], do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these HD[15, 13:9, 7, 1, 0] non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For a list of routed out, 3-stated, or not-driven pins recommended for external pullup/pulldown resistors, and internal pullup/pulldown resistors for all device pins, etc., see the Terminal Functions table. However, the HD[6, 5, 2] non-configuration pins can be opposed and driven during reset.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet. Terminal Functions SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION CLOCK/PLL CONFIGURATION CLKIN 204 A3 I IPD Clock Input CLKOUT2/GP[2] 82 Y12 O/Z IPD Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z) CLKOUT3 184 D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller. CLKMODE0 205 C4 I IPU Clock generator input clock source select 0 − Reserved, do not use. 1 – CLKIN square wave [default] For proper device operation, this pin must be either left unconnected or externally pulled up with a 1-kΩ resistor. PLLHV 202 C5 A Analog power (3.3 V) for PLL (PLL Filter) JTAG EMULATION TMS 192 B7 I IPU JTAG test-port mode select TDO 187 A8 O/Z IPU JTAG test-port data out TDI 191 A7 I IPU JTAG test-port data in TCK 193 A6 I IPU JTAG test-port clock TRST § 197 B6 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. EMU5 — B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 — C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 — B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 — D3 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 185 B9 I/O/Z IPU Emulation [1:0] pins

• Select the device functional mode of operation EMU[1:0] Operation

00 Boundary Scan/Functional Mode (see Note)

01 Reserved

10 Reserved

11 Emulation/Functional Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet)EMU1 EMU0 185 186 D9 I/O/Z IPU JTAG Compatibility Statement section of this data sheet) The DSP can be placed in Functional mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Functional mode. For the Boundary Scan mode drive EMU[1:0] and RESET pins low. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] § To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 49POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION RESETS AND INTERRUPTS RESET 176 A13 I IPU Device reset. When using Boundary Scan mode, drive the EMU[1:0] and RESET pins low. NMI 175 C13 I IPD Nonmaskable interrupt

• Edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. GP7 7 E3 General-purpose input/output pins (I/O/Z) which also function as external interrupts GP6 2 D2 interrupts
• Edge-driven Polarity independently selected via the External Interrupt Polarity Register GP5/ AMUTEIN0 6 C1 I/O/Z IPU
• Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]), in addition to the GPIO registers. GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and GP4/ AMUTEIN1 1 C2 GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the associated McASP AMUTE register. HOST-PORT INTERFACE (HPI) HINT/GP[1] 135 J20 O/Z IPU Host interrupt (from DSP to host) (O ) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). HCNTL1/AXR1[1] 144 G19 I IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). HCNTL0/AXR1[3] 146 G18 I IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). HHWIL/AFSR1 139 H20 I IPU Host half-word select − first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HR/W /AXR1[0] 143 G20 I IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) HD15/GP[15]§ 174 B14 IPU Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z)

• Used for transfer of data, address, and control Also controls initialization of DSP modes at reset via pullup/pulldown HD14/GP[14]§ 173 C14 IPU Used for transfer of data, address, and control
• Also controls initialization of DSP modes at reset via pullup/pulldown resistors − Device Endian Mode (HD8) HD13/GP[13]§ 172 A15 IPU − Device Endian Mode (HD8) 0 – Big Endian 1 − Little Endian For proper C6713 device operation, do not oppose the internal pullup (IPU) HD12/GP[12]§ 168 C15 IPU For proper C6713 device operation, do not oppose the internal pullup (IPU) resistor on HD12. − Boot mode (HD[4:3]) HD11/GP[11] 167 A16 I/O/Z IPU − Boot mode (HD[4:3]) 00 – HPI boot/Emulation boot 01 – CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 − CE1 width 16-bit, Asynchronous external ROM boot with default HD10/GP[10] 166 B16 IPU timings (default mode) 10 − CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 − CE1 width 32-bit, Asynchronous external ROM boot with default timings HD9/GP[9] 165 C16 IPU timings − HPI_EN (HD14) 0 – HPI disabled, McASP1 enabled 1 − HPI enabled, McASP1 disabled (default) HD8/GP[8]§ 160 B17 IPU 0 – HPI disabled, McASP1 enabled 1 − HPI enabled, McASP1 disabled (default) Other HD pins (HD [15, 13:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For proper device operation of the HD[15, 13:9, 7, 1, 0], do not oppose these pins HD7/GP[3] 164 A18 IPU proper device operation of the HD[15, 13:9, 7, 1, 0], do not oppose these pins with external IPUs/IPDs at reset; however, the HD[6, 5, 2] pins can be opposed and driven at reset. For more details, see the Device Configurations section of this data sheet. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] § To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 51POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION HOST-PORT INTERFACE (HPI) (CONTINUED) HD6/AHCLKR1 161 C17 I/O/Z IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). HD5/AHCLKX1 159 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). HD4/GP[0]§ 156 C19 I/O/Z IPD Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0] pin (I/O/Z). HD3/AMUTE1 § 154 C20 IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z). HD2/AFSX1 155 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z). HD1/AXR1[7] 152 D20 IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z). HD0/AXR1[4] 147 E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z). HAS /ACLKX1 153 E18 I IPU Host address strobe (I) [default] or McASP1 transmit bit clock (I/O/Z). HCS /AXR1[2] 145 F20 I IPU Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z). HDS1 /AXR1[6] 151 E19 I IPU Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z). HDS2 /AXR1[5] 150 F18 I IPU Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z) . HRDY /ACLKR1 140 H19 O/Z IPD Host ready (from DSP to host) (O ) [default] or McASP1 receive bit clock (I/O/Z). EMIF − COMMON SIGNALS TO ALL TYPES OF MEMORY ¶ CE3 57 V6 O/Z IPU Memory space enablesCE2 61 W6 O/Z IPU Memory space enables

• Enabled by bits 28 through 31 of the word address CE1 103 W18 O/Z IPU
• Enabled by bits 28 through 31 of the word address
• Only one asserted during any external data access CE0 102 V17 O/Z IPU
• Only one asserted during any external data access BE3 — V5 O/Z IPU Byte-enable control BE2 — Y4 O/Z IPU Byte-enable control
• Decoded from the two lowest bits of the internal address BE1 108 U19 O/Z IPU
• Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory Can be directly connected to SDRAM read and write mask signal (SDQM)BE0 110 V20 O/Z IPU Byte-write enables for most types of memory
• Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF − BUS ARBITRATION ¶ HOLDA 137 J18 O/Z IPU Hold-request-acknowledge to the host HOLD 138 J17 I IPU Hold request from the host BUSREQ 136 J19 O/Z IPU Bus request output † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] § To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively. ¶ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ ‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL § ECLKIN 78 Y11 I IPD External EMIF input clock source ECLKOUT 77 Y10 O/Z IPD EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]). EKSRC = 0 – ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default). EKSRC = 1 – ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN) EKEN = 0 – ECLKOUT held low EKEN = 1 – ECLKOUT enabled to clock (default) ARE /SDCAS / SSADS 79 V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe AOE /SDRAS / SSOE 75 W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable AWE /SDWE / SSWE 83 V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable ARDY 56 Y5 I IPU Asynchronous memory ready input EMIF − ADDRESS § EA21 109 U18 EA20 101 Y18 EA19 100 W17 EA18 95 Y16 EA17 99 V16 EA16 92 Y15 EA15 94 W15 EA14 90 Y14 EMIF external address EA13 91 W14 EMIF external address Note: EMIF address numbering for the C6713PYP device starts with EA2 to maintain signal name compatibility with other C671x devicesEA12 93 V14 O/Z IPU Note: EMIF address numbering for the C6713PYP device starts with EA2 to maintain signal name compatibility with other C671x devices (e.g., C6711 and C6713GDP) [see the 32-bit EMIF addressing EA11 86 W13 O/Z IPU (e.g., C6711 and C6713GDP) [see the 32-bit EMIF addressing scheme in the TMS320C6000 DSP External Memory Interface (EMIF) EA10 76 V10 scheme in the TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (literature number SPRU266)]. EA9 74 Y9 EA8 71 V9 EA7 70 Y8 EA6 69 W8 EA5 68 V8 EA4 64 W7 EA3 63 V7 EA2 62 Y6 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] § To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION EMIF − DATA§ ED31 — N3 ED30 — P3 ED29 — P2 ED28 — P1 ED27 — R2 ED26 — R3 ED25 — T2 ED24 — T1 ED23 — U3 ED22 — U1 ED21 — U2 ED20 — V1 ED19 — V2 ED18 — Y3 ED17 — W4 ED16 — V4 I/O/Z IPU External data pins (ED[31:16] pins applicable to GDP package only)ED15 112 T19 I/O/Z IPU External data pins (ED[31:16] pins applicable to GDP package only) ED14 113 T20 ED13 111 T18 ED12 118 R20 ED11 117 R19 ED10 120 P20 ED9 119 P18 ED8 123 N20 ED7 122 N19 ED6 121 N18 ED5 128 M20 ED4 127 M19 ED3 129 L19 ED2 130 L18 ED1 131 K19 ED0 132 K18 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] § To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTION MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1) GP4/ AMUTEIN1

1 C2 I/O/Z IPU General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or

McASP1 mute input (I/O/Z). HD3/AMUTE1 154 C20 I/O/Z IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z). HRDY /ACLKR1 140 H19 I/O/Z IPD Host ready (from DSP to host) (O ) [default] or McASP1 receive bit clock (I/O/Z). HD6/AHCLKR1 161 C17 I/O/Z IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). HAS /ACLKX1 153 E18 I/O/Z IPU Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z). HD5/AHCLKX1 159 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). HHWIL/AFSR1 139 H20 I/O/Z IPU Host half-word select − first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HD2/AFSX1 155 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/ right clock (LRCLK) (I/O/Z). HD1/AXR1[7] 152 D20 I/O/Z IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 TX/RX data pin 7 (I/O/Z). HDS1 /AXR1[6] 151 E19 I/O/Z IPU Host data strobe 1 (I) [default] or McASP1 TX/RX data pin 6 (I/O/Z). HDS2 /AXR1[5] 150 F18 I/O/Z IPU Host data strobe 2 (I) [default] or McASP1 TX/RX data pin 5 (I/O/Z). HD0/AXR1[4] 147 E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 TX/RX data pin 4 (I/O/Z). HCNTL0/AXR1[3] 146 G18 I/O/Z IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 TX/RX data pin 3 (I/O/Z). HCS /AXR1[2] 145 F20 I/O/Z IPU Host chip select (I) [default] or McASP1 TX/RX data pin 2 (I/O/Z). HCNTL1/AXR1[1] 144 G19 I/O/Z IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 TX/RX data pin 1 (I/O/Z). HR/W /AXR1[0] 143 G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 TX/RX data pin 0 (I/O/Z). MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) GP5/ AMUTEIN0 6 C1 I/O/Z IPU General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or McASP0 mute input (I/O/Z). CLKX1/AMUTE0 33 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z). CLKR0/ACLKR0 19 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z). TINP1/AHCLKX0 12 F2 I/O/Z IPD Timer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This pin defaults as Timer 1 input (I) and McASP transmit high−frequency master clock input (I). CLKX0/ACLKX0 16 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). CLKS0/AHCLKR0 28 K3 I/O/Z IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z). FSR0/AFSR0 24 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). FSX0/AFSX0 21 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). FSR1/AXR0[7] 38 M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z). † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 55POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED) CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z). DX1/AXR0[5] 32 L2 I/O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z). TOUT1/AXR0[4] 13 F1 I/O/Z IPD Timer 1 output (O ) [default] or McASP0 TX/RX data pin 4 (I/O/Z). TINP0/AXR0[3] 17 G2 I/O/Z IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z). TOUT0/AXR0[2] 18 G1 I/O/Z IPD Timer 0 output (O ) [default] or McASP0 TX/RX data pin 2 (I/O/Z). DX0/AXR0[1] 20 H2 I/O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z). DR0/AXR0[0] 27 J1 I/O/Z IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z). TIMER 1 TOUT1/AXR0[4] 13 F1 O IPD Timer 1 output (O ) [default] or McASP0 TX/RX data pin 4 (I/O/Z). TINP1/AHCLKX0 12 F2 I IPD Timer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This pin defaults as Timer 1 input (I) and McASP transmit high−frequency master clock input (I). TIMER0 TOUT0/AXR0[2] 18 G1 O IPD Timer 0 output (O ) [default] or McASP0 TX/RX data pin 2 (I/O/Z). TINP0/AXR0[3] 17 G2 I IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z). MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1/SCL1 8 E1 I — McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). This pin does not have an internal pullup or pulldown. When this pin is used as a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even when an external device is driving the pin. CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z). CLKX1/AMUTE0 33 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z). DR1/SDA1 37 M2 I — McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). This pin does not have an internal pullup or pulldown. When this pin is used as a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even when an external device is driving the pin. DX1/AXR0[5] 32 L2 O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z). FSR1/AXR0[7] 38 M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z). FSX1 31 L1 I/O/Z IPD McBSP1 transmit frame sync † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0/AHCLKR0 28 K3 I IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z). CLKR0/ACLKR0 19 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z). CLKX0/ACLKX0 16 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). DR0/AXR0[0] 27 J1 I IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z). DX0/AXR0[1] 20 H2 O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z). FSR0/AFSR0 24 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). FSX0/AFSX0 21 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). INTER-INTEGRATED CIRCUIT 1 (I2C1) CLKS1/SCL1 8 E1 I/O/Z — McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). This pin must be externally pulled up. When this pin is used as an I2C pin, the value of the pullup resistor is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I2C Specification Revision 2.1 (January 2000). DR1/SDA1 37 M2 I/O/Z — McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). This pin must be externally pulled up. When this pin is used as an I2C pin, the value of the pullup resistor is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I2C Specification Revision 2.1 (January 2000). INTER-INTEGRATED CIRCUIT 0 (I2C0) SCL0 41 N1 I/O/Z — I2C0 clock. This pin must be externally pulled up. The value of the pullup resistor on this pin is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I2C Specification Revision 2.1 (January 2000). SDA0 42 N2 I/O/Z — I2C0 data. This pin must be externally pulled up. The value of the pullup resistor on this pin is dependent on the number of devices connected to the I2C bus. For more details, see the Philips I2C Specification Revision 2.1 (January 2000). † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 57POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † IPD/ IPU‡ DESCRIPTIONNAME PYP GDP TYPE † IPD/ IPU‡ DESCRIPTION GENERAL-PURPOSE INPUT/OUTPUT (GPIO) HD15/GP[15] 174 B14 IPU Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) and some function as boot configuration pins at reset. HD14/GP[14] 173 C14 IPU (I/O/Z) and some function as boot configuration pins at reset.

• Used for transfer of data, address, and control
• Also controls initialization of DSP modes at reset via pullup/pulldown HD13/GP[13] 172 A15 IPU
• Also controls initialization of DSP modes at reset via pullup/pulldown resistors As general-purpose input/output (GP[x]) functions, these pins are software-con- HD12/GP[12] 168 C15 I/O/Z IPU As general-purpose input/output (GP[x]) functions, these pins are software-con- figurable through registers. The “GPxEN” bits in the GP Enable register and the GPxDIR bits in the GP Direction register must be properly configured: HD11/GP[11] 167 A16 I/O/Z IPU GPxDIR bits in the GP Direction register must be properly configured: GPxEN = 1; GP[x] pin is enabled. HD10/GP[10] 166 B16 IPU GPxEN = 1; GP[x] pin is enabled. GPxDIR = 0; GP[x] pin is an input. GPxDIR = 1; GP[x] pin is an output. HD9/GP[9] 165 C16 IPU GPxDIR = 1; GP[x] pin is an output. For the functionality description of the Host-port data pins or the boot configura- HD8/GP[8] 160 B17 IPU For the functionality description of the Host-port data pins or the boot configura- tion pins, see the Host-Port Interface (HPI) portion of this table. GP7 7 E3 General-purpose input/output pins (I/O/Z) which also function as external interrupts GP6 2 D2 interrupts
• Edge-driven Polarity independently selected via the External Interrupt Polarity Register GP5/ AMUTEIN0 6 C1 I/O/Z IPU
• Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and GP4/ AMUTEIN1 1 C2 GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the associated McASP AMUTE register. HD7/GP[3] 164 A18 I/O/Z IPU Host-port data pin 7 (I/O/Z) [default] or general-purpose input/output pin 3 (I/O/Z) CLKOUT2/GP[2] 82 Y12 I/O/Z IPD Clock output at half of device speed (O/Z) [default] or this pin can be programmed as GP[2] pin. HINT/GP[1] 135 J20 O IPU Host interrupt (from DSP to host) (O ) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). HD4/GP[0] 156 C19 I/O/Z IPD Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0] pin (I/O/Z). RESERVED FOR TEST RSV 198 A5 O/Z IPU Reserved. (Leave unconnected, do not connect to power or ground) RSV 200 B5 A§ Reserved. (Leave unconnected, do not connect to power or ground) RSV 179 C12 O — Reserved. (Leave unconnected, do not connect to power or ground) RSV — D7 O/Z IPD Reserved. (Leave unconnected, do not connect to power or ground) RSV 178 D12 I — Reserved. This pin does not have an IPU. For proper device operation, the D12 pin must be externally pulled down with a 10-kΩ resistor. RSV 181 A12 — Reserved. [For new designs, it is recommended that this pin be connected di- rectly to CVDD (core power). For old designs, this pin can be left unconnected. RSV 180 B11 — Reserved. [For new designs, it is recommended that this pin be connected di- rectly to Vss (ground). For old designs, this pin can be left unconnected. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued) SIGNAL PIN NO. TYPE † DESCRIPTIONNAME PYP GDP TYPE † DESCRIPTION SUPPLY VOLTAGE PINS — A17 — B3 — B8 — B13 — C10 — D1 — D16 — D19 — F3 — H18 — J2 — M18 — R1 — R18 — T3 — U5 — U7 — U12 — U16 DV DD — V13 S 3.3-V supply voltageDV DD — V15 S 3.3-V supply voltage (see the power-supply decoupling portion of this data sheet) — V19 (see the power-supply decoupling portion of this data sheet) — W3 — W9 — W12 — Y7 — Y17 5 — 9 — 25 — 44 — 47 — 55 — 58 — 65 — 72 — 84 — 87 — 98 — 107 — † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 59POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † DESCRIPTIONNAME PYP GDP TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) 114 — 126 — 141 — 3.3-V supply voltageDV DD 162 — S 3.3-V supply voltage (see the power-supply decoupling portion of this data sheet)DV DD 183 — S (see the power-supply decoupling portion of this data sheet) 188 — 206 — — A4 — A9 — A10 — B2 — B19 — C3 — C7 — C18 — D5 — D6 — D11 — D14 — D15 — F4 — F17 1.2-V supply voltage [PYP package] CV DD — K1 S 1.2-V supply voltage [PYP package] 1.20-V supply voltage [GDP package] (See Note) (see the power-supply decoupling portion of this data sheet)CV DD — K4 S (see the power-supply decoupling portion of this data sheet) — K17 — L4 — L17 — L20 — R4 — R17 — U6 — U10 — U11 — U14 — U15 — V3 — V18 Note: This value is compatible with existing 1.26−V designs.— W2 Note: This value is compatible with existing 1.26−V designs. — W19 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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Terminal Functions (Continued) SIGNAL PIN NO. TYPE † DESCRIPTIONNAME PYP GDP TYPE † DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) 3 — 11 — 14 — 22 — 29 — 35 — 40 — 43 — 46 — 50 — 51 — 53 — 60 — 67 — 80 — CV DD 89 — S 1.2-V supply voltage [PYP package] 1.20-V supply voltage [GDP package] (See Note) CV DD 96 — S 1.20-V supply voltage [GDP package] (See Note) (see the power-supply decoupling portion of this data sheet) 104 — (see the power-supply decoupling portion of this data sheet) 105 — 116 — 124 — 133 — 149 — 157 — 169 — 171 — 177 — 190 — 195 — 196 — Note: This value is compatible with existing 1.26−V designs.201 — Note: This value is compatible with existing 1.26−V designs. 208 — GROUND PINS — A1 — A2 — A11 VSS — A14 GND Ground pinsVSS — A19 GND Ground pins — A20 — B1 — B4 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 61POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † DESCRIPTIONNAME PYP GDP TYPE † DESCRIPTION GROUND PINS (CONTINUED) — B15 — B20 — C6 — C8 — C9 — D4 — D8 — D13 — D17 — E2 — E4 — E17 — F19 — G4 — G17 — H4 — H17 — J4 Ground pins¶ VSS — J9 GND Ground pins¶ The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to groundVSS — J10 GND The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as both electrical grounds and thermal relief (thermal dissipation). — J11 and act as both electrical grounds and thermal relief (thermal dissipation). — J12 — K2 — K9 — K10 — K11 — K12 — K20 — L9 — L10 — L11 — L12 — M4 — M9 — M10 — M11 — M12 — M17 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ¶ Shaded pin numbers denote the center thermal balls.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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Terminal Functions (Continued) SIGNAL PIN NO. TYPE † DESCRIPTIONNAME PYP GDP TYPE † DESCRIPTION GROUND PINS (CONTINUED) — N4 — N17 — P4 — P17 — P19 — T4 — T17 — U4 — U8 — U9 — U13 — U17 — U20 — W1 — W5 — W11 — W16 — W20 — Y1 VSS — Y2 GND Ground pinsVSS — Y13 GND Ground pins — Y19 — Y20 4 — 10 — 15 — 23 — 26 — 30 — 34 — 39 — 45 — 48 — 49 — 52 — 54 — 59 — 66 — 73 — 81 — † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 63POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) SIGNAL PIN NO. TYPE † DESCRIPTIONNAME PYP GDP TYPE † DESCRIPTION GROUND PINS (CONTINUED) 85 — 88 — 97 — 106 — 115 — 125 — 134 — 142 — VSS 148 — GND Ground pinsVSS 158 — GND Ground pins 163 — 170 — 182 — 189 — 194 — 199 — 203 — 207 — † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. C6000 and XDS are trademarks of Texas Instruments.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 65POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device support device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. (e.g., TMS 320C6713GDP225). Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications. TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification. TMS Fully qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GDP), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -225 is 225 MHz). For device part numbers and further ordering information for TMS320C6713 in the PYP and GDP, package types, see the TI website (http://www.ti.com) or contact your TI sales representative. TMS320 is a trademark of Texas Instruments.

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document or the TI website (www.ti.com).

225 MHz

200 MHz

167 MHz

Figure 12. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6713 Device) MicroStar BGA and PowerPAD are trademarks of Texas Instruments.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 67POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000  CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000 PRG Overview] (literature number SPRU190) provides an overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated peripheral documents. These C6713 peripherals are similar to the peripherals on the TMS320C6711 and TMS320C64x devices; therefore, see the TMS320C6711 (C6711 or C67x) peripheral information, and in some cases, where indicated, see the TMS320C6711 (C6711 or C671x) peripheral information and in some cases, where indicated, see the C64x information in the C6000 PRG Overview (literature number SPRU190). The TMS320DA6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041) describes the functionality of the McASP peripherals available on the C6713 device. TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233) describes the functionality of the PLL peripheral available on the C6713 device. TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175) describes the functionality of the I2C peripherals available on the C6713 device. The PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) focuses on the specifics of integrating a PowerPAD package into the printed circuit board design to make optimum use of the thermal efficiencies designed into the PowerPAD package. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. The Migrating from TMS320C6211(B)/C6711(B) to TMS320C6713 application report (literature number SPRA851) indicates the differences and describes the issues of interest related to the migration from the Texas Instruments TMS320C6211(B)/C6711(B), GFN package, to the TMS320C6713, GDP package. The TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191) describes the known exceptions to the functional specifications for particular silicon revisions of the TMS320C6713 device. The TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A2 or later) discusses the power consumption for user applications with the TMS320C6713B, TMS320C6712D, and TMS320C6711D DSP devices. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the application report How To Begin Development Today With the TMS320C6713 Floating-Point DSP (literature number SPRA809), which describes in more detail the similarities/differences between the C6713 and C6711 C6000 DSP devices. C62x is a trademark of Texas Instruments.

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Table 24 identify the bit fields in the CPU CSR register. Reference Guide (literature number SPRU189). Figure 13. CPU Control Status Register (CPU CSR)

Table 24. CPU CSR Register Bit Field Description 31:24 CPU ID CPU ID + REV ID. Read only. Identifies which CPU is used and defines the silicon revision of the CPU. Identifies which CPU is used and defines the silicon revision of the CPU. Control power-down modes. The values are always read as zero.

9 SAT

a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false. Endian bit. This bit is read-only. Depicts the device endian mode. 1 = Little Endian mode [default]. 000/010 = Cache Enabled / Cache accessed and updated on reads. All other PCC values reserved.

1 PGIE

taken. Allows for proper nesting of interrupts. 1 = Previous GIE value is 1.

0 GIE

Global interrupt enable bit. Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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interrupts and interrupt selector The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 25. The highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source listed in Table 25. However, their interrupt source may be reprogrammed to any one of the sources listed in Table 26 (Interrupt Selector). Table 26 lists the selector value corresponding to each of the alternate interrupt sources. The selector choice for interrupts 4−15 is made by programming the corresponding fields (listed in Table 25) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers.

Table 25. DSP Interrupts Table 26. Interrupt Selector

10000 GPINT0 GPIO

10001 Reserved −

10010 Reserved −

10011 Reserved −

10100 Reserved −

10101 Reserved −

10110 I2CINT0 I2C0

10111 I2CINT1 I2C1

11000 Reserved −

11001 Reserved −

11010 Reserved −

11011 Reserved −

11100 AXINT0 McASP0

11101 ARINT0 McASP0

11110 AXINT1 McASP1

11111 ARINT1 McASP1

Input/Output (GPIO) Reference Guide (literature number SPRU584).

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external interrupt sources are available at the same time. Table 27. External Interrupt Sources and Peripheral Module Control

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 73POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 EDMA module and EDMA selector The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned EDMA selector code (see Table 29). By loading each EVTSELx register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA channel. Table 28 lists the default EDMA selector value for each EDMA channel. See Table 30 and Table 31 for the EDMA Event Selector registers and their associated bit descriptions.

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Table 28. EDMA Channels Table 29. EDMA Selector

0 ESEL0[5:0] 000000 DSPINT 000000 DSPINT HPI

1 ESEL0[13:8] 000001 TINT0 000001 TINT0 TIMER0

2 ESEL0[21:16] 000010 TINT1 000010 TINT1 TIMER1

3 ESEL0[29:24] 000011 SDINT 000011 SDINT EMIF

4 ESEL1[5:0] 000100 GPINT4 000100 GPINT4 GPIO

5 ESEL1[13:8] 000101 GPINT5 000101 GPINT5 GPIO

6 ESEL1[21:16] 000110 GPINT6 000110 GPINT6 GPIO

7 ESEL1[29:24] 000111 GPINT7 000111 GPINT7 GPIO

12 ESEL3[5:0] 001100 XEVT0 001100 XEVT0 McBSP0

13 ESEL3[13:8] 001101 REVT0 001101 REVT0 McBSP0

14 ESEL3[21:16] 001110 XEVT1 001110 XEVT1 McBSP1

15 ESEL3[29:24] 001111 REVT1 001111 REVT1 McBSP1

100000 AXEVTE0 McASP0

100001 AXEVTO0 McASP0

100010 AXEVT0 McASP0

100011 AREVTE0 McASP0

100100 AREVTO0 McASP0

100101 AREVT0 McASP0

100110 AXEVTE1 McASP1

100111 AXEVTO1 McASP1

101000 AXEVT1 McASP1

101001 AREVTE1 McASP1

101010 AREVTO1 McASP1

101011 AREVT1 McASP1

101100 I2CREVT0 I2C0

101101 I2CXEVT0 I2C0

101110 I2CREVT1 I2C1

101111 I2CXEVT1 I2C1

110000 GPINT8 GPIO

110001 GPINT9 GPIO

110010 GPINT10 GPIO

110011 GPINT11 GPIO

110100 GPINT12 GPIO

110101 GPINT13 GPIO

110110 GPINT14 GPIO

110111 GPINT15 GPIO

Table 30. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3) Table 31. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description Reserved Reserved. Read-only, writes have no effect. EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels. channel 15 is triggered by Timer0 TINT0 events.

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peripherals). Figure 14 illustrates the PLL, the PLL controller, and the clock generator logic. † Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers. components other than the ones shown. C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD . D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U. Figure 14. PLL and Clock Generator Logic

the PLL path), see Table 32 and Figure 14. the PLL Lock Time values, see Table 32. Table 32. PLL Lock and Reset Times Table 33. CLKOUT Signals, Default Settings, and Control OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system. multiplied up by a factor of x4, x5, x6, and so on, up to x25. (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). See Table 34 for the PLL clocks input and output frequency ranges.

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Table 34. PLL Clock Frequency Ranges†‡ † SYSCLK2 rate must be exactly half of SYSCLK1. § When the McASP module is not used, the AUXCLK maximum frequency can be any frequency up to the CLKIN maximum frequency. Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register. Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233). programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 14). SYSCLK2 rate must be exactly half of the SYSCLK1 rate. PLLDIV1 and PLLDIV2 registers). to directly access the PLL Controller registers. descriptions, see Table 36 through Table 42.

Table 35. PLL Control/Status Register (PLLCSR) [0x01B7 C100] Table 36. PLL Control/Status Register (PLLCSR) Description 31:7 Reserved Reserved. Read-only, writes have no effect.

6 STABLE

Clock Input Stable. This bit indicates if the clock input has stabilized. 0 – Clock input not yet stable. Clock counter is not finished counting (default). 5:4 Reserved Reserved. Read-only, writes have no effect.

3 PLLRST

1 – PLL Reset Asserted (default). 2 Reserved Reserved. The user must write a “0” to this bit.

1 PLLPWRDN

0 – PLL Operational (default). 1 – PLL Placed in Power-Down State.

0 PLLEN

0 – Bypass Mode (default). PLL disabled. directly from input reference clock.

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Table 37. PLL Multiplier Control Register (PLLM) [0x01B7 C110] Table 38. PLL Multiplier Control Register (PLLM) Description 31:5 Reserved Reserved. Read-only, writes have no effect. PLL multiply mode [default is x7 (0 0111)]. PLLM select values 00000 through 00011 and 11010 through 11111 are not supported.

Table 39. PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3) † Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively. D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used. Table 40. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1, 31:16 Reserved Reserved. Read-only, writes have no effect.

15 DxEN

Divider Dx Enable (where x denotes 0 through 3). 0 – Divider x Disabled. No clock output. 1 − Divider x Enabled (default). These divider-enable bits are device-specific and must be set to 1 to enable. 14:5 Reserved Reserved. Read-only, writes have no effect. if D1 is set to /2, then D2 must be set to /4.

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Table 41. Oscillator Divider 1 Register (OSCDIV1) [0x01B7 C124] Table 42. Oscillator Divider 1 Register (OSCDIV1) Description 31:16 Reserved Reserved. Read-only, writes have no effect.

15 OD1EN

Oscillator Divider 1 Enable. 0 – Oscillator Divider 1 Disabled. 1 − Oscillator Divider 1 Enabled (default). 14:5 Reserved Reserved. Read-only, writes have no effect. Oscillator Divider 1 Ratio [default is /8 (0 0111)].

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 83POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 multichannel audio serial port (McASP) peripherals The TMS320C6713 device includes two multi-channel audio serial port (McASP) interface peripherals (McASP1 and McASP0). The McASP is a serial port optimized for the needs of multi-channel audio applications. With two McASP peripherals, the TMS320C6713 device is capable of supporting two completely independent audio zones simultaneously. Each McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. Each McASP module also includes a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO). The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial format. Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format. However, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data (for example, passing control information between two DSPs). The McASP peripherals have additional capability for flexible clock generation, and error detection/handling, as well as error management. McASP block diagram Figure 15 illustrates the major blocks along with external signals of the TMS320C6713 McASP1 and McASP0 peripherals; and shows the 8 serial data [AXR] pins for each McASP. Each McASP also includes full general-purpose I/O (GPIO) control, so any pins not needed for serial transfers can be used for general-purpose I/O.

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Figure 15. McASP0 and McASP1 Configuration

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 85POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 multichannel audio serial port (McASP) peripherals (continued) multichannel time division multiplexed (TDM) synchronous transfer mode The McASP supports a multichannel, time-division-multiplexed (TDM) synchronous transfer mode for both transmit and receive. Within this transfer mode, a wide variety of serial data formats are supported, including formats compatible with devices using the Inter-Integrated Sound (IIS) protocol. TDM synchronous transfer mode is typically used when communicating between integrated circuits such as between a DSP and one or more ADC, DAC, CODEC, or S/PDIF receiver devices. In multichannel applications, it is typical to find several devices operating synchronized with each other. For example, to provide six analog outputs, three stereo DAC devices would be driven with the same bit clock and frame sync, but each stereo DAC would use a different McASP serial data pin carrying stereo data (2 TDM time slots, left and right). The TDM synchronous serial transfer mode utilizes several control signals and one or more serial data signals: /C0068A bit clock signal (ACLKX for transmit, ACKLR for receive) /C0068A frame sync signal (AFSX for transmit, AFSR for receive) /C0068An (Optional) high frequency master clock (AHCLKX for transmit, AHCLKR for receive) from which the bit clock is derived /C0068One or more serial data pins (AXR for transmit and for receive). Except for the optional high-frequency master clock, all of the signals in the TDM synchronous serial transfer mode protocol are synchronous to the bit clocks (ACLKX and ACLKR). In the TDM synchronous transfer mode, the McASP continually transmits and receives data periodically (since audio ADCs and DACs operate at a fixed-data rate). The data is organized into frames, and the beginning of a frame is marked by a frame sync pulse on the AFSX, AFSR pin. In a typical audio system, one frame is transferred per sample period. To support multiple channels, the choices are to either include more time slots per frame (and therefore operate with a higher bit clock) or to keep the bit clock period constant and use additional data pins to transfer the same number of channels. For example, a particular six-channel DAC might require three McASP serial data pins; transferring two channels of data on each serial data pin during each sample period (frame). Another similar DAC may be designed to use only a single McASP serial data pin, but clocked three times faster and transferring six channels of data per sample period. The McASP is flexible enough to support either type of DAC but a transmitter cannot be configured to do both at the same time. For multiprocessor applications, the McASP supports any number of time slots per frame (between 2 and 32), and includes the ability to “disable” transfers during specific time slots. In addition, to support of S/PDIF, AES-3, IEC-60958, CP-430 receivers chips whose natural block (McASP frame) size is 384 samples; the McASP receiver supports a 384 time slot mode. The advantage to using the 384 time slot mode is that interrupts may be generated synchronous to the S/PDIF, AES-3, IEC-60958, CP-430 receivers, for example the “last slot” interrupt. burst transfer mode The McASP also supports a burst transfer mode, which is useful for non-audio data (for example, passing control information between two DSPs). Burst transfer mode uses a synchronous serial format similar to TDM, except the frame sync is generated for each data word transferred. In addition, frame sync generation is not periodic or time-driven as in TDM mode but rather data-driven.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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multichannel audio serial port (McASP) peripherals (continued) supported bit stream formats for TDM and burst transfer modes The serial data pins support a wide variety of formats. In the TDM and burst synchronous modes, the data may be transmitted / received with the following options: /C0068Time slots per frame: 1 (Burst/Data Driven), or 2,3...32 (TDM/Time-Driven). /C0068Time slot size: 8, 12, 16, 20, 24, 28, 32 bits per time slot /C0068Data size: 8, 12, 16, 20, 24, 28, 32 bits (must be less than or equal to time slot) /C0068Data alignment within time slot: Left- or Right-Justified /C0068Bit order: MSB or LSB first. /C0068Unused bits in time slot: Padded with 0, 1 or extended with value of another bit. /C0068Time slot delay from frame sync: 0,1, or 2 bit delay The data format can be programmed independently for transmit and receive, and for McASP0 vs. McASP1. In addition, the McASP can automatically re-align the data as processed natively by the DSP (any format on a nibble boundary) adjusting the data in hardware to any of the supported serial bit stream formats (TDM, Burst, and DIT modes). This reduces the amount of bit manipulation that the DSP must perform and simplifies software architecture. digital audio interface transmitter (DIT) transfer mode (transmitter only) The McASP transmit section may also be configured in digital audio interface transmitter (DIT) mode where it outputs data formatted for transmission over an S/PDIF, AES-3, IEC-60958, or CP-430 standard link. These standards encode the serial data such that the equivalent of ’clock’ and ’frame sync’ are embedded within the data stream. DIT transfer mode is used as an interconnect between audio components and can transfer multichannel digital audio data over a single optical or coaxial cable. From an internal DSP standpoint, the McASP operation in DIT transfer mode is similar to the two time slot TDM mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble, channel status, user data, validity, and parity automatically stuffed into the bit stream by the McASP module. The McASP includes separate validity bits for even/odd subframes and two 384-bit register file modules to hold channel status and user data bits. DIT mode requires at minimum: /C0068One serial data pin (if the AUXCLK is used as the reference [see the PLL and Clock Generator Logic Figure 14]) or /C0068One serial data pin plus either the AHCLKX or ACLKX pin (if an external clock is needed). If additional serial data pins are used, each McASP may be used to transmit multiple encoded bit streams (one per pin). However, the bit streams will all be synchronized to the same clock and the user data, channel status, and validity information carried by each bit stream will be the same for all bit streams transmitted by the same McASP module. The McASP can also automatically re-align the data as processed by the DSP (any format on a nibble boundary) in DIT mode; reducing the amount of bit manipulation that the DSP must perform and simplifies software architecture.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005 87POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 multichannel audio serial port (McASP) peripherals (continued) McASP flexible clock generators The McASP transmit and receive clock generators are identical. Each clock generator can accept a high-frequency master clock input (on the AHCLKX and AHCLKR pins). The transmit and receive bit clocks (on the ACLKX and ACLKR pins) can also be sourced externally or can be sourced internally by dividing down the high-frequency master clock input (programmable factor /1, /2, /3, ... /4096). The polarity of each bit clock is individually programmable. The frame sync pins are AFSX (transmit) and AFSR (receive). A typical usage for these pins is to carry the left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are individually programmable for either internal or external generation, either bit or slot length, and either rising or falling edge polarity. Some examples of the things that a system designer can use the McASP clocking flexibility for are: /C0068Input a high-frequency master clock (for example, 512fs of the receiver), receive with an internally generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2. [An example application would be to receive data from a DVD at 48 kHz but output up-sampled or decoded audio at 96 kHz or 192 kHz.] /C0068Transmit/receive data based one sample rate (for example, 44.1 kHz) using McASP0 while transmitting and receiving at a different sample rate (for example, 48 kHz) on McASP1. /C0068Use the DSP’s on-board AUXCLK to supply the system clock when the input source is an A/D converter. McASP error handling and management To support the design of a robust audio system, the McASP module includes error-checking capability for the serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that continually measures the high-frequency master clock every 32-SYSCLK2 clock cycles. The timer value can be read to get a measurement of the high-frequency master clock frequency and has a min-max range setting that can raise an error flag if the high-frequency master clock goes out of a specified range. The user would read the high-frequency transmit master clock measurement (AHCLKX0 or AHCLKX1) by reading the XCNT field of the XCLKCHK register and the user would read the high-frequency receive master clock measurement (AHCLKR0 or AHCLKR1) by reading the RCNT field of the RCLKCHK register. Upon the detection of any one or more of the above errors (software selectable), or the assertion of the AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately mute the audio output. In addition, an interrupt may be generated if enabled based on any one or more of the error sources. McASP interrupts and EDMA events The McASP transmitter and receiver sections each generate an event on every time slot. This event can be serviced by an interrupt or by the EDMA controller. When using interrupts to service the McASP, each shift register buffer has a unique address in the McASP Registers space (see Table 3). When using the EDMA to service the McASP, the McASP DATA Port space in Table 3 is accessed. In this case, the address least-significant bits are ignored. Writes to any address in this range access the transmitting buffers in order from lowest (serializer 0) to highest (serializer 15), skipping over disabled and receiving serializers. Likewise, reads from any address in this space access the receiving buffers in the same order but skip over disabled and transmitting buffers.

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with other controllers in a system or to implement a user interface. Figure 16 is a block diagram of the I2Cx module. NOTE A: Shading denotes control/status registers. Figure 16. I2Cx Module Block Diagram

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Figure 19 shows the power-down mode logic on the C6713. † External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic. Figure 19. Power-Down Mode Logic† of the control status register (CSR). The PWRD field of the CSR is shown in Figure 20 and described in Table 43. and Instruction Set Reference Guide (literature number SPRU189).

bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 20. PWRD Field of the CSR Register PD1 mode termination by an enabled interrupt. PD2 and PD3 modes can only be aborted by device reset. Table 43 summarizes all the power-down modes.

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Table 43. Characteristics of the Power-Down Modes

000000 No power-down — —

001001 PD1 Wake by an enabled interruptCPU halted (except for the interrupt logic)

010001 PD1 Wake by an enabled or

between peripherals and internal memory.

011010 PD2 † Wake by a device reset

011100 PD3 † Wake by a device reset

PLL needs time to re-lock, just as it does following power-up. the PLL needs to be re-locked, just as it does following power-up. peripherals will not operate according to specifications. if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock input (CLKIN). Therefore, bypassing the PLL makes the power-down modes PD2 and PD3 ineffective. (CSR.11) or PD2 (CSR.10) to enter a power-down mode. (>1 second) if the other supply is below the proper operating voltage. powered up, thus, preventing bus contention with other chips on the board.

power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 21). Figure 21. Schottky Diode Diagram core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. lifetime needs to be considered.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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IEEE 1149.1 JTAG compatibility statement The TMS320C6713 DSP requires that both TRST and RESET resets be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are required for proper operation. Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected after TRST is asserted. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. The TMS320C6713 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. Note: The DESIGN−WARNING section of the TMS320C6713 BSDL file contains information and constraints regarding proper device operation while in Boundary Scan Mode. For more detailed information on the C6713 JTAG emulation, see the TMS320C6000 DSP Designing for JTAG Emulation Reference Guide (literature number SPRU641). EMIF device speed The maximum EMIF speed on the C6713 device is 100 MHz. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). For ease of design evaluation, Table 44 contains IBIS simulation results showing the maximum EMIF-SDRAM interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be performed to verify that all AC timings are met for the specified board layout. Other configurations are also possible, but again, timing analysis must be done to verify proper AC timings. To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals).

Table 44. C6713 Example Boards and Maximum EMIF Speed

143 MHz 32-bit SDRAM (−7) 100 MHz

166 MHz 32-bit SDRAM (−6) For short traces, SDRAM data

183 MHz 32-bit SDRAM (−55)

200 MHz 32-bit SDRAM (−5)

125 MHz 16-bit SDRAM (−8E) 100 MHz

133 MHz 16-bit SDRAM (−75) 100 MHz

167 MHz 16-bit SDRAM (−6) 100 MHz

125 MHz 16-bit SDRAM (−8E)

167 MHz 16-bit SDRAM (−6)

143 MHz 32-bit SDRAM (−7) 83 MHz

166 MHz 32-bit SDRAM (−6) 83 MHz

183 MHz 32-bit SDRAM (−55) 83 MHz3-Loads

requirements can be met for the particular system.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

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The C6713 device resets using the active-low signal RESET and the internal reset signal. While RESET is low, the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of the internal reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts the processor running with the prescribed device configuration and boot mode. The C6713 has three types of boot modes: /C0068Host boot If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state , the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received. /C0068Emulation boot Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution, the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development. /C0068EMIF boot (using default ROM timings) Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored in the endian format that the system is using. The boot process also lets you choose the width of the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the “stalled” state and start running from address 0. reset A hardware reset (RESET) is required to place the DSP into a known good state out of power−up. The RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held low during power−up. Prior to deasserting RESET (low−to−high transition), the core and I/O voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 97POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2: All voltage values are with respect to VSS . recommended operating conditions† MIN NOM MAX UNIT CV DD Supply voltage, Core referenced to VSS PYP packages only 1.14 1.20 1.32 V CV DD Supply voltage, Core referenced to VSS GDP packages only 1.14‡ 1.20‡ 1.32 V DV DD Supply voltage, I/O referenced to VSS 3.13 3.3 3.47 V VIH High-level input voltage All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2 V VIH High-level input voltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2 V VIL Low-level input voltage All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 0.8 V VIL Low-level input voltage CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 0.3*DVDD V IOH High-level output current§ All signals except ECLKOUT, CLKOUT2, CLKOUT3 , CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 −8 mA OH ECLKOUT, CLKOUT2, and CLKOUT3 −16 mA I Low-level output current§ All signals except ECLKOUT, CLKOUT2, CLKOUT3 , CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 8 mA IOL Low-level output current§ ECLKOUT, CLKOUT2, and CLKOUT3 16 mA CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 3 mA VOS Maximum voltage during overshoot (See Figure 25) 4¶ V VUS Maximum voltage during undershoot (See Figure 26) −0.7¶ V TC Operating case temperature Default 0 90 /C0095CTC Operating case temperature A version (GDPA-200 and PYPA-167) –40 105 /C0095C † The core supply should be powered up prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage. ‡ These values are compatible with existing 1.26−V designs. § Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see the device-specific IBIS models. ¶ The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005

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electrical characteristics over recommended ranges of supply voltage and operating case temperature† (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage All signals except SCL1, SDA1, SCL0, and SDA0 IOH =MAX 2.4 V VOL Low-level output voltage All signals except SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V VOL voltage SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V II Input current All signals except SCL1, SDA1, SCL0, and SDA0 VI = VSS to DVDD ±170 uA II Input current SCL1, SDA1, SCL0, and SDA0 VI = VSS to DVDD ±10 uA IOZ Off-state output current All signals except SCL1, SDA1, SCL0, and SDA0 VO = DVDD or 0 V ±170 uA IOZ current SCL1, SDA1, SCL0, and SDA0 VO = DVDD or 0 V ±10 uA GDP, CVDD = 1.26 V, CPU clock = 225 MHz 625 mA IDD2V Core supply current‡ GDPA, CV DD = 1.26 V, CPU clock = 200 MHz 560 mA IDD2V Core supply current‡ PYP, CVDD =1.2 , CPU clock = 200 MHz 565 mA PYPA, CVDD = 1.2 V, CPU clock = 167 MHz 480 mA IDD3V I/O supply current‡ DV DD = 3.3 V, EMIF speed = 100 MHz 75 mA C i Input capacitance 7 pF C o Output capacitance 7 pF † For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. ‡ Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows: High-DSP-Activity Model: CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions; L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate Low-DSP-Activity Model: CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles; L2/EMIF EDMA: None] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C671 1D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A2 or later).

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information on these values, refer to the Recommended Operating Conditions section of this Data Sheet. Figure 25. AC Transient Specification Rise Time † tc = the peripheral cycle time. Figure 26. AC Transient Specification Fall Time † tc = the peripheral cycle time.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 101POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 45 and Figure 27). Figure 27 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device.

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Table 45. Board-Level Timings Example (see Figure 27)

1 Clock route delay

2 Minimum DSP hold time

3 Minimum DSP setup time

4 External device hold time requirement

5 External device setup time requirement

6 Control signal route delay

7 External device hold time

8 External device access time

9 DSP hold time requirement

10 DSP setup time requirement

11 Data route delay

† Control signals include data for Writes. ‡ Data signals are generated during Reads from an external device. Figure 27. Board-Level Input/Output Timings

† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. § See the PLL and PLL controller section of this data sheet. † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. § See the PLL and PLL controller section of this data sheet. Figure 28. CLKIN Timings

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† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. Figure 29. CLKOUT2 Timings † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2. Figure 30. CLKOUT3 Timings

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005

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ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles†‡§ (see Figure 33−Figure 34) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.5 ns 4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 ns 6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 3 ns 7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 2.3 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = ECLKOUT period in ns switching characteristics over recommended operating conditions for asynchronous memory cycles‡§¶ (see Figure 33−Figure 34) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS*E − 1.7 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH*E − 1.7 ns 5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 1.5 7 ns 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS*E − 1.7 ns 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals and EDx invalid WH*E − 1.7 ns 10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 1.5 7 ns 11 tosu(EDV-AWEL) Output setup time, ED valid to AWE low (WS−1)*E − 1.7 ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = ECLKOUT period in ns ¶ Select signals include: CEx, BE[3:0], EA[21:2], and AOE.

respectively, during asynchronous memory accesses. Figure 33. Asynchronous Memory Read Timing

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respectively, during asynchronous memory accesses. Figure 34. Asynchronous Memory Write Timing

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 109POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles† (see Figure 35) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns 7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns † The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ (see Figure 35 and Figure 36) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.2 7 ns 2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 7 ns 3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.2 ns 4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 7 ns 5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.2 ns 8 td(EKOH-ADSV) Delay time, ECLKOUT high to ARE/SDCAS /SSADS valid 1.2 7 ns 9 td(EKOH-OEV) Delay time, ECLKOUT high to, AOE/SDRAS /SSOE valid 1.2 7 ns 10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 ns 11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.2 ns 12 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE /SSWE valid 1.2 7 ns † The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ‡ ARE /SDCAS /SSADS , AOE/SDRAS /SSOE , and AWE/SDWE /SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

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Figure 35. SBSRAM Read Timing Figure 36. SBSRAM Write Timing

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 111POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles† (see Figure 37) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns 7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns † The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ (see Figure 37−Figure 43) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.5 7 ns 2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 7 ns 3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 ns 4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 7 ns 5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 ns 8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE/SDCAS /SSADS valid 1.5 7 ns 9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 ns 10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 ns 11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE /SSWE valid 1.5 7 ns 12 td(EKOH-RAS) Delay time, ECLKOUT high to, AOE/SDRAS /SSOE valid 1.5 7 ns † The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ‡ ARE /SDCAS /SSADS , AWE/SDWE /SSWE , and AOE/SDRAS /SSOE operate as SDCAS, SDWE , and SDRAS, respectively, during SDRAM accesses.

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Figure 37. SDRAM Read Command (CAS Latency 3)

Figure 38. SDRAM Write Command

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Figure 39. SDRAM ACTV Command Figure 40. SDRAM DCAB Command

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Figure 43. SDRAM MRS Command

‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS , AOE/SDRAS /SSOE , and AWE/SDWE /SSWE . time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS , AOE/SDRAS /SSOE , and AWE/SDWE /SSWE . Figure 44. HOLD/HOLDA Timing

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Figure 45. BUSREQ Timing

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 119POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 RESET TIMING timing requirements for reset†‡ (see Figure 46) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 1 tw(RST) Pulse duration, RESET 100 ns 13 tsu(HD) Setup time, HD boot configuration bits valid before RESET high§ 2P ns 14 th(HD) Hold time, HD boot configuration bits valid after RESET high§ 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For this device, the PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change the PLL mode in software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Phase-Lock Loop (PLL) Controller Peripheral Reference Guide (literature number SPRU233). § The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits consist of: HD[14, 8, 4:3]. switching characteristics over recommended operating conditions during reset¶ (see Figure 46) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 2 td(RSTH-ZV) Delay time, external RESET high to internal reset high and all signal groups valid#|| CLKMODE0 = 1 512 x CLKIN period ns 3 td(RSTL-ECKOL) Delay time, RESET low to ECLKOUT low 0 ns 4 td(RSTH-ECKOV) Delay time, RESET high to ECLKOUT valid 6P ns 5 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 invalid 0 ns 6 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid 6P ns 7 td(RSTL-CKO3L) Delay time, RESET low to CLKOUT3 low 0 ns 8 td(RSTH-CKO3V) Delay time, RESET high to CLKOUT3 valid 6P ns 9 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance|| 0 ns 10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group (BUSREQ) invalid|| 0 ns 11 td(RSTL-Z1HZ) Delay time, RESET low to Z group 1 high impedance|| 0 ns 12 td(RSTL-Z2HZ) Delay time, RESET low to Z group 2 high impedance|| 0 ns ¶ P = 1/CPU clock frequency in ns. Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while internal reset is asserted. # The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET is deasserted, the actual delay time may vary. ||EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS /SSADS , AWE/SDWE /SSWE , AOE/SDRAS /SSOE and HOLDA EMIF low group consists of: BUSREQ Z group 1 consists of: CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7], FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0. Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals.

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FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0. Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals. ‡ Boot and device configurations consist of: HD[14, 8, 4:3]. Figure 46. Reset Timing frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8. (when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8.

† P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. Figure 47. External/NMI Interrupt Timing

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005

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MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING timing requirements for McASP (see Figure 48 and Figure 49) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 1 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns 2 tw(AHCKRX) Pulse duration, AHCLKR/X high or low 7.5 ns 3 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X ext greater of 2P or 33 ns† ns 4 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X ext 14 ns 5 tsu(AFRXC-ACKRX) Setup time, AFSR/X input valid before ACLKR/X latches data ACLKR/X int 6 ns 5 tsu(AFRXC-ACKRX) Setup time, AFSR/X input valid before ACLKR/X latches dataACLKR/X ext 3 ns 6 th(ACKRX-AFRX) Hold time, AFSR/X input valid after ACLKR/X latches data ACLKR/X int 0 ns 6 th(ACKRX-AFRX ) Hold time, AFSR/X input valid after ACLKR/X latches dataACLKR/X ext 3 ns 7 tsu(AXR-ACKRX) Setup time, AXR input valid before ACLKR/X latches data ACLKR/X int 10.2 ns 7 tsu(AXR-ACKRX ) Setup time, AXR input valid before ACLKR/X latches dataACLKR/X ext 6 ns 8 th(ACKRX-AXR) Hold time, AXR input valid after ACLKR/X latches data ACLKR/X int 1 ns 8 th(ACKRX-AXR) Hold time, AXR input valid after ACLKR/X latches data ACLKR/X ext 3 ns † P = SYSCLK2 period. switching characteristics over recommended operating conditions for McASP‡ (see Figure 48 and Figure 49) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 9 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns 10 tw(AHCKRX) Pulse duration, AHCLKR/X high or low (AH/2) − 2.5 ns 11 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X int greater of 2P or 33 ns† ns 12 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X int (A/2) − 2.5 ns 13 td(ACKRX-AFRX) Delay time, ACLKR/X transmit edge to AFSX/R outputACLKR/X int −1 5 ns 13 td(ACKRX-AFRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X ext 0 10 ns 14 td(ACKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int −1 5 ns 14 td(ACKX-AXRV) Delay time, ACLKX transmit edge to AXR output validACLKR/X ext 0 10 ns 15 tdis(ACKRX−AXRHZ) Disable time, AXR high impedance following last data bitACLKR/X int −1 10 ns 15 tdis(ACKRX−AXRHZ ) Disable time, AXR high impedance following last data bit from ACLKR/X transmit edge ACLKR/X ext −1 10 ns † P = SYSCLK2 period. ‡ AH = AHCLKR/X period in ns. A = ACLKR/X period in ns.

falling edge (to shift data in). rising edge (to shift data in). Figure 48. McASP Input Timings

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rising edge (to shift data in). falling edge (to shift data in). Figure 49. McASP Output Timings

15 C b# Capacitive load for each bus line 400 400 pF

† The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. ‡ A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA−SCLH) ≥ 250 ns must then be met. I2C-Bus Specification) before the SCL line is released. region of the falling edge of SCL. ¶ The maximum th(SDA−SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. # C b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 50. I2C Receive Timings

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29 C p Capacitance for each I2C pin 10 10 pF

† C b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 51. I2C Transmit Timings

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 127POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 52, Figure 53, Figure 54, and Figure 55) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low 5 ns 2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low 4 ns 3 tw(HSTBL) Pulse duration, HSTROBE low (host read access) 10P + 5.8 ns3 tw(HSTBL) Pulse duration, HSTROBE low (host write access) 4P ns 4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns 10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low 5 ns 11 th(HASL-SELV) Hold time, select signals§ valid after HAS low 3 ns 12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns 13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 ns 14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns 18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns 19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. § Select signals include: HCNTL[1:0], HR/W, and HHWIL. switching characteristics over recommended operating conditions during host-port interface cycles†‡ (see Figure 52, Figure 53, Figure 54, and Figure 55) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 5 td(HCS-HRDY) Delay time, HCS to HRDY¶ 1 15 ns 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 15 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns 8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P − 4 ns 9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 ns 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 2 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 10P + 5.8 ns 17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 15 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. ||This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

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† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 52. HPI Read Timing (HAS Not Used, Tied High) † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2 )] OR HCS. Figure 53. HPI Read Timing (HAS Used)

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005

130 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 56) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X lowCLKR/X ext 0.5 * tc(CKRX) −1¶ ns 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 9 ns5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR lowCLKR ext 1 ns 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 6 ns6 th(CKRL-FRH) Hold time, external FSR high after CLKR lowCLKR ext 3 ns 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 8 ns7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0 ns 8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 3 ns8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4 ns 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 9 ns10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX lowCLKX ext 1 ns 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 6 ns11 th(CKXL-FXH) Hold time, external FSX high after CLKX lowCLKX ext 3 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. § The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. ¶ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 131POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 56) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNIT MIN MAX 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 1.8 10 ns 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1# C + 1# ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2 3 ns 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int −2 3 ns9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 2 9 ns 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bitCLKX int −1 4 ns12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX ext 1.5 10 ns 13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX int −3.2 + D1|| 4 + D2|| ns13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 0.5 + D1|| 10+ D2|| ns 14 td(FXH-DXV) Delay time, FSX high to DX valid FSX int −1.5 4.5 ns14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 2 9 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ¶ The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above). ||Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. If DXENA = 0, then D1 = D2 = 0 If DXENA = 1, then D1 = 2P, D2 = 4P

132 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 56. McBSP Timings

Figure 57. FSR Timing When GSYNC = 1 † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

134 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

† P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 58. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 135POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 59) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNITNO. MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 5 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 59) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNITNO. PARAMETER MASTER § SLAVE UNIT MIN MAX MIN MAX 1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶ L − 2 L + 3 ns 2 td(FXL-CKXH) Delay time, FSX low to CLKX high# T − 2 T + 3 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid −3 4 6P + 2 10P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low −4 4 6P + 1.5 10P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H − 2 H + 4 4P + 2 8P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

136 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 59. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

† P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. and FSR is inverted before being used internally. Figure 60. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005

138 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 61) NO. 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNITNO. MASTER SLAVE UNIT MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 5 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 61) NO. PARAMETER 13PYPA−167 13PYP−200 13GDPA−200 13GDP−225 UNITNO. PARAMETER MASTER § SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ H − 2 H + 3 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# T − 2 T + 3 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −3 4 6P + 2 10P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high −3.6 4 6P + 1.5 10P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L − 2 L + 4 4P + 2 8P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Figure 61. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

140 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

† P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. Figure 62. Timer Timing

† P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. the GPIO register through the CFGBUS. † P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. Figure 63. GPIO Port Timing

142 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Figure 64. JTAG Test-Port Timing

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005 143POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA The following tables show the thermal resistance characteristics for the GDP and PYP mechanical packages. thermal resistance characteristics (S-PBGA package) for GDP NO °C/W Air Flow (m/s)† Two Signals, Two Planes (4-Layer Board) 1 R ΘJC Junction-to-case 9.7 N/A 2 PsiJT Junction-to-package top 1.5 0.0

3 R ΘJB Junction-to-board 19 N/A

4 R ΘJA Junction-to-free air 22 0.0 5 R ΘJA Junction-to-free air 21 0.5 6 R ΘJA Junction-to-free air 20 1.0 7 R ΘJA Junction-to-free air 19 2.0 8 R ΘJA Junction-to-free air 18 4.0 9 PsiJB Junction-to-board 16 0.0 † m/s = meters per second thermal resistance characteristics (S-PQFP-G208 package) for PYP NO °C/W Junction-to-Pad Two Signals, Two Planes (4-Layer Board) − 208-pin PYP 1 R ΘJP Junction-to-pad, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 0.2 Junction-to-Package Top Two Signals, Two Planes (4-Layer Board) − 208-pin PYP 2 PsiJT Junction-to-package top, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 0.18 3 PsiJT Junction-to-package top, 7.5 x 7.5 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 0.23 Two Signals (2-Layer Board) 4 PsiJT Junction-to-package top, 26 x 26 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board. 0.18 5 PsiJT Junction-to-package top, 7.5 x 7.5 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board. 0.23 Junction-to-Still Air Two Signals, Two Planes (4-Layer Board) − 208-pin PYP 6 R ΘJA Junction-to-still air, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. 7 R ΘJA Junction-to-still air, 7.5 x 7.5 copper pad on top and bottom of PCB with solder connection and vias going to GND plane, isolated from power plane. Two Signals (2-Layer Board) 8 R ΘJA Junction-to-still air, 26 x 26 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board. 9 R ΘJA Junction-to-still air, 7.5 x 7.5 copper pad on top of PCB with solder connection and vias going to copper plane on bottom of board.

/C0084/C0077/C0083/C0051/C0050/C0048/C0067/C0054/C0055/C0049/C0051 /C0070/C0076/C0079/C0065/C0084/C0073/C0078/C0071/C0262/C0080/C0079/C0073/C0078/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SPRS186K − DECEMBER 2001 − REVISED OCTOBER 2005

144 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

For proper device thermal performance, the thermal pad must be soldered to an external ground thermal plane. This pad is electrically and thermally connected to the backside of the die. For the TMS320C6713 208−Pin PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal pad is externally flush with the mold compound. The following packaging information and addendum reflect the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMS320C6713GDP225 OBSOLETE BGA GDP 272 TBD Call TI Call TI TMS320C6713GDPA200 OBSOLETE BGA GDP 272 TBD Call TI Call TI TMS320C6713GDPX225 OBSOLETE BGA GDP 272 TBD Call TI Call TI TMS320C6713PYP200 OBSOLETE HLQFP PYP 208 TBD Call TI Call TI TMS320C6713PYP200B OBSOLETE HLQFP PYP 208 TBD Call TI Call TI TMS320C6713PYPX200 OBSOLETE HLQFP PYP 208 TBD Call TI Call TI TMX320C6713GDP OBSOLETE BGA GDP 272 TBD Call TI Call TI TMX320C6713GFN OBSOLETE BGA GFN 272 TBD Call TI Call TI TMX320C6713PYP OBSOLETE HLQFP PYP 208 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Mar-2006 Addendum-Page 1

MPBG274 – MAY 2002 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GDP (S–PBGA–N272) PLASTIC BALL GRID ARRAY 2468 2 0 1816141210 M E A C B D G F H K J L W R N P U T V Y 3 57 9 11 171513 19 0,635 0,635 26,80SQ 23,80 24,20SQ 27,20 24,13 TYP 0,57 0,65 0,60 0,90 Seating Plane 0,50 0,70 2,57 MAX 0,15 0,10 A1 Corner 1,27 1,27 4204396/A 04/02 Bottom View 1,12 1,22 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151

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