SM320C32-EP TI1 | Alldatasheet
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Controlled Baseline − One Assembly/Test Site, One Fabrication Site /C0068Extended Temperature Performance of −55°C to 125°C /C0068Enhanced Diminishing Manufacturing Sources (DMS) Support /C0068Enhanced Product Change Notification /C0068Qualification Pedigree† /C0068High-Performance Floating-Point Digital Signal Processor (DSP) SM320C32-50EP (5 V) − 40-ns Instruction Cycle Time − 275 MOPS − 50 MFLOPS − 25 MIPS SM320C32-60EP (5 V) − 33-ns Instruction Cycle Time − 330 MOPS − 60 MFLOPS − 30 MIPS /C006832-Bit High-Performance CPU /C006816-/32-Bit Integer and 32-/40-Bit Floating-Point Operations /C006832-Bit Instruction Word, 24-Bit Addresses /C0068Two 256 × 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks /C0068Flexible Boot-Program Loader /C0068On-Chip Memory-Mapped Peripherals: − One Serial Port − Two 32-Bit Timers − Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities /C0068Enhanced External Memory Interface That Supports 8-/16-/32-Bit-Wide External RAM for Data Access and Program Execution From 16-/32-Bit-Wide External RAM /C0068SMJ320C30 and SMJ320C31 Object Code Compatible /C0068Fabricated Using Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments /C0068144-Pin Plastic Quad Flatpack (PCM Suffix) 5 V /C0068Eight Extended-Precision Registers /C0068Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) /C0068Two Low-Power Modes /C0068Two- and Three-Operand Instructions /C0068Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle /C0068Block-Repeat Capability /C0068Zero-Overhead Loops With Single-Cycle Branches /C0068Conditional Calls and Returns /C0068Interlocked Instructions for Multiprocessing Support /C0068One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits /C0068Two Sets of Memory Strobes (STRB0 and STRB1 ) and One I/O Strobe (IOSTRB) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals /C0068Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size /C0068STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes) /C0068Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. EPIC is a trademark of Texas Instruments Incorporated. All trademarks are the property of their respective owners. Copyright 2002, Texas Instruments Incorporated
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002
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description
The SM320C32-EP is a member of the 320C3x generation of digital signal processors from Texas Instruments. The SM320C32-EP is an enhanced 32-bit floating-point processor manufactured in 0.7-µm triple-level-metal CMOS technology. The enhancements to the 320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts. The internal busing and special digital signal processing instruction set of the SM320C32-EP have the speed and flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SM320C32-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001. part order information DEVICE TECHNOLOGY POWER SUPPLY OPERATING FREQUENCY PACKAGE TYPE PROCESSING LEVEL SM320C32PCMM50EP 0.65-µm CMOS 5 V ± 5% 50 MHz Plastic 144-lead quad flatpack EP SM320C32PCMM60EP 0.65-µm CMOS 5 V ± 5% 60 MHz Plastic 144-lead quad flatpack EP
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 STRB1_B2/ A PCM PACKAGE † (TOP VIEW) V V DV DD VSSL VSSL DV SS CV SS D10 DV DD D11 IVSS D12 VDDL VDDL D13 D14 D15 D16 D17 DV DD D18 D19 D20 D21 DV SS CV SS DR0 DV DD FSR0 CLKR0 CLKX0 FSX0 DX0 IVSS SHZ TCLK0 TCLK1 DV DD EMU3 EMU0 VDDL VDDL EMU1 EMU2 VSSL MCBL/ MP CV SS DV SS A23 A22 A21 A20 A19 A18 DV DD A17 A16 A15 A14 A13 CV SS DV SS NC144 INT3 INT2 143 142 INT1141 INT0140 IACK139 XF1138 XF0137 DV136 CV135 RESET134 PRGW133 R/W132 STRB1_B0131 STRB1_B1130 129 128 127 STRB1_B3/ A126 125 V124 STRB0_B0123 STRB0_B1122 STRB0_B2/ A121 STRB0_B3/ A120 IOSTRB119 IV118 117 DV116 HOLD115 HOLDA114 CLKIN113 112 108 107 106 105 104 103 102 101 100 NC A12 A11 A10 DD DDL SSL SSL DD D31 D30 D29 D28 D27 D26 SS D25 DD D24 D23 DDL 111 CV 110 NC109 D22 NC RDY SS V DV SSCV DDDV DV V V DV V V DV IV DV SS SS SSL DDL DDL SS DD SS SS SUBS DV DD † NC=No internal connection
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002
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1 DR0 30 A17 59 DV DD 88 IVSS 117 RDY
2 DV DD 31 A16 60 D31 89 D11 118 IVSS
3 FSR0 32 A15 61 D30 90 DV DD 119 IOSTRB
4 CLKR0 33 A14 62 D29 91 D10 120 STRB0_B3 /A−1
5 CLKX0 34 A13 63 D28 92 CV SS 121 STRB0_B2 /A−2
6 FSX0 35 CV SS 64 D27 93 DV SS 122 STRB0_B1
7 DX0 36 DV SS 65 D26 94 VSSL 123 STRB0_B0
8 IVSS 37 NC 66 IVSS 95 VSSL 124 VDDL
9 SHZ 38 A12 67 D25 96 D9 125 VDDL
10 TCLK0 39 DV DD 68 DV DD 97 D8 126 STRB1_B3 /A−1
11 TCLK1 40 A11 69 D24 98 D7 127 VSSL
12 DV DD 41 A10 70 D23 99 D6 128 STRB1_B2 /A−2
13 EMU3 42 A9 71 D22 100 D5 129 DV DD
14 EMU0 43 A8 72 NC 101 D4 130 STRB1_B1
15 VDDL 44 A7 73 CV SS 102 DV DD 131 STRB1_B0
16 VDDL 45 A6 74 DV SS 103 D3 132 R/W
17 EMU1 46 DV DD 75 D21 104 D2 133 PRGW
18 EMU2 47 A5 76 D20 105 D1 134 RESET
19 VSSL 48 A4 77 D19 106 D0 135 CV SS
20 MCBL/MP 49 A3 78 D18 107 H1 136 DV SS
21 CV SS 50 VDDL 79 DV DD 108 H3 137 XF0
22 DV SS 51 VDDL 80 D17 109 NC 138 XF1
23 A23 52 A2 81 D16 110 VSUBS 139 IACK
24 A22 53 CV SS 82 D15 111 CV SS 140 INT0
25 A21 54 DV SS 83 D14 112 DV SS 141 INT1
26 A20 55 A1 84 D13 113 CLKIN 142 INT2
27 A19 56 VSSL 85 VDDL 114 HOLDA 143 INT3
28 A18 57 VSSL 86 VDDL 115 HOLD 144 NC
29 DV DD 58 A0 87 D12 116 DV DD
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 pin functions This section provides signal descriptions for the SM320C32-EP device. The following table lists each signal (grouped by function), the number of pins, operating modes, and a brief signal description. Pin Functions PIN TYPE † DESCRIPTION CONDITIONS WHEN NAME NO. TYPE † DESCRIPTION WHEN SIGNAL IS IN HIGH Z‡ EXTERNAL BUS INTERFACE (70 PINS) D31−D0 32 I/O/Z 32-bit data port of the external bus interface S H R A23−A0 24 O/Z 24-bit address port of the external bus interface S H R R/W 1 O/Z Read/write for external memory interface. R/ W is high when a read is performed and low when a write is performed over the parallel interface. S H R IOSTRB 1 O/Z External peripheral I/O strobe for the external memory interface S H STRB0_B3 /A−1 1 O/Z External memory-access strobe 0, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interfaceS H STRB0_B2 /A−2 1 O/Z External memory-access strobe 0, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface S H STRB0_B1 1 O/Z External memory-access strobe 0, byte enable 1 for the external memory interface S H STRB0_B0 1 O/Z External memory-access strobe 0, byte enable 0 for the external memory interface S H STRB1_B3 /A−1 1 O/Z External memory-access strobe 1, byte enable 3 for 32-bit external memory interface and address pin for 8-bit and 16-bit external memory interfaceS H STRB1_B2 /A−2 1 O/Z External memory-access strobe 1, byte enable 2 for 32-bit external memory interface and address pin for 8-bit external memory interface S H STRB1_B1 1 O/Z External memory-access strobe 1, byte enable 1 for the external memory interface S H STRB1_B0 1 O/Z External memory-access strobe 1, byte enable 0 for the external memory interface S H RDY 1 I Ready. RDY indicates that the external device is prepared for an external memory interface transaction to complete. HOLD 1 I Hold signal for external memory interface. When HOLD is a logic low, any ongoing transaction is completed. A23−A0, D31−D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R/W are placed in the high-impedance state, and all transactions over the external memory interface are held until HOLD becomes a logic high or the NOHOLD bit of the STRB0 bus-control register is set. HOLDA 1 O/Z Hold acknowledge for external memory interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23−A0, D31−D0, IOSTRB , STRB0_Bx, STRB1_Bx, and R/ W are in the high-impedance state and that all transactions over the memory are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the external bus-control register is set. S PRGW 1 I Program memory width select. When PRGW is a logic low, program is fetched as a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are performed to fetch a single 32-bit instruction word. The status of PRGW at device reset affects the reset value of the STRB0 and STRB1 bus-control register. † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF.
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002
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Pin Functions (Continued) PIN CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ DESCRIPTIONTYPE † NAME CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ DESCRIPTIONTYPE † NO. CONTROL SIGNALS (9 PINS) RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. INT3−INT0 4 I External interrupts CONTROL SIGNALS (9 PINS) (CONTINUED) IACK 1 O/Z Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. This signal can be used to indicate the beginning or end of an interrupt-service routine.S MCBL/MP 1 I Microcomputer bootloader/microprocessor mode XF1−XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/ Os or used to support interlocked-processor instructions. S R SERIAL PORT SIGNALS (6 PINS) CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. S R DX0 1 I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0.S R FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data process over DX0. S R CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R DR0 1 I/O/Z Data receive. Serial port 0 receives serial data on DR0. S R FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the receive-data process over DR0. S R TIMER SIGNALS (2 PINS) TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S R TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. S R CLOCK SIGNALS (3 PINS) CLKIN 1 I Input to the internal oscillator from an external clock source H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S RESERVED (5 PINS) EMU0−EMU2 3 I Reserved for emulation. Use 18 kΩ−22 kΩ pullup resistors to 5 V. EMU3 1 O/Z Reserved for emulation S SHZ 1 I Shutdown high impedance. When active, SHZ shuts down the C32 and places all 3-state I/O pins in the high-impedance state. SHZ is used for board-level testing to ensure that no dual drive conditions occur. CAUTION: A low on SHZ corrupts C32 memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF.
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Functions (Continued) PIN CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ DESCRIPTIONTYPE † NAME CONDITIONS WHEN SIGNAL IS IN HIGH Z‡ DESCRIPTIONTYPE † NO. POWER/GROUND CV SS 7 I Ground DV SS 7 I Ground IVSS 4 I Ground DV DD 12 I 5 Vdc supply§ VDDL 8 I 5 Vdc supply§ VSSL 6 I Ground VSUBS 1 I Substrate, tie to ground † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor is 0.1 µF.
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002
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ÉÉÉ Boot ROM Program Cache (64 × 32) RAM Block 0 (256 × 32) RAM Block 1 (256 × 32) IR PC CPU1 REG1 REG2 Multiplexer BKARAU0 ARAU1 DISP0, IR0, IR1 Extended- Precision Registers (R0−R7) Auxiliary Registers (AR0 − AR7) Other Registers (12) Multiplier 32-Bit Barrel Shifter ALU External Memory Interface Serial Port ÉÉÉ ÉÉÉ Data-Transmit Register Data-Receive Register FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Timer 0 Global-Control Register Timer-Period Register Timer-Counter Register TCLK0 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register TCLK1 PDATA Bus PADDR Bus DDATA Bus DADDR1 Bus DADDR2 Bus DMADATA Bus 32 24 24 24 2432 32 32 CPU2 32 32 40 40 ÉÉÉ ÉÉÉ Serial Port- Control Reg. ÉÉÉÉÉ ÉÉÉÉÉ Receive/Transmit (R/X)Timer Register Controller Peripheral Address Bus CPU1 REG1 REG2 DMAADDR Bus STRB0 Control Reg. STRB1 Control Reg. IOSTRB Control Reg. STRB1 IOSTRB STRB0 Peripheral Data Bus RESET INT(3-0) IACK XF(1,0) MCBL / MP CLKIN VDD VSS SHZ EMU0−3 Multiplexer A23 − A0 D31 − D0 R/W RDY HOLD HOLDA PRGW STRB0_B3 /A−1 STRB0_B2 /A−2 STRB0_B1 STRB0_B0 IOSTRB Multiplexer DMA Controller Global-Contol Register Source-Address Register Destination-Address Reg. Transfer-Counter Reg. DMA Channel 0 Global-Control Register Source-Address Register Destination-Address Reg. Transfer-Counter Reg. DMA Channel 1 STRB1_B 3/A−1 STRB1_B 2/A−2 STRB1_B1 STRB1_B0 operation Operation of the SM320C32-EP is identical to the 320C30 and 320C31 digital signal processors, with the exception of an enhanced external memory interface and the addition of two CPU power-management modes. external memory interface The SM320C32-EP has a configurable external memory interface with a 24-bit address bus, a 32-bit data bus, and three independent multi-function strobes. The flexibility of this unique interface enables product designers to minimize external memory-chip count.
Up to three mutually exclusive memory areas—one program area and two data areas—can be implemented. memory areas configurations. See Figure 1. Figure 1. C32 External Memory Interface 32 bits if the PRGW signal is low. SM320C32-EP memory map, showing the address ranges for which the strobe signals become active. consecutive 8-bit locations, each having its own address.
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(least significant address bits) and the STRBx_B0 pin functions as a byte-enable (chip-select) pin. STRBx_B1 is unused. See Figure 2. Figure 2. C32 With 8-Bit-Wide External Memory address bits). The STRBx_B0 and STRBx_B1 pins function as byte-enable (chip-select) pins. STRBx_B2 /A−2 is unused. See Figure 3. Figure 3. C32 With 16-Bit-Wide External Memory
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Figure 5. C32 With 32-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and 32-Bit and program words can be stored and retrieved as half words. Figure 6. C32 With 16-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and a 32-Bit
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User’s Guide (literature number SPRU132B) for a detailed description of this memory mapping. Figure 8. SM320C32-EP Memory Map
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 power management The SM320C32-EP CPU has two power-management modes, IDLE2 and LOPOWER (low power). In IDLE2 mode, no instructions are executed and the CPU, peripherals, and memory retain their previous state while the external bus output pins are idle. During IDLE2 mode, the H1 clock signal is held high while the H3 clock signal is held low until one of the four external interrupts is asserted. In the LOPOWER mode, the CPU continues to execute instructions and the DMA continues to perform transfers, but at a reduced clock rate of the CLKIN frequency divided by 16 (that is, SM320C32-EP with a 32-MHz CLKIN frequency performs the same as a 2-MHz SM320C32-EP with an instruction cycle time of 1000 ns or 1 MHz. bootloader The SM320C32-EP flexible bootloader loads programs from the serial port, EPROM, or other standard non-volatile memory device. The boot-loader functionality of the SM320C32-EP is equivalent to that of the 320C31, and has added modes to handle the data-type sizes and memory widths supported by the external memory interface. The memory-bootload supports data transfers with and without handshaking. The handshake mode allows synchronous transfer of programs by using two pins as data-acknowledge and data-ready signals. peripherals The SM320C32-EP peripherals are comprised of one serial port, two timers, and two DMA channels. The serial port and timers are functionally identical to those in the 320C31 peripherals. The SM320C32-EP two-channel DMA coprocessor has user-configurable priorities: CPU, DMA, or rotating between CPU and DMA.
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Figure 9 shows the SM320C32-EP peripheral-bus control-register mapping. Figure 9. Peripheral-Bus Memory-Mapped Registers
To reduce external logic and simplify the interface, the external interrupts can be either edge- or level-triggered. a user-relocatable interrupt-trap vector table. The interrupt-trap vector table must start on a 256-word boundary. address 0h as shown in Figure 8. Figure 10. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002
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absolute maximum ratings over specified temperature ranges (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS . 2. This value calculated for the C32-40. Actual operating power is less. This value was obtained under specially produced worst-case test conditions which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external bus at the maximum rate possible. See normal (IDD ) current specification in the electrical characteristics table and see the Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020). recommended operating conditions (see Note 3) MIN NOM ‡ MAX UNIT VDD Supply voltage (DVDD , VDDL ) 4.75 5 5.25 V VSS Supply voltage (CVSS , VSSL , IVSS , DVSS , VSUBS ) 0 V VIH High-level input voltage CLKIN 2.6 VDD + 0.3* V VIH High-level input voltage All other inputs 2 VDD + 0.3* V VIL Low-level input voltage −0.3* 0.8 V IOH High-level output current −300 µA IOL Low-level output current 2 mA TC Operating case temperature (see Note 4) −55 125 °C * This parameter is not production tested. ‡ All nominal values are at VDD = 5 V, TA (ambient-air temperature)= 25°C. NOTE 3: All input and output voltage levels are TTL compatible. NOTE 4: T C MAX at maximum rated operating conditions at any point on case. TC MIN at initial (time zero) power-up. electrical characteristics over recommended ranges of supply voltage (unless otherwise noted) ‡ PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VOH High-level output voltage VDD = MIN, I OH = MAX 2.4 3 V VOL Low-level output voltage VDD = MIN, I OL = MAX 0.3 0.8 V IOZ High-impedance state output current VDD = MAX − 20 20 µA II Input current VI = VSS to VDD − 10 10 µA fx = 50 MHz‡ TA = 25 °C, V DD = MAX, 200 425 mA IDD Supply current (see Note 5) fx = 60 MHz‡ TA = 25 C, V DD = MAX, fx = MAX‡ 225 475 mA IDD Supply current (see Note 5) Standby IDLE2, CLKIN shut off 50 µA CLKIN 25 C I Input capacitance All other inputs 15* pF C o Output capacitance 20* pF * This parameter is not production tested. ‡ All nominal values are at VDD = 5 V, TA = 25°C. ‡ fx is the input clock frequency. NOTE 5: Actual operating current is less than this maximum value (see Note 2).
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002
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PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameter symbology Timing parameter symbols used in this document are in accordance with JEDEC Standard 100-A. Unless otherwise noted, in order to shorten the symbols, pin names and other related terminology have been abbreviated as follows: A A23−A0 when the physical-memory-width-bit field of the STRBx control register is set to 32 bits A23−A0 and STRBx_B3 /A−1 when the physical-memory-width-bit field of the STRBx control register is set to 16 bits A23−A0, STRBx_B3 /A−1, and STRBx_B2/A−2 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits CI CLKIN RDY RDY D D(31−0) H H1, H3 IOS IOSTRB Pt c(H) Qt c(CI) RW R/W S STRBx_B(3−0) when the physical-memory-width-bit field of the STRBx control register is set to 32 bits STRBx_B(1−0) when the physical-memory-width-bit field of the STRBx control register is set to 16 bits STRBx_B0 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits XF XF0 or XF1
† Minimum CLKIN high-pulse duration at 3.3 MHz is 10 ns.
- This parameter is not production tested.
Figure 14. CLKIN Timing
- This parameter is not production tested.
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Figure 15. H1/H3 Timing
- This parameter is not production tested.
Figure 16. Memory-Read-Cycle Timing
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Figure 17. Memory-Write-Cycle Timing
- This parameter is not production tested.
Figure 18. Memory-Read-Cycle Timing Using IOSTRB
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- This parameter is not production tested.
Figure 19. Memory-Write-Cycle Timing Using IOSTRB
Figure 20. XF0 and XF1 When Executing LDFI or LDII
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executing, the address of the store is not driven until the store can execute. Figure 21. XF0 When Executing a STFI or STII
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- This parameter is not production tested.
NOTE A: I/OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register. Figure 24. Change of XF From Output to Input Mode
NOTE A: I/OXFx represents either bit 1 or bit 5 of the IOF register. Figure 25. Change of XF From Input to Output Mode
32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
- This parameter is not production tested.
10 H1 Clock Cycles
sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. kΩ, if undesirable spurious writes can occur when these outputs go low. (MCBL / MP = 1), the reset vector is fetched two times, with no software wait states. D. Control signals include STRBx and IOSTRB. E. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLKx. Figure 26. RESET Timing
- This parameter is not production tested.
Figure 27. INT3−INT0 Interrupt-Response Timing
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NOTES: 6. IACK is active for the entire duration of the bus cycle and is extended if the bus cycle utilizes wait states.
- IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
phase of the IACK instruction is extended. Figure 28. IACK Timing
/C0083/C0077/C0051/C0050/C0048/C0067/C0051/C0050/C0262/C0069/C0080 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS038 − AUGUST 2002 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 serial-port timing serial-port timing [P = tc(H)] (see Figure 29 and Figure 30) NO. 320C32-50 320C32-60 UNITNO. MIN MAX MIN MAX UNIT 65 td(H1-SCK) Delay time, H1 high to internal CLKX/R high/low 10 8 ns 66 tc(SCK) Cycle time, CLKX/R ext 2.6P 2.6P ns66 tc(SCK) Cycle time, CLKX/R CLKX/R int 2P (232)P 2P (232)P ns 67 tw(SCK) Pulse duration, CLKX/R ext P + 10 P + 10 ns67 tw(SCK) Pulse duration, CLKX/R high/low CLKX/R int [tc(SCK)/2]−5 [tc(SCK)/2]+5 [tc(SCK)/2]−5 [tc(SCK)/2]+5 ns 68 tr(SCK) Rise time, CLKX/R 6 5 ns 69 tf(SCK) Fall time, CLKX/R 6 5 ns 70 td(DX) Delay time, CLKX CLKX ext 24 20 ns70 td(DX) Delay time, CLKX to DX valid CLKX int 16 15 ns 71 tsu(DR) Setup time, DR CLKR ext 9 8 ns71 tsu(DR) Setup time, DR before CLKR low CLKR int 17 15 ns 72 th(DR) Hold time, DR CLKR ext 7 6 ns72 th(DR) Hold time, DR from CLKR low CLKR int 0 0 ns 73 td(FSX) Delay time, CLKX to internal FSX CLKX ext 22 20 ns73 td(FSX) to internal FSX high/low CLKX int 15 14 ns 74 tsu(FSR) Setup time, FSR CLKR ext 7 6 ns74 tsu(FSR) Setup time, FSR before CLKR low CLKR int 7 6 ns 75 th(FS) Hold time, FSX/R input from CLKX/R ext 7 6 ns75 th(FS) input from CLKX/R low CLKX/R int 0 0 ns 76 tsu(FSX) Setup time, external FSX CLKX ext 8−P [tc(SCK)/2]−10* 8−P [tc(SCK)/2]−10* ns76 tsu(FSX) external FSX before CLKX high CLKX int 21−P tc(SCK)/2* 21−P tc(SCK)/2* ns 77 td(CH-DX)V Delay time, CLKX to first DX bit, FSX CLKX ext 24* 20* ns77 td(CH-DX)V to first DX bit, FSX precedes CLKX high CLKX int 14* 12* ns 78 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 24* 20* ns 79 td(DXZ) Delay time, CLKX high to DX in the high-impedance state following last data bit 14* 12* ns * This parameter is not production tested.
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NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 29. Fixed Data-Rate-Mode Timing NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 30. Variable Data-Rate-Mode Timing
- This parameter is not production tested.
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high. Figure 31. HOLD/HOLDA Timing
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of internal control registers associated with each peripheral. Figure 32. Peripheral-Pin General-Purpose I/O Timing
- This parameter is not production tested.
of internal control registers associated with each peripheral. Figure 33. Timing of Peripheral Pin Changing From General-Purpose Output to Input Mode
of internal control registers associated with each peripheral. Figure 34. Timing of Peripheral Pin Changing From General-Purpose Input-to-Output Mode
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
- This parameter is not production tested.
Figure 35. Timing for Timer Pin
- This parameter is not production tested.
NOTE A: Enabling SHZ destroys C32 register and memory contents. Assert SHZ = 1 and reset the C32 to restore it to a known condition. Figure 36. SHZ Pin Timing Table 1. Thermal Resistance Characteristics for PCM package
www.ti.com 31-Mar-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SM320C32PCMM50EP NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR SM320C32PCMM60EP NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR V62/03616-01XE NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR V62/03616-02XE NRND QFP PCM 144 24 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MQFP022A – JANUARY 1995 – REVISED MAY 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCM (S-PQFP-G***) PLASTIC QUAD FLATPACK 4040024/B 10/94
144 PINS SHOWN
0,38 0,22 NO. OF PINS*** 22,75 TYP 25,35 TYP 0,16 NOM 0,25 0,73 1,03 Seating Plane 0,25 MIN Gage Plane 108 109 144 A SQ SQ31,45 28,20 30,95 27,80 3,60 3,20 4,10 MAX 0,10 0,65 M0,13 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022 D. The 144 PCM is identical to the 160 PCM except that four leads per corner are removed.
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