SMJ320C31_07 TI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 59
Technical content
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Processed to MIL-PRF-38535 (QML) /C0068Operating Temperature Ranges: − Military (M) −55°C to 125°C − Special (S) −55°C to 105°C /C0068SMD Approval /C0068High-Performance Floating-Point Digital Signal Processor (DSP): − SMJ320C31-60 (5 V) 33-ns Instruction Cycle Time
330 Million Operations Per Second
(MOPS), 60 Million Floating-Point Operations Per Second (MFLOPS),
30 Million Instructions Per Second
(MIPS) − SMJ320C31-50 (5 V) 40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
− SMJ320C31-40 (5 V) 50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
− SMJ320LC31-40 (3.3 V) 50-ns Instruction Cycle Time − SMQ320LC31-40 (3.3 V) 50-ns Instruction Cycle Time /C006832-Bit High-Performance CPU /C006816-/32-Bit Integer and 32-/40-Bit Floating-Point Operations /C006832-Bit Instruction and Data Words, 24-Bit Addresses /C0068Two 1K Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks /C0068Boot-Program Loader /C006864-Word × 32-Bit Instruction Cache /C0068Eight Extended-Precision Registers /C0068Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) /C0068Two Low-Power Modes /C0068On-Chip Memory-Mapped Peripherals: − One Serial Port Supporting 8-/16-/24-/32-Bit Transfers − Two 32-Bit Timers − One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation /C0068Fabricated Using Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments (TI) /C0068Two- and Three-Operand Instructions /C006840 / 32-Bit Floating-Point /Integer Multiplier and Arithmetic Logic Unit (ALU) /C0068Parallel ALU and Multiplier Execution in a Single Cycle /C0068Block-Repeat Capability /C0068Zero-Overhead Loops With Single-Cycle Branches /C0068Conditional Calls and Returns /C0068Interlocked Instructions for Multiprocessing Support /C0068Bus-Control Registers Configure Strobe-Control Wait-State Generation /C0068Validated Ada Compiler /C0068Integer, Floating-Point, and Logical Operations /C006832-Bit Barrel Shifter /C0068One 32-Bit Data Bus (24-Bit Address) /C0068Packaging − 132-Lead Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) − 141-Pin Ceramic Staggered Pin Grid- Array Package (GFA Suffix) − 132-Lead TAB Frame − 132-Lead Plastic Quad Flatpack (PQ Suffix)
description
The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.6-µm triple-level-metal CMOS technology. The devices are part of the SMJ320C3x generation of DSPs from Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 EPIC is a trademark of Texas Instruments Incorporated. Copyright 2006, Texas Instruments Incorporated /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
description (continued) The SMJ320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 60 MFLOPS. The SMJ320C3x optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The SMJ320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features. General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SMJ320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic. For additional information when designing for cold temperature operation, please see Texas Instruments application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature number SGUA001.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TA PACKAGE (TOP VIEW) TB PACKAGE (TOP VIEW) Die Face Up Tab Leads Up 132 100 6733 Die Face Up Tab Leads Up 100 132 B DF H K M PTV 141-PIN GFA STAGGERED GRID ARRAY PACKAGE (BOTTOM VIEW) ACE G J LNRUW 132-PIN HFG QUAD FLATPACK (TOP VIEW) ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ 100 991 132 6733
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SMQ320LC31 pinout (top view) The SMQ320LC31 device is also packaged in a132-pin plastic quad flatpack (PQ Suffix). The full part numbers are SMQ320LC31PQM40 and 5962-9760601NXB. VDD VSS D31 VDD VDD D30 VSS VSS D29 D28 VDD D27 VSS D26 D25 D24 D23 D22 D21 VSS X2/CLKIN HOLDA HOLD VDD RDY STRB R/W RESET XF0 VDD XF1 IACK INT0 VSS VSS VDD VDD INT2 INT3 DR0 VSS FSR0 CLKR0 CLKX0 VSS FSX0 /C0049/C0055/C0049/C0054/C0049/C0053/C0049/C0052/C0049/C0051/C0049/C0050/C0049/C0049 /C0049/C0048 /C0057 /C0056 /C0055 /C0054 /C0053 /C0052 /C0051 /C0050 /C0049 /C0049/C0051/C0050 /C0049/C0051/C0049 /C0049/C0051/C0048 /C0049/C0050/C0057 /C0049/C0050/C0056 /C0049/C0050/C0055 /C0049/C0050/C0054 /C0049/C0050/C0053 /C0049/C0050/C0052 /C0049/C0050/C0051 /C0049/C0050/C0050 /C0049/C0050/C0049 /C0049/C0050/C0048 /C0049/C0049/C0057 /C0049/C0049/C0056 /C0049/C0049/C0055 /C0049/C0049/C0054 /C0049/C0049/C0053 /C0049/C0049/C0052 /C0049/C0049/C0051 /C0049/C0049/C0050 /C0049/C0049/C0049 /C0049/C0049/C0048 /C0049/C0048/C0057 /C0049/C0048/C0056 /C0049/C0048/C0055 /C0049/C0048/C0054 /C0049/C0048/C0053 /C0049/C0048/C0052 /C0049/C0048/C0051 /C0049/C0048/C0050 /C0049/C0048/C0049 /C0049/C0048/C0048 /C0057/C0057 /C0057/C0056 /C0057/C0055 /C0057/C0054 /C0057/C0053 /C0057/C0052 /C0057/C0051 /C0057/C0050 /C0057/C0049 /C0057/C0048 /C0056/C0057 /C0056/C0056 /C0056/C0055 /C0056/C0054 /C0056/C0053 /C0056/C0052 /C0051/C0054 /C0053/C0048 /C0052/C0057 /C0052/C0056 /C0052/C0055 /C0052/C0054 /C0052/C0053 /C0052/C0052 /C0052/C0051 /C0052/C0050 /C0052/C0049 /C0052/C0048 /C0051/C0057 /C0051/C0056 /C0051/C0055 /C0051/C0053 /C0051/C0052 /C0051/C0051 /C0051/C0050 /C0051/C0049 /C0051/C0048 /C0050/C0057 /C0050/C0056 /C0050/C0055 /C0050/C0054 /C0050/C0053 /C0050/C0052 /C0050/C0051 /C0050/C0050 /C0050/C0049 /C0050/C0048 /C0049/C0057 /C0049/C0056 DDV A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 SSV SSV /C0053/C0049 /C0053/C0050 /C0053/C0051 /C0053/C0052 /C0053/C0053 /C0053/C0054 /C0053/C0055 /C0053/C0056 /C0053/C0057 /C0054/C0048 /C0054/C0049 /C0054/C0050 /C0054/C0051 /C0054/C0052 /C0054/C0053 /C0054/C0054 /C0054/C0055 /C0054/C0056 /C0054/C0057 /C0055/C0048 /C0055/C0049 /C0055/C0050 /C0055/C0051 /C0055/C0052 /C0055/C0053 /C0055/C0054 /C0055/C0055 /C0055/C0056 /C0056/C0048 /C0056/C0049 /C0056/C0050 /C0056/C0051 DDV DDV A22 A23 MCBL/MP EMU2 EMU1 EMU0 EMU3 TCLK1 SHZ DDV D18 D16 D15 D14 D13 D12 D11 D10 DDV DDV SSV /C0055/C0057 VSS VSS VDD D20 A10D19 VDD DX0 INT1 SSV A11 DDV SSV TCLK0 SSV SSV VSS VSS SSV D17 SSV DDV SSV SSV SSV DDV DDV PQ PACKAGE (TOP VIEW)
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Assignments PIN PIN NUMBER NUMBER PQ PKG HFG PKG GFA PKG NAME PQ PKG HFG PKG GFA PKG NAME 29 12 L1 A0 64 47 W9 D10 28 11 K2 A1 63 46 U9 D11 27 10 J1 A2 62 45 V8 D12 26 9 J3 A3 60 43 W7 D13 25 8 G1 A4 58 41 U7 D14 23 6 F2 A5 56 39 V6 D15 22 5 E1 A6 55 38 W5 D16 21 4 E3 A7 54 37 U5 D17 20 3 D2 A8 53 36 V4 D18 18 1 C1 A9 52 35 W3 D19 16 131 C3 A10 50 33 U3 D20 14 129 B2 A11 48 31 V2 D21 13 128 A1 A12 47 30 W1 D22 12 127 C5 A13 46 29 R3 D23 11 126 B4 A14 45 28 T2 D24 10 125 A3 A15 44 27 U1 D25 9 124 C7 A16 43 26 N3 D26 8 123 B6 A17 41 24 P2 D27 7 122 C9 A18 39 22 R1 D28 5 120 B8 A19 38 21 L3 D29 2 117 A7 A20 34 17 M2 D30 1 116 A9 A21 31 14 N1 D31 130 113 B10 A22 108 91 C19 DR0 129 112 A11 A23 116 99 C17 DX0 111 94 E17 CLKR0 124 107 B14 EMU0 112 95 A19 CLKX0 125 108 A13 EMU1 80 63 W19 D0 126 109 B12 EMU2 79 62 V16 D1 123 106 A15 EMU3 78 61 W17 D2 110 93 D18 FSR0 77 60 U13 D3 114 97 B18 FSX0 76 59 V14 D4 81 73 P18 HOLD 75 58 W15 D5 82 72 R19 HOLDA 73 56 U11 D6 90 64 V18 H1 72 55 V12 D7 89 65 U17 H3 68 51 W11 D8 99 82 H18 IACK 67 50 V10 D9 100 83 J17 INT0 † CV SS , VSSL , and IVSS are on the same plane. ‡ AV DD , DVDD , CVDD , and PVDD are on the same plane. § VSUBS connects to die metallization. Tie this pin to clean ground.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Assignments (Continued) PIN PIN NUMBER NUMBER PQ PKG HFG PKG GFA PKG NAME PQ PKG HFG PKG GFA PKG NAME 103 86 E19 INT1 30 18 P4 VSSL † 106 89 F18 INT2 35 19 T10 VSSL † 107 90 G17 INT3 36 20 K4 DV SS 127 110 C11 MCBL/MP 37 25 T4 IVSS † 92 77 L19 R/W 42 34 G3 DV SS 95 75 N17 RDY 51 40 K16 CV SS † 94 78 K18 RESET 57 44 T8 IVSS † 118 101 A17 SHZ 61 52 T12 DV SS 93 76 M18 STRB 69 53 R11 VSSL † 120 103 B16 TCLK0 70 54 J15 VSSL †
105 C15 TCLK1 71 67 W13 DV SS
121 G5 AV DD ‡ 84 68 D10 CV SS †
6 130 E7 AV DD ‡ 85 69 D16 IVSS † 15 7 E5 AV DD ‡ 86 84 T16 DV SS 24 15 N5 VDDL 101 85 D12 VSSL † 32 16 R5 VDDL 102 92 F16 CV SS † 33 23 H4 DV DD ‡ 109 96 H16 IVSS † 40 32 J5 DV DD ‡ 113 100 D14 VSUBS § 49 42 T14 DV DD ‡ 117 102 U15 DV SS 59 48 R7 VDDL 119 111 C13 CV SS † 65 49 R9 VDDL 128 71 T18 X1 66 57 R13 DV DD ‡ 88 70 U19 X2/CLKIN 74 66 R15 DV DD ‡ 87 79 J19 XF0 83 74 P16 CV DD ‡ 96 81 G19 XF1 91 80 N15 CV DD ‡ 98 F6 No Connect 97 87 G15 VDDL D4 DV SS 104 88 E15 VDDL N19 DV SS 105 98 L15 PV DD ‡ R17 DV SS 115 104 E9 PV DD ‡ L17 DV SS 121 114 E13 VDDL M16 DV SS 131 115 E11 VDDL D6 DV SS 132 118 L5 VSSL † A5 DV SS 3 119 H2 DV SS D8 DV SS 4 132 M4 CV SS † 17 2 F4 DV SS 19 13 T6 CV SS † † CV SS , VSSL , and IVSS are on the same plane. ‡ AV DD , DVDD , CVDD , and PVDD are on the same plane. § VSUBS connects to die metallization. Tie this pin to clean ground.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions TERMINAL TYPE † DESCRIPTION CONDITIONS WHEN NAME QTY TYPE † DESCRIPTION WHEN SIGNAL IS Z TYPE‡ PRIMARY-BUS INTERFACE D31−D0 32 I/O/Z 32-bit data port S H R A23−A0 24 O/Z 24-bit address port S H R R/W 1 O/Z Read/write. R/W is high when a read is performed and low when a write is performed over the parallel interface. S H R STRB 1 O/Z External-access strobe S H RDY 1 I Ready. RDY indicates that the external device is prepared for a transaction completion. HOLD 1 I Hold. When HOLD is a logic low, any ongoing transaction is completed. A23−A0, D31−D0, STRB , and R/W are placed in the high-impedance state and all transac- tions over the primary-bus interface are held until HOLD becomes a logic high or until the NOHOLD bit of the primary-bus-control register is set. HOLDA 1 O/Z Hold acknowledge. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23−A0, D31−D0, STRB, and R/W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic high of HOLD or the NOHOLD bit of the primary-bus-control register is set. S CONTROL SIGNALS RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. INT3−INT0 4 I External interrupts IACK 1 O/Z Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used to indicate the beginning or the end of an interrupt-service routine.S MCBL/MP 1 I Microcomputer boot-loader/microprocessor mode-select SHZ 1 I Shutdown high impedance. When active, SHZ shuts down the device and places all pins in the high-impedance state. SHZ is used for board-level testing to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support interlocked processor instruction. S R SERIAL PORT 0 SIGNALS CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.S R CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. S R DR0 1 I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive process using DR0. S R FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit process using DX0. S R TIMER SIGNALS TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. S TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. S † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued) TERMINAL TYPE † DESCRIPTION CONDITIONS WHEN NAME QTY TYPE † DESCRIPTION WHEN SIGNAL IS Z TYPE‡ SUPPLY AND OSCILLATOR SIGNALS H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S VDD 20 I 5-V supply for ’C31 devices and 3.3-V supply for ’LC31 devices. All must be connected to a common supply plane.§ VSS 25 I Ground. All grounds must be connected to a common ground plane. X1 1 O Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left unconnected. X2/CLKIN 1 I Internal-oscillator input from a crystal or a clock RESERVED ¶ EMU2−EMU0 3 I Reserved for emulation. Use pullup resistors to VDD EMU3 1 O/Z Reserved for emulation S † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling capacitor value is 0.1 µF. ¶ Follow the connections specified for the reserved pins. Use 18-kΩ−22-kΩ pullup resistors for best results. All VDD supply pins must be connected to a common supply plane, and all ground pins must be connected to a common ground plane.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉ ÉÉÉ Boot Loader Cache (64 × 32) RAM Block 0 (1K × 32) RAM Block 1 (1K × 32) RDY HOLD HOLDA STRB R/W D31− D0 A23 − A0 RESET IR PC CPU1 REG1 REG2 MUX BKARAU0 ARAU1 DISP0, IR0, IR1 Extended- Precision Registers (R7−R0) Auxiliary Registers (AR0 − AR7) Other Registers (12) Multiplier 32-Bit Barrel Shifter ALU DMA Controller Global-Control Register Source-Address Register Destination- Address Register Serial Port 0 Serial-Port-Control Register Receive/Transmit (R / X) Timer Register Data-Transmit Register Data-Receive Register FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Timer 0 Global-Control Register Timer-Period Register Timer-Counter Register TCLK0 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register TCLK1 Port Control STRB -Control Register Transfer- Counter Register PDATA Bus PADDR Bus DDATA Bus DADDR1 Bus DADDR2 Bus DMADATA Bus DMAADDR Bus 32 32 24 24 32 INT(3 − 0) IACK MCBL / MP XF(1,0) VDD (19 − 0) VSS (24 − 0) X2 / CLKIN EMU(3 − 0) 32 24 24 24 2432 32 32 CPU2 32 32 40 40 MUX Controller Peripheral Data Bus Peripheral Address Bus CPU1 REG1 REG2 MUX
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 1. SMJ320C31 Memory Map
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 3. Peripheral Bus Memory-Mapped Registers†
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over specified temperature range (unless otherwise noted)† ’C31 ’LC31 (for SMJ320C31-33) (for SMJ320LC31-33) † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS . 2. Actual operating power is less. This value was obtained under specially produced worst-case test conditions for the TMS320C31-33 and the TMS320LC31-33, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary and extension buses at the maximum rate possible. See normal (ICC ) current specification in the electrical characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020). recommended operating conditions (see Note 3) ’C31 ’LC31 UNITMIN NOM MAX MIN NOM MAX UNIT VSS Supply voltage (CVSS , etc.) 0 0 V VIH High-level input voltage (except RESET) 2.1 VDD + 0.3* 1.8 VDD + 0.3* V VIH High-level input voltage (RESET) 2.2 VDD + 0.3* 2.2 VDD + 0.3* V VIL Low-level input voltage − 0.3* 0.8 − 0.3* 0.6 V IOH High-level output current − 300 − 300 µA IOL Low-level output current 2 2 mA TC Operating case temperature ’320C31-40 ’320C31-50 ’320C31-60 ’320LC31-40 −55 −55 −55 125 125 105 −55 125 VTH High-level input voltage for CLKIN 3.0 VDD + 0.3* 2.5 VDD + 0.3* V * This parameter is not production tested. NOTE 3: All voltage values are with respect to VSS . All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS clock.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted) (see Note 3)† PARAMETER TEST CONDITIONS ’C31 ’LC31 UNITPARAMETER TEST CONDITIONS MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VOH High-level output voltageVDD = MIN, IOH = MAX 2.4 3 2 V VOL Low-level output voltageVDD = MIN, IOH = MAX 0.3 0.6 0.4 V IZ High-impedance current VDD = MAX − 20 + 20 − 20 + 20 µA II Input current VI = VSS to VDD − 10 + 10 − 10 + 10 µA IIP Input current (with internal pullup) Inputs with internal pullups§ − 600 20 − 600 10 µA ICC Supply current¶# TA = 25°C, fx = 40 MHz ’C31-40 ’LC31-40 160 400 150 300 mAICC Supply current¶# TA = 25°C, VDD = MAX fx = 50 MHz ’C31-50 200 425 mAVDD = MAX fx = 60 MHz ’C31-60 225 475 IDD Supply current Standby, IDLE2 Clocks shut off 50 20 µA C i Input All inputs except CLKIN 15* 15* pFC i Input capacitance CLKIN 25 25 pF C o Output capacitance 20* 20* pF † All input and output voltage levels are TTL compatible. ‡ For ’C31, all typical values are at VDD = 5 V, TA = 25°C. For ’LC31, all typical values are at VDD = 3.3 V, TA = 25°C. § Pins with internal pullup devices: INT3−INT0, MCBL/MP . ¶ Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary and expansion buses at the maximum rate possible. See Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020). # fx is the input clock frequency. * This parameter is not production tested. NOTE 3: All voltage values are with respect to VSS . All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS clock.
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 7. SMJ320LC31 Test Load Circuit is 2 V and the level at which the output is said to be low is 1 V. which the output is said to be high is 2 V. Figure 8. ’LC31 Output Levels 1.8 V and the level at which the input is said to be low is 0.6 V. 0.6 V and the level at which the input is said to be high is 1.8 V. Figure 9. ’LC31 Input Levels
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows, unless otherwise noted: A A23−A0 H H1 and H3 ASYNCH Asynchronous reset signals HOLD HOLD C CLKX0 HOLDA HOLDA CI CLKIN IACK IACK CLKR CLKR0 INT INT3 −INT0 CONTROL Control signals RDY RDY D D31−D0 RW R/W DR DR RESET RESET DX DX S STRB FS FSX/R SCK CLKX/R FSX FSX0 SHZ SHZ FSR FSR0 TCLK TCLK0, TCLK1, or TCLKx GPI General-purpose input XF XF0, XF1, or XFx GPIO General-purpose input/output; peripheral pin XFIO XFx switching from input to output GPO General-purpose output
18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Timing specifications apply to the SMJ320C31 and SMJ320LC31. The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals.
- This parameter is not production tested.
Figure 10. Timing for X2/CLKIN
Figure 11. Timing for H1 and H3
4.5 V Band
5.5 V Band
Figure 12. SMJ320C31 CLKIN to H1/H3 as a Function of Temperature
20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
2.5 V Band
3.8 V Band
Figure 13. SMJ320LC31 CLKIN to H1/H3 as a Function of Temperature
The following table defines memory read/write timing parameters for STRB. † See Figure 16 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).
- This parameter is not production tested.
NOTE A: STRB remains low during back-to-back read operations. Figure 14. Timing for Memory (STRB = 0) Read
22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 15. Timing for Memory (STRB = 0) Write Figure 16. Address-Bus Timing Variation With Load Capacitance (see Note A)
The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII. Figure 17. Timing for XF0 and XF1 When Executing LDFI or LDII
24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. from executing, the address of the store will not be driven until the store can execute. Figure 18. Timing for XF0 When Executing an STFI or STII
The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI. Figure 19. Timing for XF0 and XF1 When Executing SIGI
26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register. Figure 20. Timing for Loading XF Register When Configured as an Output Pin
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.
- This parameter is not production tested.
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register. Figure 21. Timing for Change of XFx From Output to Input Mode
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin. NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register. Figure 22. Timing for Change of XFx From Input to Output Mode The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1. and therefore results in slow external accesses until these registers are initialized. is an asynchronous input and can be asserted during reset.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 RESET timing (see Figure 23) NO. ’C31-40 ’LC31-40 ’C31-50 ’C31-60 UNITNO. MIN MAX MIN MAX MIN MAX MIN MAX UNIT 38 tsu(RESET-CIL) Setup time, RESET before 39 td(CLKINH-H1H) Delay time, CLKIN high to H1 high (see Note 4) 2 14 2 14 2 10 2 10 ns 40 td(CLKINH-H1L) Delay time, CLKIN high to H1 low (see Note 4) 2 14 2 14 2 10 2 10 ns 41 tsu(RESETH-H1L) Setup time, RESET high before H1 low and after ten H1 clock cycles 9 9 7 6 ns 42 td(CLKINH-H3L) Delay time, CLKIN high to H3 low (see Note 4) 2 14 2 14 2 10 2 10 ns 43 td(CLKINH-H3H) Delay time, CLKIN high to H3 high (see Note 4) 2 14 2 14 2 10 2 10 ns 44 tdis(H1H-DZ) Disable time, H1 high to D (high impedance) 15* 13* 12* 11* ns 45 tdis(H3H-AZ) Disable time, H3 high to A (high impedance) 9* 9* 8* 7* ns 46 td(H3H-CONTROLH) Delay time, H3 high to control signals high 9* 9* 8* 7* ns 47 td(H1H-RWH) Delay time, H1 high to R/W high 9* 9* 8* 7* ns 48 td(H1H-IACKH) Delay time, H1 high to IACK high 9* 9* 8* 7* ns 49 tdis(RESETL-ASYNCH) Disable time, RESET low to asynchronous reset signals disabled (high impedance) 21* 21* 17* 14* ns † P = tc(CI) * This parameter is not production tested. NOTE 4: See Figure 12 and Figure 13 for typical temperature dependence.
30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
NOTES: A. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1. sequence shown occurs; otherwise, an additional delay of one clock cycle is possible. reset vector is fetched twice, with no software wait states. D. Control signals include STRB. 18−22 kΩ, if undesirable spurious writes are caused when these outputs go low. Figure 23. Timing for RESET
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 interrupt response timing The following table defines the timing parameters for the INT signals. timing for INT3−INT0 response (see Figure 24) NO. ’C31-40 ’LC31-40 ’C31-50 ’C31-60 UNITNO. MIN MAX MIN MAX MIN MAX MIN MAX UNIT 50 tsu(INT-H1L) Setup time, INT3−INT0 before H1 low 13 15 11 8 ns 51 tw(INT) Pulse duration, interrupt to ensure only one interrupt P 2P†* P 2P†* P 2P†* P 2P†* ns † P = tc(H) * This parameter is not production tested. The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The SMJ320C3x interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1. Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA respond to detected interrupts on instruction-fetch boundaries only. For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held to: /C0068A minimum of one H1 falling edge /C0068No more than two H1 falling edges The SMJ320C3x can accept an interrupt from the same source every two H1 clock cycles. If the specified timings are met, the exact sequence shown in Figure 24 occurs; otherwise, an additional delay of one clock cycle is possible.
32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 24. Timing for INT3−INT0 Response
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction. phase of the IACK instruction is extended. Figure 25. Timing for IACK
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
serial-port timing for SMJ320C31-40 and SMJ320LC31-40 (see Figure 26 and Figure 27) NO. ’C31-40 ’LC31-40 UNITNO. MIN MAX UNIT 54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 13 ns 55 tc(SCK) Cycle time, CLKX/R CLKX/R ext tc(H)x2.6 ns55 tc(SCK) Cycle time, CLKX/R CLKX/R int tc(H)x2 tc(H)x232 ns 56 tw(SCK) Pulse duration, CLKX/R high/low CLKX/R ext tc(H)+10 ns56 tw(SCK) Pulse duration, CLKX/R high/low CLKX/R int [tc(SCK)/2]−5 [tc(SCK)/2]+5 ns 57 tr(SCK) Rise time, CLKX/R 7 ns 58 tf(SCK) Fall time, CLKX/R 7 ns 59 td(C-DX) Delay time, CLKX to DX valid CLKX ext 30 ns59 td(C-DX) Delay time, CLKX to DX valid CLKX int 17 ns 60 tsu(DR-CLKRL) Setup time, DR before CLKR low CLKR ext 9 ns60 tsu(DR-CLKRL) Setup time, DR before CLKR low CLKR int 21 ns 61 th(CLKRL-DR) Hold time, DR from CLKR low CLKR ext 9 ns61 th(CLKRL-DR) Hold time, DR from CLKR low CLKR int 0 ns 62 td(C-FSX) Delay time, CLKX to internal FSX high/low CLKX ext 27 ns62 td(C-FSX) Delay time, CLKX to internal FSX high/lowCLKX int 15 ns 63 tsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR ext 9 ns63 tsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR int 9 ns 64 th(SCKL-FS) Hold time, FSX/R input from CLKX/R low CLKX/R ext 9 ns64 th(SCKL-FS) Hold time, FSX/R input from CLKX/R lowCLKX/R int 0 ns 65 tsu(FSX-C) Setup time, external FSX before CLKX CLKX ext −[tc(H)−8]* [tc(SCK)/2]−10* ns65 tsu(FSX-C) Setup time, external FSX before CLKX CLKX int [tc(H)−21]* tc(SCK)/2* ns 66 td(CH-DX)V Delay time, CLKX to first DX bit, FSX CLKX ext 30* ns66 td(CH-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high CLKX int 18* ns 67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 30* ns 68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data bit 17* ns * This parameter is not production tested.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 35POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 serial-port timing for SMJ320C31-50 (see Figure 26 and Figure 27) NO. ’C31-50 UNITNO. MIN MAX UNIT 54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 10 ns 55 tc(SCK) Cycle time, CLKX/R CLKX/R ext tc(H)x2.6 ns55 tc(SCK) Cycle time, CLKX/R CLKX/R int tc(H)x2 tc(H)x232 ns 56 tw(SCK) Pulse duration, CLKX/R high/low CLKX/R ext tc(H)+10 ns56 tw(SCK) Pulse duration, CLKX/R high/low CLKX/R int [tc(SCK)/2]−5 [tc(SCK)/2]+5 ns 57 tr(SCK) Rise time, CLKX/R 6 ns 58 tf(SCK) Fall time, CLKX/R 6 ns 59 td(C-DX) Delay time, CLKX to DX valid CLKX ext 24 ns59 td(C-DX) Delay time, CLKX to DX valid CLKX int 16 ns 60 tsu(DR-CLKRL) Setup time, DR before CLKR low CLKR ext 9 ns60 tsu(DR-CLKRL) Setup time, DR before CLKR low CLKR int 17 ns 61 th(CLKRL-DR) Hold time, DR from CLKR low CLKR ext 7 ns61 th(CLKRL-DR) Hold time, DR from CLKR low CLKR int 0 ns 62 td(C-FSX) Delay time, CLKX to internal FSX high/low CLKX ext 22 ns62 td(C-FSX) Delay time, CLKX to internal FSX high/lowCLKX int 15 ns 63 tsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR ext 7 ns63 tsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR int 7 ns 64 th(SCKL-FS) Hold time, FSX/R input from CLKX/R low CLKX/R ext 7 ns64 th(SCKL-FS) Hold time, FSX/R input from CLKX/R low CLKX/R int 0 ns 65 tsu(FSX-C) Setup time, external FSX before CLKX CLKX ext −[tc(H)−8]* [tc(SCK)/2]−10* ns65 tsu(FSX-C) Setup time, external FSX before CLKX CLKX int −[tc(H)−21]* tc(SCK)/2* ns 66 td(CH-DX)V Delay time, CLKX to first DX bit, FSX CLKX ext 24* ns66 td(CH-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high CLKX int 14* ns 67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 24* ns 68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data bit 14* ns * This parameter is not production tested.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
serial-port timing for SMJ320C31-60 (see Figure 26 and Figure 27) NO. ’C31-60 UNITNO. MIN MAX UNIT 54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 8 ns 55 tc(SCK) Cycle time, CLKX/R CLKX/R ext tc(H)x2.6 ns55 tc(SCK) Cycle time, CLKX/R CLKX/R int tc(H)x2 tc(H)x232 ns 56 tw(SCK) Pulse duration, CLKX/R high/low CLKX/R ext tc(H)+10 ns56 tw(SCK) Pulse duration, CLKX/R high/low CLKX/R int [tc(SCK)/2]−5 [tc(SCK)/2]+5 ns 57 tr(SCK) Rise time, CLKX/R 5 ns 58 tf(SCK) Fall time, CLKX/R 5 ns 59 td(C-DX) Delay time, CLKX to DX valid CLKX ext 20 ns59 td(C-DX) Delay time, CLKX to DX valid CLKX int 15 ns 60 tsu(DR-CLKRL) Setup time, DR before CLKR low CLKR ext 8 ns60 tsu(DR-CLKRL) Setup time, DR before CLKR low CLKR int 15 ns 61 th(CLKRL-DR) Hold time, DR from CLKR low CLKR ext 6 ns61 th(CLKRL-DR) Hold time, DR from CLKR low CLKR int 0 ns 62 td(C-FSX) Delay time, CLKX to internal FSX high/low CLKX ext 20 ns62 td(C-FSX) Delay time, CLKX to internal FSX high/lowCLKX int 14 ns 63 tsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR ext 6 ns63 tsu(FSR-CLKRL) Setup time, FSR before CLKR low CLKR int 6 ns 64 th(SCKL-FS) Hold time, FSX/R input from CLKX/R low CLKX/R ext 6 ns64 th(SCKL-FS) Hold time, FSX/R input from CLKX/R low CLKX/R int 0 ns 65 tsu(FSX-C) Setup time, external FSX before CLKX CLKX ext −[tc(H)−8]* [tc(SCK)/2]−10* ns65 tsu(FSX-C) Setup time, external FSX before CLKX CLKX int −[tc(H)−21]* tc(SCK)/2* ns 66 td(CH-DX)V Delay time, CLKX to first DX bit, FSX CLKX ext 20* ns66 td(CH-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high CLKX int 12* ns 67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 20* ns 68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data bit 12* ns * This parameter is not production tested.
TMS320C3x User’s Guide (literature number SPRU031). NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 26. Timing for Fixed Data-Rate Mode
38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 27. Timing for Variable Data-Rate Mode
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 39POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HOLD timing HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is possible. The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents future hold cycles. Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus allowing the processor to continue until a second write is encountered. timing for HOLD/HOLDA (see Figure 28) NO. ’C31-40 ’LC31-40 ’C31-50 ’C31-60 UNITNO. MIN MAX MIN MAX MIN MAX MIN MAX UNIT 69 tsu(HOLD-H1L) Setup time, HOLD before H1 low 13 13 10 8 ns 70 tv(H1L-HOLDA) Valid time, HOLDA after H1 low 0† 9 0* 9 0* 7 0* 6 ns 71 tw(HOLD) † Pulse duration, HOLD low 2tc(H) 2tc(H) 2tc(H) 2tc(H) ns 72 tw(HOLDA) Pulse duration, HOLDA low tcH−5* tcH−5* tcH−5* tcH−5* ns 73 td(H1L-SH)H Delay time, H1 low to STRB high for a HOLD 0* 9 0* 9 0* 7 0* 6 ns 74 tdis(H1L-S) Disable time, H1 low to STRB to the high-impedance state 75 ten(H1L-S) Enable time, H1 low to STRB enabled (active) 0* 9 0* 9 0* 7 0* 6 ns 76 tdis(H1L-RW) Disable time, H1 low to R/W to the high-impedance state 0* 9* 0* 9* 0* 8* 0* 7* ns 77 ten(H1L-RW) Enable time, H1 low to R/W enabled (active) 0* 9 0* 9 0* 7 0* 6 ns 78 tdis(H1L-A) Disable time, H1 low to address to the high-impedance state 79 ten(H1L-A) Enable time, H1 low to address enabled (valid) 0* 13 0* 13 0* 10 0* 11? ns 80 tdis(H1H-D) Disable time, H1 high to data to the high-impedance state † HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay of one clock cycle is possible. * This parameter is not production tested.
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 28. Timing for HOLD/HOLDA
control registers associated with each peripheral define the modes for these pins. of internal-control registers associated with each peripheral. NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. Figure 29. Timing for Peripheral Pin General-Purpose I/O
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
pin to a general-purpose input pin and vice versa. of internal-control registers associated with each peripheral. NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. Figure 30. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following tables define the timing requirements for the timer pin.
- This parameter is not production tested.
Figure 32. Timing for Timer Pin
The following table defines the timing parameter for the SHZ pin.
- This parameter is not production tested.
NOTE A: Enabling SHZ destroys SMJ320C3x register and memory contents. Figure 33. Timing for SHZ
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
FREQUENCY PACKAGE TYPE PROCESSING LEVEL 5962-9205803MXA 0.6-µm CMOS 5 V ± 5% 40 MHz Ceramic 141-pin staggered PGA DSCC SMD SMJ320C31GFAM40 0.6-µm CMOS 5 V ± 5% 40 MHz Ceramic 141-pin staggered PGA QML SM320C31GFAM40 0.6-µm CMOS 5 V ± 5% 40 MHz Ceramic 141-pin staggered PGA Std 5962-9205803MYA 0.6-µm CMOS 5 V ± 5% 40 MHz Ceramic 132-pin quad flatpack with nonconductive tie bar. DSCC SMD SMJ320C31HFGM40 0.6-µm CMOS 5 V ± 5% 40 MHz Ceramic 132-lead quad flatpack with a nonconductive tie bar QML SM320C31HFGM40 0.6-µm CMOS 5 V ± 5% 40 MHz Ceramic 132-lead quad flatpack with a nonconductive tie bar Std 5962-9205803Q9A 0.72-µm CMOS 5 V ± 5% 40 MHz C31−40 KGD (known good die) DSCC SMD SMJ320C31KGDM40B 0.72-µm CMOS 5 V ± 5% 40 MHz C31−40 KGD (known good die) QML 5962-9205804MXA 0.6-µm CMOS 5 V ± 5% 50 MHz Ceramic 141-pin staggered PGA DSCC SMD SMJ320C31GFAM50 0.6-µm CMOS 5 V ± 5% 50 MHz Ceramic 141-pin staggered PGA QML SM320C31GFAM50 0.6-µm CMOS 5 V ± 5% 50 MHz Ceramic 141-pin staggered PGA Std 5962-9205804MYA 0.6-µm CMOS 5 V ± 5% 50 MHz Ceramic 132-pin quad flatpack with nonconductive tie bar. DSCC SMD SMJ320C31HFGM50 0.6-µm CMOS 5 V ± 5% 50 MHz Ceramic 132-lead quad flatpack with nonconductive tie bar QML SM320C31HFGM50 0.6-µm CMOS 5 V ± 5% 50 MHz Ceramic 132-lead quad flatpack with nonconductive tie bar Std 5962-9205805QXA 0.6-µm CMOS 5 V ± 5% 60 MHz Ceramic 141-pin staggered PGA DSCC SMD SMJ320C31GFAS60 0.6-µm CMOS 5 V ± 5% 60 MHz Ceramic 141-pin staggered PGA QML SM320C31GFAS60 0.6-µm CMOS 5 V ± 5% 60 MHz Ceramic 141-pin staggered PGA Std 5962-9205805QYA 0.6-µm CMOS 5 V ± 5% 60 MHz Ceramic 132-pin quad flatpack with nonconductive tie bar. DSCC SMD SMJ320C31HFGS60 0.6-µm CMOS 5 V ± 5% 60 MHz Ceramic 132-lead quad flatpack with nonconductive tie bar QML SM320C31HFGS60 0.6-µm CMOS 5 V ± 5% 60 MHz Ceramic 132-lead quad flatpack with nonconductive tie bar Std 5962-9760601NXB 0.72-µm CMOS 3.3 V ± 5% 40 MHz Plastic 132-lead good flatpack DSCC SMD SMQ320LC31PQM40 0.72-µm CMOS 3.3 V ± 5% 40 MHz Plastic 132-lead good flatpack QML 5962-9760601Q9A 0.72-µm CMOS 3.3 V ± 5% 40 MHz LC31−40 KGD (known good die) DSCC SMD SMJ320LC31KGDM40B 0.72-µm CMOS 3.3 V ± 5% 40 MHz LC31−40 KGD (known good die) QML
Figure 34. Device Nomenclature
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
GFA (S-CPGA-P141) CERAMIC PIN GRID ARRAY PACKAGE 0.900 (22,86) TYP W V T U P N R K L H G J D E B A C F M 0.100 (2,54) TYP 0.050 (1,27) TYP 1513 108 0.034 (0,86) TYP 0.120 (3,05) 0.140 (3,56) 4040133/D 04/96 DIA TYP 0.022 (0,56) 0.016 (0,41) 0.048 (1,22) DIA TYP
4 Places
0.006 (0,15) 0.105 (2,67) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-128 4.3 PARAMETER Thermal Resistance Characteristics °C/W 39.0R θJC R θJA
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 49POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA HFG (S-CQFP-F132) CERAMIC QUAD FLATPACK WITH TIE-BAR “C” “B” 0.960 (24,38) 132 1.210 (30,73) 0.800 (20,32) TYP SQ 100 TYP ”A” 2.025 (51,44) MAX 0.059 (1,50) 0.061 (1,55)DIA TYP TYP SQ0.945 (24,00) 1.990 (50,55) 2.015 (51,18) 0.014 (0,36) 0.002 (0,05) 4040231-8/F 04/96 0.020 (0,51) MAX 0.040 (1,02) 0.030 (0,76) DETAIL “B” Braze 0.006 (0,15) 0.013 (0,33)132 /C0002 DETAIL “A” 0.010 (0,25) 0.005 (0,12) DETAIL “C” 0.175 (4,45) 0.225 (5,72)Tie Bar Width NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier. D. This package can be hermetically sealed with a metal lid. E. The terminals will be gold plated. 44.3 PARAMETER Thermal Resistance Characteristics† °C/W 2.1R θJC R θJA † Falls within MIL-STD-1835 CMGA7-PN and CMGA19-PN and JEDEC MO-067AG and MO-066AG, respectively
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK
100 LEAD SHOWN
0.012 (0,30) 0.008 (0,20) 0.025 (0,635) Seating Plane 132 1.090 (27,69) 1.070 (27,18) 0.966 (24,54) 0.934 (23,72) 1.112 (28,25) 1.088 (27,64) 0.800 (20,32) 4040045/C 11/95 100113 6339 ”D2” SQ ”D1” SQ ”D” SQ ”D3” SQ DIM ”D” ”D2” ”D3” ”D1” NOM MIN MAX MIN MAX MIN MAX LEADS *** 0.180 (4,57) MAX 100 0.890 (22,61) 0.870 (22,10) 0.766 (19,46) 0.734 (18,64) 0.912 (23,16) 0.888 (22,56) 0.600 (15,24) 0.004 (0,10) M0.006 (0,15) 0.010 (0,25) 0.020 (0,51) MIN 0.130 (3,30) 0.150 (3,81) 0.006 (0,16) NOM Gage Plane 0.036 (0,91) 0.046 (1,17) 0°−/C0257 8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-069
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006 51POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA TA (35 OR 70 mm WITH PROTECTIVE FILM) SMJ320C31 244-PIN TAB FRAME (PG6) SOCKET,
132 OLB/ILB 0,30-mm PITCH
2,25 (4 Places) 14,00 (2 Places) Tab Leads Up 0,31 0,29 × 32 = 9,62 9,58 0,31 0,29 × 32 = 9,62 9,58 0,31 0,29 9,62 9,5832 =× 0,31 0,29 9,62 9,5832 =× NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. The OLB lead width is 0,120 ± 0,03 mm. D. The ILB lead width is 0,0832 ± 0,015 mm. E. The tape width is 35 mm. F. The TA is encapsulated die with polyimide overcoat.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0051/C0049/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0076/C0067/C0051/C0049/C0044 /C0083/C0077/C0081/C0051/C0050/C0048/C0076/C0067/C0051/C0049 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082/C0083 SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TB (35 OR 70 mm WITHOUT PROTECTIVE FILM) SMJ320C31 244-PIN TAB FRAME (PG6) SOCKET, 2,25 (4 Places) 14,00 (2 Places) Tab Leads Up 0,31 0,29 × 32 = 9,62 9,58 0,31 0,29 × 32 = 9,62 9,58 0,31 0,29 9,62 9,5832 =× 0,31 0,29 9,62 9,5832 =× NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. The OLB lead width is 0,120 ± 0,03 mm. D. The ILB lead width is 0,0832 ± 0,015 mm. E. The tape width is 35 mm. F. The TB is bare die.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9205803MXA ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type 5962-9205803MXC ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type 5962-9205803MYA ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type 5962-9205804MXA ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type 5962-9205804MXC ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type 5962-9205804MYA ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type 5962-9205805QXA ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type 5962-9205805QYA ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type 5962-9760601NXB ACTIVE BQFP PQ 132 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR 5962-9760601Q9A OBSOLETE XCEPT KGD 0 TBD Call TI Call TI SM320C31GFAM50 ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type SM320C31GFAS60 ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type SM320C31HFGM40 ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type SM320C31HFGM50 ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type SM320C31HFGS60 ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type SMJ320C31GFAM40 ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type SMJ320C31GFAM50 ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type SMJ320C31GFAS60 ACTIVE CPGA GFA 141 1 TBD Call TI N / A for Pkg Type SMJ320C31HFGM40 ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type SMJ320C31HFGM50 ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type SMJ320C31HFGS60 ACTIVE CFP HFG 132 1 TBD Call TI N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on PACKAGE OPTION ADDENDUM www.ti.com 21-May-2007 Addendum-Page 1
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 21-May-2007 Addendum-Page 2
MBQF001A – NOVEMBER 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK 0.012 (0,30) 0.008 (0,20) 0.025 (0,635) Seating Plane 132 1.090 (27,69) 1.070 (27,18) 0.966 (24,54) 0.934 (23,72) 1.112 (28,25) 1.088 (27,64) 0.800 (20,32) 4040045/C 11/95 100113 6339 ”D2” SQ ”D1” SQ ”D” SQ ”D3” SQ DIM ”D” ”D2” ”D3” ”D1” NOM MIN MAX MIN MAX MIN MAX LEADS *** 0.180 (4,57) MAX 100 0.890 (22,61) 0.870 (22,10) 0.766 (19,46) 0.734 (18,64) 0.912 (23,16) 0.888 (22,56) 0.600 (15,24) 0.004 (0,10) M0.006 (0,15) 0.010 (0,25) 0.020 (0,51) MIN 0.130 (3,30) 0.150 (3,81) 0.006 (0,16) NOM Gage Plane 0.036 (0,91) 0.046 (1,17) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-069
MCPG015B – FEBRUARY 1996 – REVISED DECEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GFA (S-CPGA-P141) CERAMIC PIN GRID ARRAY 0.900 (22,86) TYP W V T U P N R K L H G J D E B A C F M 0.100 (2,54) TYP 0.050 (1,27) TYP 1513 108 0.034 (0,86) TYP 0.120 (3,05) 0.140 (3,56) 4040133/E 11/01 DIA TYP 0.022 (0,56) 0.016 (0,41) 0.048 (1,22) DIA TYP 0.006 (0,15) 0.105 (2,67) A1 Corner Bottom View NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark can appear on top or bottom, depending on package vendor. D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edge of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold-plated or solder-dipped. G. Falls within JEDEC MO-128AB
(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for
applications
design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power www.ti.com/lpw Video Imaging www.ti.com/video Wireless Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2007, Texas Instruments Incorporated