SMJ320C25GBM TI1 | Alldatasheet
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/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Military Temperature Range – –55°C to 125°C /C0068100-ns or 80-ns Instruction Cycle Times /C0068544 Words of Programmable On-Chip Data RAM /C00684K Words of On-Chip Program ROM /C0068128K Words of Data/Program Space /C006816 Input and 16 Output Channels /C006816-Bit Parallel Interface /C0068Directly Accessible External Data Memory Space – Global Data Memory Interface /C006816-Bit Instruction and Data Words /C006816 × 16-Bit Multiplier With a 32-Bit Product /C006832-Bit ALU and Accumulator /C0068Single-Cycle Multiply/Accumulate Instructions /C00680 to 16-Bit Scaling Shifter /C0068Bit Manipulation and Logical Instructions /C0068Instruction Set Support for Floating-Point Operations, Adaptive Filtering, and Extended-Precision Arithmetic /C0068Block Moves for Data/Program Management /C0068Repeat Instructions for Efficient Use of Program Space /C0068Eight Auxiliary Registers and Dedicated Arithmetic Unit for Indirect Addressing /C0068Serial Port for Direct Code Interface /C0068Synchronization Input for Synchronous Multiprocessor Configurations /C0068Wait States for Communication to Slow-Off-Chip Memories/Peripherals /C0068On-Chip Timer for Control Operations /C0068Three External Maskable User Interrupts /C0068Input Pin Polled by Software Branch Instruction /C00681.6-µm CMOS Technology /C0068Programmable Output Pin for Signaling External Devices /C0068Single 5-V Supply /C0068On-Chip Clock Generator /C0068Packaging: – 68-Pin Leaded Ceramic Chip Carrier (FJ Suffix) – 68-Pin Ceramic Grid Array (GB Suffix) – 68-Pin Leadless Ceramic Chip Carrier (FD Suffix) Copyright 2001, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IACK MSC CLKOUT1 CLKOUT2 XF HOLDA DX FSX X2 CLKIN BR D10 D11 D12 D13 D14 D15 READY CLKR CLKX STRB R/W PS IS DS VSS 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VSS SYNC INT0 INT1 INT2 VCC DR FSR A10 A11 A12 A13 A14 A15 V SS V CC V CC V CC 68-Pin FJ and FD Packages (Top View) /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 123456789 1 0 1 1 A B C D E F G H J K L 68-Pin GB Package (Top View)
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
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description
This data sheet provides design documentation for the SMJ320C25 and the SMJ320C25-50 digital signal processor (DSP) devices in the SMJ320 family of VLSI digital signal processors and peripherals. The SMJ320 family supports a wide range of digital signal processing applications such as tactical communications, guidance, military modems, speech processing, spectrum analysis, audio processing, digital filtering, high-speed control, graphics, and other computation-intensive applications. Differences between the SMJ320C25 and the SMJ320C25-50 are specifically identified, as in the following paragraph and in the parameter tables on pages 18 through 24 of this data sheet. When not specifically differentiated, the term SMJ320C25 is used to describe both devices. The SMJ320C25 has a 100-ns instruction cycle time. The SMJ320C25-50 has an 80-ns instruction cycle time. With these fast instruction cycle times and their innovative memory configurations, these devices perform operations necessary for many real-time digital signal processing algorithms. Since most instructions require only one cycle, the SMJ320C25 is capable of executing 12.5 million instructions per second. On-chip data RAM of 544 16-bit words, on-chip program ROM of 4K words, direct addressing of up to 64K words of external data memory space and 64K words of external program memory space, and multiprocessor interface features for sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the instruction set. Table 1. PGA/CLCC/LCCC Pin Assignments SMJ320 is a trademark of Texas Instruments Incorporated.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Terminal Functions SIGNALS I/O/Z† DEFINITION VCC I 5-V supply pins VSS I Ground pins X1 0 Output from internal oscillator for crystal X2/CLKIN I Input to internal oscillator from crystal or external clock CLKOUT1 0 Master clock output (crystal or CLKIN frequency/4) CLKOUT2 0 A second clock output signal D15 –D0 I/O/Z 16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/0 spaces. A15–A0 O/Z 16-bit address bus A15 (MSB) through A0 (LSB) PS ,DS,IS O/Z Program, data, and I/O space select signals R/W O/Z Read / write signal STRB O/Z Strobe signal RS I Reset input INT2–INT0 I External user interrupt inputs MP/MC I Microprocessor/microcomputer mode select pin MSC 0 Microstate complete signal IACK 0 Interrupt acknowledge signal READY I Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction is complete. BR 0 Bus request signal. Asserted when the SMJ320C25 requires access to an external global data memory space. XF 0 External flag output (latched software-programmable signal) HOLD 1 Hold input. When asserted, SMJ320C25 goes into an idle mode and places the data, address, and control lines in the high-impedance state. HOLDA 0 Hold acknowledge signal SYNC I Synchronization input BIO I Branch control input. Polled by BIOZ instruction DR I Serial data receive input CLKR I Clock for receive input for serial port FSR I Frame synchronization pulse for receive input DX O/Z Serial data transmit output CLKX I Clock for transmit output for serial port FSX I/O/Z Frame synchronization pulse for transmit. Configurable as either an input or an output. † I/O/Z denotes input/output/high-impedance state.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
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Shifters (0-7)† ACCL(16) ACCH(16) ALU(32) Shifter(-6, 0, 1, 4) Shifter(0-16)
7 LSB
TR(16) Multiplier PR(32) DATA/PROG RAM (256 × 16) Block B0 16 16 Data RAM Block B1 (256 × 16) Block B2 (32 × 16) ARB(3) ARP(3) ARAU(16) AR4(16) AR3(16) AR2(16) AR1(16) AR0(16) DP(9) FSX CLKX DX FSR CLKR DRR(16) DXR(16) PRD(16) TIM(16) IMR(6) GREG(8) 16 16 IFR(6) RPTC(8) STO(16) ST1(16) IR(16) 16D15-D0 1616 A15-A0 INT(2-0) MP/MC Instruction (8 x 16) 16 16 16 Stack PC(16) IACK RS BIO MSC HOLDA HOLD XF BR STRB R/W Program Bus Program Bus Program ROM/ EPROM (4096 × 16) QIR(16) 16 16 X2/CLKIN CLKOUT1 CLKOUT2 Controller PFC(16) MCS(16) PS DS IS SYNC MUX MUX MUX MUX MUX MUX MUX DR MUXMUX C READY Address AR5(16) AR6(16) AR7(16) RSR(16) XSR(16) LEGEND: ACCH = Accumulator high IFR = Interrupt flag register PC = Program counter ACCL = Accumulator low IMR = Interrupt mask register PFC = Prefetch counter ALU = Arithmetic logic unit IR = Instruction register RPTC = Repeat instruction counter ARAU = Auxiliary register arithmetic unit MCS = Microcall stack GREG = Global memory allocation register ARB = Auxiliary register pointer buffer QIR = Queue instruction register RSR = Serial port receive shift register ARP = Auxiliary register pointer PR = Product register XSR = Serial port transmit shift register DP = Data memory page pointer PRD = Period register for timer AR0-AR7 = Auxiliary registers DRR = Serial port data receive register TIM = Timer ST0, ST1 = Status registers DXR = Serial port data transmit register TR = Temporary register C = Carry bit
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 architecture The SMJ320C25 increases performance of DSP algorithms through innovative additions to the SMJ320 architecture. Increased throughput on the SMJ320C25 for many DSP applications is accomplished by means of single-cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing. The architectural design of the SMJ320C25 emphasizes overall speed, communication, and flexibility in processor configuration. Control signals and instructions provide floating-point support, block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations. Two large on-chip RAM blocks, configurable either as separate program and data spaces or as two contiguous data blocks, provide increased flexibility in system design. Programs of up to 4K words can be masked into the internal program ROM. The remainder of the 64K-word program memory space is located externally. Large programs can execute at full speed from this memory space. Programs can also be downloaded from slow external memory to high-speed on-chip RAM. A total of 64K data memory address space is included to facilitate implementation of DSP algorithms. The VLSI implementation of the SMJ320C25 incorporates all of these features as well as many others, such as a hardware timer, serial port, and block data transfer capabilities. 32-bit ALU/accumulator The SMJ320C25 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch instructions dependent on the status of the ALU or a single bit in a word. These instruction provide the following capabilities: /C0068Branch to an address specified by the accumulator /C0068Normalize fixed-point numbers contained in the accumulator /C0068Test a specified bit of a word in data memory. One input to the ALU is always provided from the accumulator, and the other input can be provided from the product register (PA) of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator. The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. scaling shifter The SMJ320C25 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction. The LSBs of the output are filled with zeroes, and the MSBs can be either filled with zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1.
16 X 16-bit parallel multiplier
The SMJ320C25 has a 16 x 16-bit hardware multiplier, which is capable of computing a signed or unsigned 32-bit product in a single machine cycle. The multiplier has the following two associated registers: /C0068A 16-bit temporary register (TR) that holds one of the operands for the multiplier, and /C0068A 32-bit product register (PR) that holds the product. Incorporated into the SMJ320C25 instruction set are single-cycle multiply/accumulate instruction that allow both operands to be processed simultaneously. The data for these operations can reside anywhere in internal or external memory and can be transferred to the multiplier each cycle via the program and data buses.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
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16 X 16-bit parallel multiplier (continued)
Four product shift modes are available at the product register (PR) output that are useful when performing multiply/accumulate operations, fractional arithmetic, or justifying fractional products. timer The SMJ320C25 provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM) register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every time the timer decrements to zero. The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts can be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT1. memory control The SMJ320C25 provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks (B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words (block B0) are programmable as either data or program memory. A data memory size of 544 words allows the SMJ320C25 to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed. When using on-chip program RAM, ROM, or high-speed external program memory, the SMJ320C25 runs at full speed without wait states. However, the READY line can be used to interface the SMJ320C25 to slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM speeds processing while cutting system costs. The SMJ320C25 provides three separate address states for program memory, data memory, and I/O. The on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon the memory configuration. The CNF0 (configure block B0 as data memory) and CNFP (configure block B0 as program memory) instruction allow dynamic configuration of the memory maps through software. Regardless of the configuration, the user can still execute from external program memory. The SMJ320C25 has six registers which are mapped into the data memory space: a serial port data receive register, serial port data transmit register, timer register, period register, interrupt mask register, and global memory allocation register.
Figure 1. Memory Maps
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
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interrupts and subroutines The SMJ320C25 has three external maskable user interrupts INT2–INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on two-word boundaries so that branch instruction can be accommodated in those locations if desired. A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction is completed. This mechanism applies both to instructions that are repeated or become multicycle due to the READY signal. external interface The SMJ320C25 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O. thus maximizing system throughout. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices. Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When transitions are made with slower devices, the SMJ320C25 processor waits until the other device completes its function and signals the processor via the READY line. Then, the SMJ320C25 continues execution. A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and other serial systems. The interface signals are compatible with codecs and many other serial devices with a minimum of external hardware. The serial port can also be used for intercommunication between processors in multiprocessing applications. The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register (DRR). Both registers operate in either the byte mode or 16-bit word mode, any can be accessed in the same manner as any other data memory location. Each register has an external clock, a framing synchronization pulse, and associated shift registers. One method of multiprocessing can be implemented by programming one device to transmit while the others are in the receive mode. multiprocessing The flexibility of the SMJ320C25 allows configurations to satisfy a wide range of system requirements. The SMJ320C25 can be used as follows: /C0068A standalone processor /C0068A multiprocessor with devices in parallel /C0068A slave/host multiprocessor with global memory space /C0068A peripheral processor interfaced via processor-controlled signals to another device. For multiprocessing applications, the SMJ320C25 has the capability of allocating global data memory space and communicating with that space via the BR (bus request) and READY control signals. Global memory is data memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit memory-mapped GREG (global memory allocation register) specifies part of the SMJ320C25s data memory as global external memory. The contents of the register determine the size of the global memory space. If the current instruction addresses an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY line. The SMJ320C25 supports DMA (direct memory access) to its external program/data memory using the HOLD and HOLDA signals. Another processor can take complete control of the SMJ320C25s external memory by asserting HOLD low. This causes the SMJ320C25 to place its address, data, and control lines in a high-impedance state, and assert HOLDA. Program execution from on-chip memory can proceed concurrently while the device is in the hold mode.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 instruction set The SMJ320C25 microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal processing operations as well as general-purpose applications, such as multiprocessing and high-speed control. For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary depending upon whether the next data operand fetch is from internal or external program memory. Highest throughput is achieved by maintaining data memory on-chip and using either internal or fast external program memory. addressing modes The SMJ320C25 instruction set provides three memory addressing modes: direct, indirect, and immediate addressing. Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data memory address. Indirect addressing accesses data memory through the eight auxiliary registers. In immediate addressing, the data is based on a portion of the instruction word(s). In direct memory addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus, memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words. Eight auxiliary register (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0–AR7, respectively. There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding or subtracting the contents of AR0, or single indirect addressing with no increment or decrement and bit-reversal addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, followed by anew ARP value being loaded. repeat feature A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded with either a data memory value (RPT instruction) or an immediate value (RPTK instruction) .The value of this operand is one less than the number of times that the next instruction is executed. Those instructions that are normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle instructions. instruction set summary Table 1 lists the symbols and abbreviations used in Table 1, the instruction set summary, Table 2 consists primarily of single-cycle,single-word instructions. Infrequently used branch, I/O, and CALL instructions are multicycle. The instruction set summary is arranged according to function and alphabetized within each functional grouping.
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Table 1. Instruction Symbols
S NO. WORDS D D D K D D S D S S D D S D S S X D DX S D D D D K D MNEMONIC K INSTRUCTION BIT CODE D /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 Table 2. SMJ320C25 Instruction Set Summary † These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
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Table 2. SMJ320C25 Instruction Set Summary (continued) † These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
† These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
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† These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
Table 2. SMJ320C25 Instruction Set Summary (concluded) † These instructions are not included in the TMS320C1x instruction set. ‡ These instructions are not included in the TMS32020 instruction set.
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nearest Texas Instruments Regional Technology Center (RTC). the emulator provides the real-time in-circuit emulation necessary to perform system level debug efficiently. Table 3 gives a complete list of SMJ320C25 software and hardware development tools. Table 3. SMJ/SMJ320C25 Software and Hardware Support
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. † All voltage values are with respect to VSS . recommended operating conditions‡ SMJ320C25-50 SMJ320C25 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.75 5 5.25 4.5 5 5.5 V VSS Supply voltage 0 0 V READY 3.00 2.35 D15 –D0 2.20 2.20 V High le el inp t oltage FSX 2.20 2.30 VVIH High-level input voltageCLKR, CLKX 3.50 3.50 V CLKIN 4.00 3.50 All others 3.00 3.00 D15 –D0, FSX, CLKIN, CLKR, CLKX 0.80 0.80 VIL Low-level input voltage HOLD 0.70 0.70 VVIL Low level in ut voltage All others 0.80 0.70 V IOH High-level output current 300 300 /C0109A IOL Low-level output current 2 2 mA TC Operating case temperature –55 125 –55 125 °C ‡ TC MAX at maximum rated operating conditions at any point on case TC MIN at initial (time zero) power up This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
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The SMJ320C25 can use either its internal oscillator or an external frequency source for a clock. circuit (see the application report, Hardware Interfacing to the TMS320C25). † These values are derived from characterization data and are not tested. Figure 2. Internal Clock Options
unconnected. The external frequency injected must conform to the specifications listed in the following table.
- Rise and fall times, assuming a 40–60% duty cycle, are incorporated within this specification CLKIN rise and fall times must be less
Figure 3. Test Load Circuit
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Figure 4. Voltage Reference Levels † These values are derived from characterization data and not tested.
- A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ”address”
- Delays between CLKOUT1 /CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no
- Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R + tr(C).
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 RS , INT, BIO, and XF timing switching characteristics over recommended operating conditions (see Note 1) PARAMETER SMJ320C25-50 SMJ320C25 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT td(RS) Delay time, CLKOUT1 low to reset state entered 22† 22† ns td(IACK) Delay time, CLKOUT1 to IACK valid –5† 0 7 –8† 0 8 ns td(XF) Delay time, XF valid before falling edge of STRB Q – 10 Q – 12 ns timing requirements over recommended operating conditions (see Note 1) SMJ320C25-50 SMJ320C25 UNITMIN MAX MIN MAX UNIT tsu(IN) Setup time, INT/BIO/RS before CLKOUT1 high 25 32 ns th(IN) Hold time, INT/BIO/RS after CLKOUT1 high 0 0 ns tw(IN) Pulse duration, INT/BIO low tc(C) tc(C) ns tw(RS) Pulse duration, RS low 3tc(C) 3tc(C) ns switching characteristics over recommended operating conditions (see Note 1) PARAMETER SMJ320C25-50 SMJ320C25 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT td(C1L-AL)Delay time, HOLDA low after CLKOUT1 low –1 11 –1 10 ns tdis(AL-A)Disable time, HOLDA low to address three-state 0 0 ns tdis(C1L-A) Disable time, address three-state after CLKOUT1 low (HOLD mode, see Note 7 ) 20† 20† ns td(HH-AH) Delay time, HOLD high to HOLDA high 19 25 ns ten(A-C1L) Enable time, address driven before CLKOUT1 low (HOLD mode, see Note 7 ) 8† 8† ns timing requirements over recommended operating conditions (see Note 1) SMJ320C25-50 SMJ320C25 UNIT MIN MAX MIN MAX UNIT td(C2H-H) Delay time, HOLD valid after CLKOUT2 high Q – 19 Q – 24 ns † These values are derived from characterization data and not tested. NOTES: 1. Q = 1/4tc(C) 6. RS , INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagram occurs. INT/BIO fall time must be less than 8 ns. 7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as ’”address”.
/C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0044 /C0083/C0077/C0074/C0051/C0050/C0048/C0067/C0050/C0053/C0262/C0053/C0048 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0083/C0073/C0071/C0078/C0065/C0076 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
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switching characteristics over recommended operating conditions (see Note 1) PARAMETER SMJ320C25-50 SMJ320C25 UNITPARAMETER MIN MAX MIN MAX UNIT td(CH-DX) Delay time, DX valid after CLKX rising edge (see Note 8) 75 80 ns td(FL-DX) Delay time, DX valid after FSX falling edge (TXM = 0. see Note 8) 40 45 ns td(CH-FS) FSX valid after CLKX rising edge (TXM = 1 ) 40 45 ns timing requirements over recommended operating conditions (see Note 1) SMJ320C25-50 SMJ320C25 UNITMIN MAX MIN MAX UNIT fsx Serial port frequency 1.25 6250 1.25 5000 kHz tc(SCK) Serial port clock (CLKX/CLKR) cycle time 160 800 000 200 800 000 ns tw(SCK1 Serial port clock (CLKX/CLKR) low pulse duration (see Note 9) 64 80 ns tw(SCK) Serial port clock (CLKX/CLKR) high pulse duration (see Note 9) 64 80 ns tsu(FS) FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0) 5 18 ns th(FS) FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0) 10 20 ns tsu(DR) OR setup time before CLKR falling edge 5 10 ns th(DR) OR hold time after CLKR falling edge 10 20 ns NOTES: 1: Q = 1/4tc(C) 8. The last occurrence of FSX falling and CLKX rising. 9. The duty cycle of the serial port clock must be within 40–60% .Serial port clock (CLKX/CLKR) rise and fall times must be less than 25 ns.
1.1 V and a rising edge low voltage of 2.2 V. Figure 5. Clock Timing
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Figure 6. Memory Read Timing
Figure 7. Memory Write Timing
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Figure 8. One Wait-State Memory Access Timing
† Control signals are DS, IS, R/W, and XF. ‡ Serial port controls are DX and FSX. Figure 9. Reset Timing
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Figure 10. Interrupt Timing Figure 11. BIO Timing
Figure 12. External Flag Timing
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otherwise, a delay of one CLKOUT2 cycle occurs. Figure 13. HOLD Timing (part A)
otherwise, a delay of one CLKOUT2 cycle occurs. Figure 14. HOLD Timing (part B)
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Figure 15. Serial Port Receive Timing Figure 16. Serial Port Transmit Timing
www.ti.com 25-Sep-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-8861901XA ACTIVE CPGA GB 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861901XA SMJ320C25GBM 5962-8861901YA ACTIVE LCCC FD 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861901YA SMJ320C25FDM 5962-8861901ZA ACTIVE JLCC FJ 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861901ZA SMJ320C25FJM 5962-8861902XA ACTIVE CPGA GB 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861902XA SMJ320C25-50GB M 5962-8861902ZA ACTIVE JLCC FJ 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861902ZA SMJ320C25-50FJ M SM320C25GBM ACTIVE CPGA GB 68 1 TBD Call TI N / A for Pkg Type -55 to 125 SM320C25GBM SMJ320C25-50FJM ACTIVE JLCC FJ 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861902ZA SMJ320C25-50FJ M SMJ320C25-50GBM ACTIVE CPGA GB 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861902XA SMJ320C25-50GB M SMJ320C25FDM ACTIVE LCCC FD 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861901YA SMJ320C25FDM SMJ320C25FJM ACTIVE JLCC FJ 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861901ZA SMJ320C25FJM SMJ320C25GBM ACTIVE CPGA GB 68 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8861901XA SMJ320C25GBM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
www.ti.com 25-Sep-2013 Addendum-Page 2 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SMJ320C25 :
- Catalog: TMS320C25 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
MCPG023A – OCTOBER 1997 – REVISED DECEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GB (S-CPGA-P68) CERAMIC PIN GRID ARRAY 7893456 J H G F E D B A C 0.800 (20,32) TYP 4040114-14/D 11/01 0.970 (24,63) 0.072 (1,83) 0.088 (2,23) 0.536 (13,61) 0.524 (13,31) 0.950 (24,13)
4 Places
0.050 (1,27) DIA 0.018 (0,46) DIA TYP 0.166 (4,16) 0.194 (4,98) 0.055 (1,39) 0.045 (1,14) 0.100 (2,54) A1 Corner Bottom View NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark may appear on top or bottom depending vendor. D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edges of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold plated or solder dipped. G. Falls within MIL STD 1835 CMGA1-PN, CMGA13-PN and JEDEC MO-067 AA, MO-066 AA respectively
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