SLX-2143 SIRENZA | Alldatasheet
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The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not au thorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved. 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com
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The Sirenza Microdevices’ SLX-2143 is a low noise ampli- fier module operating in the 1700 - 2200 MHz frequency band. This device has been optimized to serve high linear- ity base station applications where a high intercept point is required with low noise figure. The SLX-2143 uses PHEMT device technology, internal bias circuitry, and proven ceramic module technology to yield a high performance product with proven reliability. Internal RF matching is also included on both the input and output to provide an easy to implement, unconditionally stable, 50 ohm circuit block. Product Specifications FO Frequency Range GHz 1.7 2.0 >2.0 2.2 S21 Gain dB 13.5 15 16.5 13 14.5 16 S11 Input Return Loss dB 10 12 – 10 12 – S22 Output Return Loss dB 10 13 – 10 13 – NF Noise Figure dB – 1.05 1.3 – 1.05 1.3 OIP3 Output Third Order Intercept Point dBm 32 34 – 33 35 – P1dB Compression Point dBm 20 19 GD Group Delay ns <0.5 <0.5 Deviation from Linear Phase (over 100MHz) degrees <0.15 <0.1 S12 Reverse Isolation dB -23 -23 Vdd Supply Voltage V 4.75 5 5.25 Idd Supply Current mA 90 108 120 Rth Thermal Resistance (junction-back) ºC/W 80 All parameters measured in a 50 ohm system, Vdd=5V, T=25ºC. OIP3 measured at a power of 6dBm per tone, 6MHz tone spacing. NOTE: For applications between 2.2 - 2.5GHz please contact apps@sirenza.com Noise Figure SLX-2143 1700-2200 MHz High Linearity Low Noise Amplifier Module Product Features
Applications
Very Low Noise Figure, 1.05dB High OIP3 = +35dBm at 2GHz Gain = 15dB, Low Gain Slope 50Ω Input/Output Match, Stable Single Supply Operation, Self Biased PCS, TDMA, CDMA, WCDMA receivers Product Description Noise Figure 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Frequency (GHz) Noise Figure (dB)
522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com
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S LX - 214 3 170 0- 220 0 M Hz LN A Mo dul e Absolute Maximum Ratings Parameters Value Unit Supply Current (Idd) 150 mA Device Voltage (Vdd) 5.5 V Operating Temperature -40 to +85 ºC Storage Temperature Range -65 to +150 ºC Peak Reflow Temperature (30sec) +230 ºC Operating Junction Temperature +150 ºC Maximum Input Power +20 dBm Subjecting this device at or beyond any one of these limits may cause permanent damage. For reliable operation, the device operating voltage and current must not exceed the maximum values shown in the “Product Specifications” table. Bias conditions should also satisfy the following expression: V DD IDD RTH <T J -T OP,w h e r eTJ is the junction tempera- ture (150ºC) and TOP is the board temperature. Ga in Frequency (GHz) Gain (dB) -40ºC +85ºC Reverse Isolation -30 -26 -22 -18 -14 -10 Frequency (GHz) S12 (dB) -40ºC +85ºC Input Return Loss -25 -20 -15 -10 Frequency (GHz) S11 (dB) -40ºC +85ºC Output Return Loss -25 -20 -15 -10 Frequency (GHz) S22 (dB) -40ºC +85ºC
522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com
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S LX - 214 3 170 0- 220 0 M Hz LN A Mo dul e OIP3, P1dB, G ain and NF Dependence on Vdd at 2G Hz, +40ºC Vdd (V) IP3 (dBm), P1dB (dBm), Gain (dB),NF (dBX10)TOI Gain P1dB NF (x10) Supply Current, Idd, Variation with Supply Voltage, Vdd 100 102.5 105 107.5 110 Vdd (V) Idd (mA) G roup Delay, Devation from Linear Phase over 100MHz 0.1 0.2 0.3 0.4 0.5 0.6 Fr e que ncy (GHz) Delay (nS), Deviation from Lin Phase (degs) Delay Dev. Linear Phase Noise Figure 0.00 0.50 1.00 1.50 2.00 Frequency (GHz) Noise Figure (dB) -40ºC +35ºC +85ºC Compression Point P1dB @ 2GHz, +25ºC, Vdd=5 Frequency (GHz) P1dB (dBm) Output Intercept, OIP3 Frequency (GH z) Output Intercept (dBm) -40º +35º C +85ºC
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S LX - 214 3 170 0- 220 0 M Hz LN A Mo dul e Pin # Function Description Device Schematic 1R F I n RF input pin. This pin is at DC ground. An external DC block- ing capacitor should be used in most applications.
2 RF Out/
RF output and bias pin. Bias should be supplied to this pin through an external RF choke inductor. Because DC biasing is present on this pin, a DC blocking capacitor should be used in most applications (see application schematic). The supply side of the bias network should be well bypassed. Package Backside GND Connection to RF/DC ground. For best performance use via holes as shown in recommended PCB layout to reduce induc- tance and to provide adequate thermal path. Part Number Ordering Information Part Number Reel Size Devices/Reel SLX-2143 7” 500 Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Part Symbolization The part will be symbolized with an “SLX2143” on the top surface of the package. Package Dimensions (“43” Ceramic Module) RF In RF Out/ DC In All dimensions in inches (mm) RF Output/ DC Input RF Input SLX-2143 X-XX XX-X YYWW 0.015 (0.38) Denotes Pin 1 0.024 (0.6) 0.272 (6.9) 0.136 (3.45) 0.394 (10.0) 0.097 (2.47) Backside must connect to DC/RF ground 0.4 (10.16) 0.275 (6.98) 0.05 (1.27) typical 0.04 (1.02) 0.02 (0.51) 0.04 (1.02) 0.03 (0.76) 0.295 (7.5) All plated thru holes: 0.02 (0.5) diameter. All dimensions in inches (mm). Board material: FR-4, 0.032 (.81) thick. Solder Outline 0.015 (.38) PCB Front Test PCB Pad Layout 0.4 (10.16) 0.275 (6.98) 0.05 (1.27) typical 0.04 (1.02) 0.02 (0.51) 0.04 (1.02) 0.03 (0.76) 0.295 (7.5) All plated thru holes: 0.02 (0.5) diameter. All dimensions in inches (mm). Board material: FR-4, 0.032 (.81) thick. Solder Outline 0.015 (.38) PCB Front 0.256 (6.5) 0.035 (0.90) 0.024 (0.62) 0.028 (0.70) 0.378 (9.6) All dimensions in inches (mm). M a t e r i a l :C uw i t hA uf l a s h . 0.02 (.50) .012 (.30) radius Package Back
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S LX - 214 3 170 0- 220 0 M Hz LN A Mo dul e C1 C2 RF OUTRF IN Package Backside Connect to RF/D C ground SLX-2143 C4 C3 VD 1.7GHz to 2.2GHz Test Board P/N EEB102508 Bill of Materials Component Designator Value Qty Vendor Part Number Description U1 1 SMDI SLX-2143 High linearity low noise amplifier S1, S2 2 Johnson Components 142-0701-851 SMA side mount connector C1, C2 10 pF 2 Kemet C0603C100J5GAC 0603 capacitor C3 220 pF 1 Kemet C0603C221J5GAC 0603 capacitor C4 0.01 uF 1 Kemet C0603C103K5RAC 0603 capacitor R1 0 Ω 1 Panasonic POOGCTND 0603 jumper J1 1 Sullins S1312-2-ND 2 pin header L1 47 nH 1 TOKO LL1608-F47NK 0603 inductor 1.7GHz to 2.2GHz Application Schematic Sirenza Microdevices LNA C1 C2 C3C4 R1J1 S1 S2 RF Input RF Output SLX-2143 1.5" (38.1mm) 1.8" (45.7mm) VDD
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S LX - 214 3 170 0- 220 0 M Hz LN A Mo dul e Abstract This application note describes the components and materials that make up the SLX-2143 low noise amplifier module. It also describes the circuit board layout required for optimum performance, and procedures for reliable sol- der attachment. Introduction T h eS L X - 2 1 4 3i sat h i c kf i l mh y b r i dl o wn o i s ea m p l i f i e r designed for 1.7 - 2.2GHz applications that require both low noise figure and good linearity. This module is based on conventional thick film circuit fabrication methods, and can be surface mounted onto circuit boards using industry stan- dard solder reflow techniques. In order to extract peak per- formance from this amplifier, it is important to use an appropriate circuit board layout, and to ensure that the part is soldered down correctly. Please contact apps@sirenza.com if your application is between 2.2 - 2.5 GHz. Materials The base of the SLX-2143 is an alumina (ceramic) “thick film” substrate, 0.015” (.38mm) thick. The back of this substrate is metallized with plated copper (on a base layer of fired silver) that has been protected with a thin flash of nickel and gold to guarantee solderability, even after extended storage time. The ceramic substrate has via holes that are filled with a fired silver compound. On the compo- nent side of the substrate (the side that is covered with the lid) there are conductors based on plated copper (that are protected with a flash of nickel-gold), and pure gold conduc- tors. The copper conductors are formed by plating copper onto a silver conductor that has been fired into the sub- strate. The fired silver base ensures excellent adhesion to the substrate, and the plated copper ensures that the silver is completely protected. The gold conductors are fired into the substrate and are used wherever wire bonds are required. Thick film resistors are also integrated onto this substrate. A glass passivation layer is used for additional protection, and to act as a solder dam. Inside the module there are several different types of components in use. Solder terminated capacitors and inductors are attached with high temperature lead free (96.5% Sn 3.5% Ag) solder. Chip components are attached with conductive silver epoxy and are connected to the rest of the circuit with gold wire-bonds. The module is sealed w i t hac e r a m i cl i dt h a ti sh e l dd o w nw i t haB - s t a g ee p o x y seal ring. The overall module is non-hermetic, but it will pass a standard “bubble” leak test. T h em o d u l ei sd e s i g n e dt ob er e f l o w e do n t oal a m i n a t e based circuit board such as FR4. Input and output connec- tions to the module are made with “castellations” on either end of the module. Castellations are rounded metallized notches (metallized with silver, copper, nickel, gold, as in other parts of the module) in the edge of the ceramic sub- strate. When these are put through a solder reflow process, the solder tends to wick up into the notches, creating a robust solder fillet that can be easily inspected. The third connection, ground, is formed by the rest of the metal on the back of the module. Board Design As the module has the input, output, and ground con- nections on the same plane, in principal coplanar w a v e g u i d es h o u l db eu s e dt of e e dt h em o d u l e .I np r a c t i c e , m i c r o s t r i pc a na l s ob eu s e da sg r o u n dv i a su n d e rt h em o d - ule connect the “top” ground to a microstrip ground plane. Care still needs to be taken to ensure a graceful transition from microstrip to coplanar waveguide. Care also needs to be taken to ensure that the medium leading up to the mod- ule (be it microstrip, coplanar waveguide, or grounded coplanar waveguide) is 50 ohms, with minimal loss. The dimensions used in the evaluation board are recommended (they yield a return loss of 27dB at 2 GHz) if that material structure can be adapted. The evaluation board layout is shown in Figure 1. The DC blocks, bias inductor, and decoupling capacitors are also shown on the board. The coplanar line leading up to the module has a width of 0.04” (1.0mm) with a spacing of 0.02” (0.5mm) to the coplanar ground. The thickness of the board dielectric, FR4, is 0.032” (0.81mm), although typically the overall board thickness is increased with additional lay- ers. One ounce copper is used on both sides. At 2.5GHz, the performance of the FR-4 board material is becoming marginal, so users may find it necessary to adjust the tuning of the part with external turning elements if operating at this frequency. Sirenza Microdevices will provide the detailed layout (in AutoCAD format) to users wishing to use the same layout and materials.
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S LX - 214 3 170 0- 220 0 M Hz LN A Mo dul e Solder Reflow The module is designed to be soldered onto a pad that has an array of via holes for improved grounding. Note that the module is reasonably tolerant of voids in the solder cov- erage on the back, but that voids should be avoided because they can result in an increase in thermal imped- ance, which will result in the module running too hot. The gold content on the back is very small so solder embrittle- ment will not be a problem. The module can be assembled onto a circuit board using standard oven or IR reflow profiles. It is difficult to rec- ommend any single reflow profile because such profiles depend on the board size, other components on the board, and the reflow equipment in use. The most critical parame- ter is the peak temperature. Reflow profiles that have a peak temperature on the order of 220ºC-240ºC for 30 sec- onds will be adequate for this part. Lower peak tempera- tures can be used if the time is increased. For small volume prototype fabrication and rework, a hot plate running at about 250ºC is recommended, with the part left on only until the solder reflows. Soldering irons are not recommended for mounting or removing the part. There is a thermal coefficient of expansion mismatch between the module and typical circuit board material, but the small dimensions of the module make the strain induced into the module minimal, so no stress related prob- lems should be encountered. If the module is mounted on a very thin laminate (such as FR-4 0.032” (0.81mm) or less), then care should be taken to avoid flexing the laminate, as the ceramic substrate could crack. This has not been observed on conventional thick circuit board materials. (The evaluation board is a three layer structure with two .032” thick dielectric layers.) Conclusion The SLX-2143 has been designed to be both easy to use and robust, and lab tests done at Sirenza Microdevices have repeatedly demonstrated this. By following the guide- lines in this application note, excellent performance can be achieved. We hope that this application note and the prod- ucts offered by Sirenza Microdevices will assist you in achieving your design goals. If there are any questions about this module or any other Sirenza Microdevices part, please contact us at apps@sirenza.com. Figure 1: Evaluation Board Layout