SLW24N50C THINKISEMI | Alldatasheet
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Technical content
Features
※ Uninterruptible Power Supply(UPS) LCD Panel Power ※ DC-AC Inverter,Amplifier and SMPS Mechanical Data ※ Case:TO-3P non-isolated package ※ Terminals: Solderable p er MIL-STD-202 method 208 ※ Polarit y : As per configuration ※ Mountin g p osition: An y ※ Wei g ht: 6.0 g ram a pp roximatel y Epoxy: UL 94V-0 rate flame retardant Schematic Diagram Low ON Resistance Low Gate Charge Peak Current vs Pulse Width Curve ESD Capability Improved 100% Avalanche Tested Absolute Maximum Ratings T C = 25°C unless otherwise noted V DSS Drain-Source Voltage 500 V Drain Current Continuous (T C =2 5 A I D Drain Current Continuous C A - Continuous (T C = 100℃)1 5 A I DM Drain Current - Pulsed (Note 1) 96 A V GSS Gate-Source Voltage ±30 V EAS Single Pulsed Avalanche Energy (Note 2) 1150 mJ I AR Avalanche Current (Note 1) 24 A E AR Repetitive Avalanche Energy (Note 1) 29 mJ dv/dt Peak Diode Recovery dv/dt (Note 3)
4.5 V/ns
P D Power Dissipation (T C = 25℃) 290 W P D - Derate above 25℃ 2.33 W/ ℃ T J , T STG Operating and Storage Temperature Range -55 to +150 ℃ T L Maximum lead temperature for soldering purposes, 300 ℃1/8" from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units Symbol Parameter Typ Max Units R θJC Thermal Resistance, Junction-to-Case -- 0.43 ℃/W R θJS Thermal Resistance, Case-to-Sink Typ. 0.24 -- ℃/W R θJA Thermal Resistance, Junction-to-Ambient -- 40 ℃/W Symbol Parameter SLW24N50C Units
http://www.thinkisemi.com.tw/ Page 2/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd.
Electrical Characteristics
T C = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain-Source Breakdown Voltage V GS = 0 V, I D = 250 uA 500 -- -- V △BV DSS / △T J Breakdown Voltage Temperature Coefficient I D = 250 uA, Referenced to 25℃ -- 0.5 -- V/ ℃ I DSS Zero Gate Voltage Drain Current V DS = 500 V, V GS = 0 V -- -- 1 uA V DS = 400 V, T C = 125℃ -- -- 10 uA I GSSF Gate-Body Leakage Current, Forward V GS = 30 V, V DS = 0 V -- -- 100 nA I GSSR Gate-Body Leakage Current, Reverse V GS = -30 V, V DS On Characteristics On Characteristics V GS(th) Gate Threshold Voltage V DS = V GS , I D = 250 uA 2.0 -- 4.0 V R DS(on) Static Drain-Source On-Resistance V GS = 10 V, I D = 12 A -- 0.16 0.2 Ω g FS Forward Transconductance V DS = 40 V, I D = 12 A (Note 4) -- 15 -- S Dynamic Characteristics C iss Input Capacitance V DS = 25 V, V GS = 0 V, -- 3500 -- pF C Output Capacitance 520 pF f = 1.0 MHz C oss Output Capacitance 520 pF C rss Reverse Transfer Capacitance -- 55 -- pF Switching Characteristics t d(on) Turn-On Delay Time V DD = 250 V, I D = 24 A, R G = 25 Ω (Note 4, 5) -- 100 -- ns t r Turn-On Rise Time -- 250 -- ns t d(off) Turn-Off Delay Time -- 200 -- ns t f Turn-Off Fall Time -- 150 -- ns Q g Total Gate Charge V DS = 400 V, I D = 24 A, V 10 V -- 90 -- nC Q Gate Source Charge nC V GS V (Note 4, 5) Q gs Gate Source Charge nC Q gd Gate-Drain Charge -- 45 -- nC Drain-Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current -- -- 24 A I SM Maximum Pulsed Drain-Source Diode Forward Current -- -- 96 A V SD Drain-Source Diode Forward Voltage V GS = 0 V, I S = 24 A -- -- 1.4 V t rr Reverse Recovery Time V GS = 0 V, I S Q rr Reverse Recovery Charge dI F / dt = 100 A/us (Note 4) -- 4.3 -- uC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 3.4mH, I AS = 24A, V DD = 50V, R G = 25Ω, Starting T J = 25°C 3. I SD 24A, di/dt 200A/us, V DD BV DSS, Starting T J = 25°C 4. Pulse Test : Pulse width 300us, Duty cycle 2% 5. Essentially independent of operating temperature SLW24N50C
http://www.thinkisemi.com.tw/ Page 5/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd. Gate Charge Test Circuit & Waveform Current Regulator V GS 10V Q g Q gs Q gd V GS DUT V DS 300nF 50KΩ 200nF12V Same Type as DUT Resistive Switching Test Circuit & Waveforms Charge 3mA Current Sampling (I G ) Current Sampling (I D Resistor Resistor R R V in V out 10% 90%V DD ( 0.5 rated V DS V out V in R L DUT R G Unclamped Inductive Switching Test Circuit & Waveforms t d(on) t r t on t off t d(off) t f 10V E AS 1---- L L I AS2 BV DSS -- V DD BV DSS Vary t p to obtain required peak I D V DD C L L V DS I D R G DUT V DD BV DSS I AS V DS (t) I D (t) 10V t p t p Time SLW24N50C
http://www.thinkisemi.com.tw/ Page 6/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT V DS L I S V Driver GS Same Type as DUT R G V GS
- dv/dt controlled by 밨 G S controlled by Duty Factor 밆? V DD
- dv/dt controlled by R G
- I SD controlled by pulse period V GS ( Driver ) I S I FM , Body Diode Forward Current Gate Pulse Width Gate Pulse Period 10V ( DUT ) V DS ( DUT ) I RM Body Diode Reverse Current Body Diode Recovery dv/dt di/dt V DD Body Diode Forward Voltage Drop V f SLW24N50C
15.60 ±0.20 4.80 ±0.20 13.60 ±0.20 9.60 ±0.20 2.00 ±0.20 3.00 ±0.20 1.00 ±0.20 1.40 ±0.20 ø3.20 ±0.10 3.80 ±0.20 13.90 ±0.20 3.50 ±0.20 16.50 ±0.30 12.76 ±0.20 19.90 ±0.20 23.40 ±0.20 18.70 ±0.20 1.50 +0.15 –0.05 0.60 +0.15 –0.05 5.45TYP [5.45 ±0.30 5.45TYP [5.45 ±0.30 TO-3PN-SQ/TO-3PB-SQ http://www.thinkisemi.com.tw/ Page 7/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd. SLW24N50C