SLW20N50C THINKISEMI | Alldatasheet
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Technical content
Features
※ Uninterruptible Power Supply(UPS) LCD Panel Power ※ DC-AC Inverter,Amplifier and SMPS Mechanical Data ※ Case:TO-3P non-isolated package ※ Terminals: Solderable p er MIL-STD-202 method 208 ※ Polarit y : As per configuration ※ Mountin g p osition: An y ※ Wei g ht: 6.0 g ram a pp roximatel y Epoxy: UL 94V-0 rate flame retardant Schematic Diagram Low ON Resistance Low Gate Charge Peak Current vs Pulse Width Curve ESD Capability Improved 100% Avalanche Tested Absolute Maximum Ratings T C = 25°Cunless otherwise noted * Drain current limited by maximum junction temperature. Thermal Characteristics V DSS Drain-Source Voltage 500 V I D Drain Current - Continuous (T C = 25°C) 20 A - Continuous (T C = 100°C) 13 A I DM Drain Current - Pulsed (Note 1) 80 A V GSS Gate-Source Voltage 30 V E AS Single Pulsed Avalanche Energy (Note 2) 1110 mJ E AR Repetitive Avalanche Energy (Note 1) 28 mJ dv/dt Peak Diode Recovery dv/dt (Note 3)
4.5 V/ns
P D Power Dissipation (T C = 25°C) 280 W - Derate above 25°C 2.3 W/°C T J , T STG Operating and Storage Temperature Range -55 to +150 °C T L Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 300 °C Symbol Parameter TYP MAX Units R JC Thermal Resistance, Junction-to-Case -- 0.44 °C /W R CS Thermal Resistance, Case-to-Sink Typ. 0.24 -- °C /W R JA Thermal Resistance, Junction-to-Ambient -- 40 °C /W Symbol Parameter SLW20N50C Units
http://www.thinkisemi.com.tw/ Page 2/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd.
Electrical Characteristics
T C = 25°C unless otherwise noted Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 5 mH, I AS = 20 A, V DD = 50V, R G = 25 Starting T J = 25°C 3. I SD 20 A, di/dt 200A/s, V DD BV DSS, Starting T J = 25°C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain-Source Breakdown Voltage V GS = 0 V, I D BV DSS / T J Breakdown Voltage Temperature Coefficient I D = 250 A, Referenced to 25°C -- 0.5 -- V/°C I DSS Zero Gate Voltage Drain Current V DS = 500 V, V GS = 0 V -- -- 1 A V DS = 400 V, T C I GSSF Gate-Body Leakage Current, Forward V GS = 30 V, V DS = 0 V -- -- 100 nA I GSSR Gate-Body Leakage Current, Reverse V GS = -30 V, V DS On Characteristics V GS(th) Gate Threshold Voltage V DS = V GS , I D R DS(on) Static Drain-Source On-Resistance V GS = 10 V, I D Dynamic Characteristics C iss Input Capacitance V DS = 25 V, V GS = 0 V, f = 1.0 MHz -- 2700 -- pF C oss Output Capacitance -- 400 -- pF C rss Reverse Transfer Capacitance -- 40 -- pF Switching Characteristics t d(on) Turn-On Delay Time V DD = 250 V, I D = 20 A, R G = 25 (Note 4, 5) -- 100 -- ns t r Turn-On Rise Time -- 400 -- ns t d(off) Turn-Off Delay Time -- 100 -- ns t f Turn-Off Fall Time -- 100 -- ns Q g Total Gate Charge V DS = 400 V, I D = 20 A, V GS = 10 V (Note 4, 5) -- 70 - nC Q gs Gate-Source Charge -- 18 -- nC Q gd Gate-Drain Charge -- 35 -- nC Drain-Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current -- -- 20 A I SM Maximum Pulsed Drain-Source Diode Forward Current -- -- 80 A V SD Drain-Source Diode Forward Voltage V GS = 0 V, I S = 20 A -- -- 1.5 V t rr Reverse Recovery Time V GS = 0 V, I S = 20 A, dI F / dt = 100 A/s (Note 4) -- 500 -- ns Q rr Reverse Recovery Charge -- 7.2 -- C SLW20N50C
http://www.thinkisemi.com.tw/ Page 5/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd. Gate Charge Test Circuit & Waveform V Current Regulator V GS 10V Q g Q gs Q gd V GS DUT V DS 300nF 50KΩ 200nF12V Same Type as DUT Resistive Switchin g Test Circuit & Waveforms Charge 3mA Current Sampling (I G Resistor Current Sampling (I D Resistor R R g V in V out 10% 90%V DD ( 0.5 rated V DS 10V V out V in R L DUT R G Unclamped Inductive Switching Test Circuit & Waveforms t d(on) t r t on t off t d(off) t f 10V E AS L I AS ---- BV DSS -- V DD BV DSS Vary t p to obtain required peak I D V DD C L L V DS I D R G DUT BV DSS V DD I AS V DS (t) I D (t) 10V t p t p Time SLW20N50C
http://www.thinkisemi.com.tw/ Page 6/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT DUT V DS L I S DriverV GS R G Same Type as DUT V GS
- dv/dt controlled by 밨 G S controlled by Duty Factor 밆? V DD
- dv/dt controlled by R G
- I SD controlled by pulse period 10V V GS ( Driver ) I S I FM , Body Diode Forward Current D = Gate Pulse Width Gate Pulse Period S ( DUT ) V DS ( DUT ) Body Diode Reverse Current I RM Body Diode Recovery dv/dt di/dt V DD Body Diode Forward Voltage Drop V f SLW20N50C
15.60 ±0.20 4.80 ±0.20 13.60 ±0.20 9.60 ±0.20 2.00 ±0.20 3.00 ±0.20 1.00 ±0.20 1.40 ±0.20 ø3.20 ±0.10 3.80 ±0.20 13.90 ±0.20 3.50 ±0.20 16.50 ±0.30 12.76 ±0.20 19.90 ±0.20 23.40 ±0.20 18.70 ±0.20 1.50 +0.15 –0.05 0.60 +0.15 –0.05 5.45TYP [5.45 ±0.30 5.45TYP [5.45 ±0.30 TO-3PN-SQ/TO-3PB-SQ http://www.thinkisemi.com.tw/ Page 7/7Rev.11T © 1995 Thinki Semiconductor Co., Ltd. SLW20N50C