TLV705_16 TI1 | Alldatasheet
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/c109 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TLV705,TLV705P SBVS151E –DECEMBER 2010–REVISED MAY 2015 TLV705x200-mA,LowIQ,Low-Noise,Low-DropoutRegulatorinUltra-Small, 0.8-mm×0.8-mmDSBGAandPicoStar™
1 Features 3 Description
The TLV705 series of low-dropout (LDO) linear 1• Very Low Dropout: regulators are low quiescent current devices with– 105 mV at IOUT = 150 mA excellent line and load transient performance. These – 145 mV at IOUT = 200 mA devices are designed for power-sensitive applications, with a precision band gap. An error• Accuracy: 0.5% Typical amplifier provides typical accuracy of 0.5%. Low• Low IQ: 35 μA output noise, very high power-supply rejection ratio
- Available in Fixed-Output Voltages From (PSRR), and low dropout voltage make this series of 0.7 V to 4.8 V LDOs ideal for a wide selection of battery-operated hand-held equipment. All devices have a thermal• VIN Range: 2 V to 5.5 V shutdown and current limit for safety.• High PSRR: 70 dB at 1 kHz Furthermore, the TLV705 series is stable with an• Stable With Effective Capacitance of 0.1 μF effective output capacitance of only 0.1 μF. This• Thermal Shutdown and Overcurrent Protection feature enables the use of cost-effective capacitors
- Available in an Ultra-Low Profile (0.2-mm Max that have higher bias voltage and temperature Height) PicoStar Package Option derating. The devices regulate to the specified accuracy with zero output load. The TLV705P series also provides an active pulldown circuit to quickly2 Applications discharge output.• Wireless Handsets The TLV705 and TLV705P series are both available• Smart Phones in 0.8-mm × 0.8-mm DSBGA and PicoStar packages• Zigbee® Networks with three height options that are optimal for hand-
- Bluetooth® Devices held applications.
- Other Li-Ion Operated Hand-Held Products Device Information(1)
- WLAN and Other PC Add-On Cards PART NUMBER PACKAGE BODY SIZE (NOM) DSGBA (4) 0.80 mm × 0.80 mm TLV705x PicoStar (4) 0.77 mm × 0.77 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit (Fixed-Voltage Versions) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV705,TLV705P SBVS151E –DECEMBER 2010–REVISED MAY 2015 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (April 2015) to Revision E Page Changes from Revision C (October 2012) to Revision D Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
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Product Folder Links: TLV705 TLV705P
TLV705,TLV705P www.ti.com SBVS151E –DECEMBER 2010–REVISED MAY 2015 Changes from Revision B (December 2011) to Revision C Page Changes from Revision A (August 2011) to Revision B Page Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TLV705 TLV705P
TLV705,TLV705P SBVS151E –DECEMBER 2010–REVISED MAY 2015 www.ti.com
5 Pin Configuration and Functions
YFF, YFP Packages YFM Package 4-Pin DSBGA 4-Pin PicoStar Top View Top View Pin Functions PIN I/O DESCRIPTION NAME NO. GND A1 — Ground pin. Enable pin. EN A2 I Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode, thus reducing operating current to 1 μA, nominal. Regulated output voltage pin. VOUT B1 O A small 1-μF ceramic capacitor is required to be placed from this pin to ground to assure stability. See the Input and Output Capacitor Requirements section for more details. Input pin. VIN B2 I A small 1-μF ceramic capacitor is recommended to be placed from this pin to ground for good transient performance. See the Input and Output Capacitor Requirements section for more details.
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Product Folder Links: TLV705 TLV705P
TLV705,TLV705P www.ti.com SBVS151E –DECEMBER 2010–REVISED MAY 2015
6 Specifications
6.1 Absolute Maximum Ratings
Specified at TJ = –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND.(1) MIN MAX UNIT VIN –0.3 6 V Voltage(2) VEN –0.3 6 V VOUT –0.3 6 V Maximum output current IOUT Internally limited Output short-circuit duration Indefinite Operating junction, TJ –55 150 °C Temperature Storage, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) All voltages are with respect to network ground pin.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 2 5.5 V VOUT Output voltage 0.7 4.8 V IOUT Output current 0 200 mA TJ Junction temperature –40 125 °C
6.4 Thermal Information
YFF, YFP YFMTHERMAL METRIC(1) UNIT(DSBGA) (PicoStar)
4 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 160 191.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 80 3.1 °C/W RθJB Junction-to-board thermal resistance 90 36.5 °C/W ψJT Junction-to-top characterization parameter 0.5 2.8 °C/W ψJB Junction-to-board characterization parameter 78 26.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TLV705 TLV705P
TLV705,TLV705P SBVS151E –DECEMBER 2010–REVISED MAY 2015 www.ti.com
6.5 Electrical Characteristics
At TJ = –40°C to 125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = 0.9 V, and COUT = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range 2 5.5 V VOUT Output voltage range 0.7 4.8 V 0 mA ≤ IOUT ≤ 200 mA, VOUT ≥ 1 V –2% ±0.5% 2% VO DC output accuracy –40°C ≤ TJ ≤ 125°C 0 mA ≤ IOUT ≤ 200 mA, VOUT < 1 V –20 ±5 20 mV ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V 0.05 5 mV ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 200 mA 1 mV VDO Dropout voltage(1) VIN = 0.98 × VOUT(nom), IOUT = 200 mA 145 250 mV ICL Output current limit VOUT = 0.9 × VOUT(nom), TJ = 25°C 260 400 550 mA IOUT = 0 mA 35 55 μA IGND Ground pin current IOUT = 200 mA 315 μA Shutdown ground pinISHUTDOWN VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V 1 1.8 μAcurrent VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 10 kHz 80 dBPower-supplyPSRR rejection ratio VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 MHz 55 dB VIN = 2.3 V, VOUT = 1.8 V 26.6 μVRMS BW = 100 Hz to VIN = 3.3 V, VOUT = 2.8 V 26.7 μVRMS100 kHz, IOUT = 10 mA VIN = 3.8 V, VOUT = 3.3 V 28.2 μVRMS Vn Output noise voltage VIN = 2.3 V, VOUT = 1.8 V 30.7 μVRMS BW = 10 Hz to 100 kHz, VIN = 3.3 V, VOUT = 2.8 V 31.3 μVRMSIOUT = 10 mA VIN = 3.8 V, VOUT = 3.3 V 34.1 μVRMS tSTR Start-up time(2) COUT = 1 μF, IOUT = 200 mA 100 μs VHI Enable high (enabled) 0.9 VIN V VLO Enable low (disabled) 0 0.4 V IEN EN pin current VEN = 5.5 V 0.01 μA UVLO Undervoltage lockout VIN rising 1.9 V Shutdown, temperature increasing 160 °CThermal shutdowntSD temperature Reset, temperature decreasing 140 °C Operating junctionTJ –40 125 °Ctemperature (1) VDO is measured for devices with VOUT(nom) = 2.35 V so that VIN = 2.3 V. (2) Start-up time = time from EN assertion to 0.98 × VOUT(nom).
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Product Folder Links: TLV705 TLV705P
6.6 Typical Characteristics
or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C. Figure 1. Line Regulation Figure 2. Line Regulation Figure 3. Load Regulation ( 0 mA ≤ IOUT ≤ 200 mA) Figure 4. Dropout Voltage vs Input Voltage Figure 5. Dropout Voltage vs Output Current Figure 6. Output Voltage vs Temperature
or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C. Figure 7. Ground Pin Current vs Input Voltage Figure 8. Ground Pin Current vs Output Current Figure 9. Ground Pin Current vs Temperature Figure 10. Shutdown Pin Current vs Input Voltage Figure 11. Current Limit vs Input Voltage Figure 12. Power-Supply Rejection Ratio vs Frequency
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or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C. Figure 19. Small-Step Line Transient (10 mA) Figure 20. Small-Step Line Transient (200 mA) Figure 21. VIN Inrush Current Figure 22. VIN Inrush Current Figure 23. Line Transient (10 mA) Figure 24. Line Transient (200 mA)
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or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = 25°C. Figure 25. Power-Up and Power-Down
7 Detailed Description
7.1 Overview
TLV705P provides an active pulldown circuit to quickly discharge the outputs.
7.2 Functional Block Diagrams
Figure 26. TLV705 Series Figure 27. TLV705P Series
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TLV705,TLV705P www.ti.com SBVS151E –DECEMBER 2010–REVISED MAY 2015
7.3 Feature Description
7.3.1 Internal Current Limit
The internal current limits of the TLV705 series help protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated, and can be measured as VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When the device cools down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown; see the Power Dissipation and Junction Temperature section for more details. The PMOS pass element in the TLV705 has a built-in body diode that conducts current when the voltage at VOUT exceeds the voltage at VIN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended.
7.3.2 Undervoltage Lockout (UVLO)
The TLV705 uses an UVLO circuit to keep the output shut off until the internal circuitry is operating properly.
7.3.3 Start-Up Current
The TLV705 uses a unique start-up architecture that creates a constant start-up time regardless of the output capacitor. The start-up current is given by Equation 1. Equation 1 shows that start-up current is directly proportional to COUT. ISTARTUP = COUT (μF) × 0.06 (Vμs) + ILOAD (mA) (1) The output voltage ramp rate is independent of COUT and the load current, and has a typical value of 0.06 V/μs. The TLV705 automatically adjusts the soft-start current to supply both the load current and the current to charge COUT. For example, if ILOAD = 0 mA upon enabling the LDO, then ISTARTUP = 1 μF × 0.06 Vμs + 0 mA = 60 mA, which is the current that charges the output capacitor. However, if ILOAD = 200 mA, then ISTARTUP = 1 μF × 0.06 V / μs + 200 mA = 260 mA, which is the current required for charging the output capacitor and supplying the load current. If the output capacitor and load are increased such that the start-up current exceeds the output current limit, the start-up current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, then 10 μF × 0.06 V / μs + 200 mA = 800 mA is not supplied and is instead clamped at 400 mA.
7.3.4 Dropout Voltage
The TLV705 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(on) of the PMOS pass element. VDO approximately scales with the output current because the PMOS device functions as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 13 in the Typical Characteristics section.
7.3.5 Shutdown
The enable pin (EN) is active high. The device is enabled when the EN pin goes above 0.9 V. This relatively lower value of voltage required to turn the LDO on can be used to power the device with the GPIO of recent processors with a GPIO voltage lower than traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the VIN pin. The TLV705P version has internal active pulldown circuitry that discharges the output with a time constant of: τ = (120 × RL) / (120 + RL) × COUT where
- RL = load resistance
- COUT = output capacitor (2) Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TLV705 TLV705P
7.4 Device Functional Modes
7.4.1 Normal Operation
- The input voltage is greater than the nominal output voltage added to the dropout voltage.
- The output current is less than the current limit.
- The input voltage is greater than the UVLO voltage.
7.4.2 Dropout Operation
the LDO. Line or load transients in dropout can result in large output voltage deviations. Table 1 lists the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison
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8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
of this device is –40°C to 125°C.
8.2 Typical Application
Figure 28. Typical Application Circuit (Fixed-Voltage Versions)
8.2.1 Design Requirements
Table 2 lists the design parameters. Table 2. Design Parameters
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage. GND pin current, and power the load.
8.2.2.1 Input and Output Capacitor Requirements
capacitance under operating conditions is less than 0.1 μF. Maximum ESR must be less than 200 mΩ.
source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.
8.2.2.2 Transient Response
but increases the duration of the transient response.
8.2.3 Application Curves
Figure 30. Power-Up and Power-DownFigure 29. Power-Supply Rejection Ratio vs Frequency
8.3 Do's and Don'ts
Place input and output capacitors as close to the device as possible. Do not exceed the device absolute maximum ratings.
9 Power Supply Recommendations
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10 Layout
10.1 Layout Guidelines
directly to the GND pin of the device. High ESR capacitors can degrade PSRR.
10.2 Layout Example
Figure 31. Example PCB Layout
10.3 Power Dissipation
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the thermal dissipation. board with 2 ounces of copper per side.
10.4 Power Dissipation and Junction Temperature
125°C at the highest expected ambient temperature and worst-case load. running the TLV705 into thermal shutdown degrades device reliability.
/c89 /c89 /c89 /c180 JT J T JT D: T = T + P/c89 /c180 JB J B JB D: T = T + P TLV705,TLV705P SBVS151E –DECEMBER 2010–REVISED MAY 2015 www.ti.com
10.5 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances; rather, these metrics offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the Thermal Information table and are used in accordance with Equation 4. where:
- PD is the power dissipated, as explained in the Thermal Information table,
- TT is the temperature at the center-top of the device package, and
- TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge. (4)
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Product Folder Links: TLV705 TLV705P
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV705. the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
11.1.2 Device Nomenclature
Table 3. Available Options(1) = 4.75 V).TLV705xx(x)Pyyyz P is optional; devices with P have an LDO regulator with an active output discharge. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
- TLV70533EVM-596 Evaluation Module User's Guide, SLVU439
11.3 Related Links
resources, tools and software, and quick access to sample or buy. Table 4. Related Links
TLV705,TLV705P SBVS151E –DECEMBER 2010–REVISED MAY 2015 www.ti.com
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments. PicoStar is a trademark of Texas Instruments, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. Zigbee is a registered trademark of ZigBee Alliance. All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Package Mounting
Solder pad footprint recommendations for the TLV705 are available from the Packaging Information page on TI's website through the TLV705 series product folders. The recommended land patterns for the YFF, YFP, and YFM packages are appended to this data sheet.
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Product Folder Links: TLV705 TLV705P
www.ti.com 25-Aug-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV705075YFPR PREVIEW DSBGA YFP 4 3000 TBD Call TI Call TI -40 to 125 3V TLV70509YFPR PREVIEW DSBGA YFP 4 3000 TBD Call TI Call TI -40 to 125 3W TLV70512YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BU TLV70512YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BU TLV70515YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BV TLV70515YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BV TLV705185YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 YS TLV705185YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 YS TLV70518PYFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 EV TLV70518PYFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 EV TLV70518YFMR ACTIVE DSLGA YFM 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 TLV70518YFMT ACTIVE DSLGA YFM 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 TLV70518YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 WT TLV70518YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 WT TLV70525PYFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 EK TLV70525PYFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 EK TLV70525YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 YB TLV70525YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 YB
www.ti.com 25-Aug-2016 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV705285YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BW TLV705285YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BW TLV70528YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 WU TLV70528YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 WU TLV70530YFMR ACTIVE DSLGA YFM 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 TLV70530YFMT ACTIVE DSLGA YFM 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 TLV70530YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 XA TLV70530YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 XA TLV70533YFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 US TLV70533YFFT ACTIVE DSBGA YFF 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 US TLV70533YFMR ACTIVE DSLGA YFM 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 TLV70533YFMT ACTIVE DSLGA YFM 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 TLV70533YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VV TLV70533YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VV TLV70534YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 B4 TLV70534YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 B4 TLV70536YFMR ACTIVE DSLGA YFM 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125 TLV70536YFMT ACTIVE DSLGA YFM 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -40 to 125
www.ti.com 25-Aug-2016 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV70536YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BX TLV70536YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BX (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
www.ti.com 25-Aug-2016 Addendum-Page 4
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2015 Pack Materials-Page 1
(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant *All dimensions are nominal PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2015 Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70512YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70512YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70515YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70515YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV705185YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV705185YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70518PYFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70518PYFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70518YFMR DSLGA YFM 4 3000 210.0 185.0 35.0 TLV70518YFMT DSLGA YFM 4 250 210.0 185.0 35.0 TLV70518YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70518YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70525PYFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70525PYFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70525YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70525YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV705285YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV705285YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70528YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70528YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70530YFMR DSLGA YFM 4 3000 210.0 185.0 35.0 TLV70530YFMT DSLGA YFM 4 250 210.0 185.0 35.0 TLV70530YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70530YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70533YFFR DSBGA YFF 4 3000 210.0 185.0 35.0 TLV70533YFFT DSBGA YFF 4 250 210.0 185.0 35.0 TLV70533YFMR DSLGA YFM 4 3000 210.0 185.0 35.0 TLV70533YFMT DSLGA YFM 4 250 210.0 185.0 35.0 TLV70533YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70533YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70534YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70534YFPT DSBGA YFP 4 250 182.0 182.0 20.0 TLV70536YFMR DSLGA YFM 4 3000 210.0 185.0 35.0 TLV70536YFMT DSLGA YFM 4 250 210.0 185.0 35.0 TLV70536YFPR DSBGA YFP 4 3000 182.0 182.0 20.0 TLV70536YFPT DSBGA YFP 4 250 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2015 Pack Materials-Page 3
D: Max = E: Max = 0.806 mm, Min = 0.806 mm, Min = 0.746 mm 0.746 mm
www.ti.com PACKAGE OUTLINE C
0.625 MAX
0.30 0.12 0.4 TYP
0.4 TYP
4X 0.3 0.2 B E A D 4219460/A 02/2014 DSBGA - 0.625 mm max heightYFF0004 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFree TM package configuration. NanoFree Is a trademark of Texas Instruments. BALL A1 CORNER SEATING PLANE BALL TYP B A 1 2
0.015 C A B
SCALE 13.000 D: Max = E: Max = 0.806 mm, Min = 0.806 mm, Min = 0.746 mm 0.746 mm
www.ti.com EXAMPLE BOARD LAYOUT 4X 0.23 0.02 (0.4) TYP (0.4) TYP ( ) METAL 0.23 0.05 MAX SOLDER MASK OPENING METAL UNDER MASK SOLDER MASK OPENING 0.23
0.05 MIN
DSBGA - 0.625 mm max heightYFF0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM LAND PATTERN EXAMPLE SCALE:50X 1 2 A B NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (0.4) TYP (0.4) TYP 4X ( 0.25) (R ) TYP 0.05 METAL TYP 4219460/A 02/2014 DSBGA - 0.625 mm max heightYFF0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X 1 2 A B
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