SLVE2.8 | DigiCamel IC Datasheet

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1 www.semtech.com PROTECTION PRODUCTS SLVE2.8 and SLVG2.8 ESD and Latch-Up Protection Description Features Schematic & Pin Configuration Schematic & PIN Configuration Revision 01/28/03 The SLV series of transient voltage suppressors are designed to protect low voltage, state-of-the-art CMOS semiconductors from transients caused by electro- static discharge (ESD), cable discharge events (CDE), lightning and other induced voltage surges. The devices are constructed using Semtech’s propri- etary EPD process technology. The EPD process pro- vides low standoff voltages with significant reductions in leakage currents and capacitance over silicon- avalanche diode processes. The SLVE2.8 and SLVG2.8 are in a SOT-143 package and have a low 2.8V work- ing voltage. They may be used to protect one line in differential or common mode. The “flow-thru” design minimizes trace inductance and reduces voltage overshoot associated with ESD events. The SLV is specifically designed to protect low voltage components such as Ethernet transceivers, laser diodes, ASICs, and high-speed RAM. The low clamping voltage of the SLV minimizes the stress on the pro- tected IC. The SLV series TVS diodes will exceed the surge re- quirements of IEC 61000-4-2, Level 4.

Applications

Mechanical Characteristics ESD and Latch-up Protection Analog Inputs WAN/LAN Equipment Low Voltage ASICs Desktops, Servers, Notebooks and Handhelds Portable Instrumentation Base Stations Laser Diode Protection 300 Watts peak pulse power (t p = 8/20 μs) Transient protection for low voltage data lines to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 24A (8/20 μs) Protects one line Comprehensive pin out for easy board layout Low capacitance Low leakage current Low operating and clamping voltages Solid-state EPD TVS process technology JEDEC SOT-143 package Molding compound flammability rating: UL 94V-0 Marking : Marking code Packaging : Tape and Reel per EIA 481 SLVE2.8 (Top View) 2 3 2 3 SLVG2.8 (Top View)

Electrical Characteristics

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3© 2003 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SLVE2.8 and SLVG2.8 Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time 100 110 0 25 50 75 100 125 150 Ambient Temperature - T A (oC) % of Rated Power or IPP Power Derating Curve Pulse Waveform Clamping Voltage vs. Peak Pulse Current 100 110 0 5 10 15 20 25 30 Time (μs) Percent of IPP e td = IPP/2 Waveform Parameters: tr = 8μs td = 20μs 0.01 0.1 0.1 1 10 100 1000 Pulse Duration - tp (μs) Peak Pulse Power - Ppk (kW) 0 5 10 15 20 25 30 Peak Pulse Current - IPP (A) Clamping Voltage - VC (V) SLVG2.8 SLVE2.8 Waveform Parameters: tr = 8μs td = 20μs

4© 2003 Semtech Corp. www.semtech.com PROTECTION PRODUCTSPROTECTION PRODUCTS SLVE2.8 and SLVG2.8 Circuit Diagrams Common Mode Protection (SLVE2.8 and SLVG2.8) Device Connection Electronic equipment is susceptible to transient distur- bances from a variety of sources including: ESD to an open connector or interface, direct or nearby lightning strikes to cables and wires, and charged cables “hot plugged” into I/O ports. The SLV series is designed to protect sensitive components from damage and latch- up which may result from such transient events. The SLVG2.8 is designed to protect one unidirectional line while the SLVE2.8 is designed to protect one bidirec- tional line (or two differential lines). The options for connecting the devices are as follows: z SLVE2.8: Common mode protection of one bidirec- tional data line is achieved by connecting the data line input/output at pins 2 and 3. Pins 1 and 4 are connected to ground. For differential protection, pins 1 and 4 can be connected to a second I/O line. For best results, the ground connection should be made directly to a ground plane on the board. The path length should be kept as short as possible to minimize parasitic inductance. z SLVG2.8: Common mode protection of one unidi- rectional line is achieved by connecting the line to be protected at pins 2 and 3. Pins 1 and 4 are connected to ground. For best results, the ground connection should be made directly to a ground plane on the board. The path length should be kept as short as possible to minimize parasitic inductance. Circuit Board Layout Recommendations for Suppres- sion of ESD. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: z Place the TVS near the input terminals or connec- tors to restrict transient coupling. z Minimize the path length between the TVS and the protected line. z Minimize all conductive loops including power and ground loops. z The ESD transient return path to ground should be kept as short as possible. z Never run critical signals near board edges. z Use ground planes whenever possible. 2 3 Line In Line Out 2 3 Line 2 In Line 2 Out Line 1 In Line 1 Out Differential Mode Protection (SLVE2.8 only) 2 3 2 3 SLVG2.8 SLVE2.8 Applications Information

5© 2003 Semtech Corp. www.semtech.com PROTECTION PRODUCTS SLVE2.8 and SLVG2.8 Applications Information (continued) IPP ISB IPT IR VRWM VV PT VC VBRR IBRR SB EPD TVS IV Characteristic Curve EPD TVS™ Characteristics The SLV series is constructed using Semtech’s propri- etary EPD technology. The structure of the EPD TVS is vastly different from the traditional pn-junction devices. At voltages below 5V, high leakage current and junction capacitance render conventional avalanche technology impractical for most applications. However, by utilizing the EPD technology, the SLVE2.8 and SLVG2.8 can effectively operate at 2.8V while maintaining excellent electrical characteristics. The EPD TVS employs a complex nppn structure in contrast to the pn structure normally found in tradi- tional silicon-avalanche TVS diodes. The EPD mecha- nism is achieved by engineering the center region of the device such that the reverse biased junction does not avalanche, but will “punch-through” to a conduct- ing state. This structure results in a device with supe- rior dc electrical parameters at low voltages while maintaining the capability to absorb high transient currents. The IV characteristic curve of the EPD device is shown in Figure 1. The device represents a high impedance to the circuit up to the working voltage (V RWM). During a transient event, the device will begin to conduct as it is biased in the reverse direction. When the punch- through voltage (V PT) is exceeded, the device enters a low impedance state, diverting the transient current away from the protected circuit. When the device is conducting current, it will exhibit a slight “snap-back” or negative resistance characteristic due to its structure. This must be considered when connecting the device to a power supply rail. To return to a non-conducting state, the current through the device must fall below the snap-back current (approximately < 50mA).

6© 2003 Semtech Corp. www.semtech.com PROTECTION PRODUCTSPROTECTION PRODUCTS SLVE2.8 and SLVG2.8 Land Pattern - SOT-143 Notes: (1) Controlling dimension: Millimeters. (2) Dimension A and B do not include mold protrusions. Mold protrusions are .006” max. Outline Drawing - SOT-143

200 Flynn Road, Camarillo, CA 93012

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Ordering Information

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Product Information

SLVE2.8 specifications and overview.

Summary

EPD TVS??Diodes For ESD and Latch-Up Protection

Description

The SLV series of transient voltage suppressors are designed to protect low voltage, state-of-the-art CMOS semiconductors from transients caused by electrostatic discharge (ESD), cable discharge events (CDE), lightning and other induced voltage surges.

Source title SLVE2.8 Datasheet(PDF) - Semtech Corporation

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