Power Management

SLPA005

Texas Instruments

Digital Control Compatible Synchronous-Buck Gate Driver With Current Sense and Fault Protection MAY 2011

Manufacturer: Texas Instruments

Document: 34 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse S parts

Online Datasheet

Read SLPA005 online.

UCD7232 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 34

Technical content

www.ti.com SLUSAH3 –MAY 2011 DigitalControlCompatible Synchronous-Buck Gate Driver With CurrentSense and FaultProtection Check forSamples: UCD7232 1FEATURES DESCRIPTION• Dual High CurrentDrivers. The UCD7232 high currentdriveris specifically• FullCompatibilitywithTIFusion DigitalPower designed for digitally-controlled,point-of-load,Supply Controllers,such as UCD91xx and synchronous buck switchingpower supplies.TwoUCD92xx Families drivercircuitsprovidehigh charge and discharge

Operationalto2 MHz SwitchingFrequency currentfor the high-sideNMOS switch and the low-side NMOS synchronous rectifierin a• High-SideFET and Output CurrentLimit synchronous buck circuit.The MOSFET gates areProtectionwithIndependentlyAdjustable drivenby an internallyregulatedVGG supply.TheThresholds internalVGG regulatorcan be disabledto permitthe
FastHigh-SideOvercurrentSense Circuitwith user to supply theirown gate drivevoltage.This FaultFlagOutput – PreventsCatastrophic flexibilityallows a wide power conversioninput CurrentLevelson a Cycle-by-CycleBasis voltagerange of 2.2 to 15 V. Internalunder voltage lockout(UVLO) logicinsuresVGG is good before• DifferentialHigh-GainCurrentSense Amplifier allowingchipoperation.• VoltageProportionaltoLoad CurrentMonitor A drivelogicblockallowsoperationin one of twoOutput preventcrossconduction.The SynchronousRectifier• Onboard RegulatedSuppliesforGate Drive Enable(SRE) pincontrolswhetherornotthelow-sideand InternalCircuits FET isturnedon when the PWM signalislow.In• IntegratedThermal Shutdown IndependentMode, the PWM and SRE pinscontrol• SelectableOperationModes: the high-sideand low-side gates directly.No anti-cross-conductionlogicisused inthismode.– PWM plusSynchronous RectifierEnable (SRE) withAutomatic Dead-Time Control On-boardcomparatorsmonitorthevoltageacrossthe – DirectHigh-Gateand Low-Gate Inputsfor highsideswitchand the voltageacrossan external DirectFET Control currentsense elementtosafeguardthepower stage fromsudden highcurrentloads.Blankingdelayisset• 3-StatePWM InputforPower Stage Shutdown forthe high sidecomparatorby a singleresistorin• UVLO Housekeeping Circuit ordertoavoidfalsereportscoincidentwithswitching
Rated from –40°C to+125°C Junction edge noise.In the event of a high-sidefaultor an Temperature over-currentfault,the high-sideFET turnedoffand the FaultFlag (FLT) isassertedto alertthe digital controller.The faultthresholdsare independentlysetAPPLICATIONS by theHS Sense and ILIMpins.• Digitally-ControlledSynchronous-Buck Power Output currentis measured and monitored by aStages forSingle-and Multi-Phase precision,high gain,switchedcapacitordifferentialApplications amplifierthatprocessesthe voltagepresentacross• Digitally-ControlledPower Modules an externalcurrentsense element.The amplified signalisavailableforuse by thedigitalcontrolleron the IMON pin.The currentsense amplifierhas output offsetof 0.5 V so thatboth positive(sourcing)and negative(sinking)currentcan be sensed. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

G = 50 UCD7232 0.5 V HS Fault OC FaultTSD PP PAD UCD7232 SLUSAH3 –MAY 2011 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. DESCRIPTION (CONTINUED) An on-chiptemperaturesense monitorsthedietemperature.Ifitexceeds approximately165°C, thetemperature sensorwillinitiatea thermalshutdown thathaltsoutputswitchingand setstheFLT flag.The temperaturefault automaticallyclearswhen thedietemperaturesfallsby approximately20°. FUNCTIONAL BLOCK DIAGRAM Figure1. UCD7232 Block Diagram

2 Copyright© 2011,Texas InstrumentsIncorporated

(QFN - RTJ) (4x4, 0.50) 6 7 8 9 10 20 19 18 17 16 HS Sense FLT SRE Mode SRE ILIM LS Gate PGND VGG DIS AGND RDLY IMO N CSN CSP BP3 PWM SW HS Gate BST VGG Vin UCD7232 www.ti.com SLUSAH3 –MAY 2011 SIMPLIFIED APPLICATION DIAGRAM Figure2. TypicalSynchronous Buck Power Stage CONNECTION DIAGRAM

ORDERING INFORMATION

TEMPERATURE RANGE PACKAGE TAPE AND REEL QTY PART NUMBER

250 UCD7232RTJT

–40°C to+125°C PlasticQFN-20 (RTJ)

2500 UCD7232RTJR

SLUSAH3 –MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE PARAMETER UNIT MIN MAX Supplyvoltage,VIN –0.3 16 V VBST DC –0.3 23 VBST Pulse(VSW at20V < 400ns) –0.3 27 Bootstrapvoltage V VBST Pulse(VSW at22V < 64ns) –0.3 29 VBST Pulse(VSW at30V < 16ns) –0.3 37 Gate drivesupplyvoltage VGG (Externallysupplied) –0.3 7 V HS Gate – SW –0.3 7 Outputgatedrivevoltage V LS Gate PGND – 0.3 VGG +0.3 VSW DC –1 16 VSW Pulse< 400 ns,E = 20 µJ –2 20 Switchnode voltage V VSW Pulse< 64 ns –5 22 VSW Pulse< 16 ns –10 30 CSP, CSN, RDLY –0.3 5.6 Analoginputs ILIM –0.3 3.6 V HS Sense –0.3 16 PWM, SRE, SRE Mode –0.3 5.6 Digitalinputs V VGG DIS –0.3 3.6 Analogoutputs IMON –0.3 3.6 V Digitaloutputs FLT –0.3 3.6 V Human body model 2000 ESD Rating V Charged devicemodel 500 Operatingambienttemperature,TA –40 125 °C Operatingjunctiontemperature,TJ –40 150 °C Storagetemperature,TSTG –65 150 °C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionbeyond thoseindicatedisnotimplied.Exposureto absolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.AllvoltagesarewithrespecttoAGND. Currents arepositiveinto,negativeoutofthespecifiedterminal.Consultcompany packaginginformationforthermallimitationsand considerationsofpackages. THERMAL INFORMATION UCD7232 THERMAL METRIC (1) UNITS RTJ (20PINS) θJA Junction-to-ambientthermalresistance 38.2 θJCtop Junction-to-case(top)thermalresistance 34.4 θJB Junction-to-boardthermalresistance 15.7 °C/W ψJT Junction-to-topcharacterizationparameter 0.4 ψJB Junction-to-boardcharacterizationparameter 15.7 θJCbot Junction-to-case(bottom)thermalresistance 5.9 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 .

4 Copyright© 2011,Texas InstrumentsIncorporated

www.ti.com SLUSAH3 –MAY 2011 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT VIN Power InputVoltage(InternallygeneratedVGG ) 4.7 12 15 V VIN Power InputVoltage(ExternallysuppliedVGG ) 2.2 – 15 V VGG Externallysuppliedgatedrivevoltage 4.6 6 6.5 V TJ Operatingjunctiontemperaturerange –40 – 125 °C

ELECTRICAL CHARACTERISTICS

VIN = 12V,4.7µF fromVGG toPGND, 1 µF fromBP3 toAGND, 0.22µF fromBST toSW, TA = TJ = –40°C to125°C, RDLY = 8.06kΩ,SRE Mode = 3.3V,VGG DIS tiedtoAGND (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY SECTION Supplycurrent Outputsnotswitching,VIN = 5 V,PWM = LOW 8 10 mA Supplycurrent Outputsnotswitching,VIN = 15 V,PWM = LOW 8 10 mA GATE DRIVE UNDER-VOLTAGE LOCKOUT VGG UVLO OFF VGG rising 4.4 4.6 V VGG UVLO ON VGG falling 4.1 4.3 V VGG UVLO hysteresis 80 mV VGG SUPPLY GENERATOR VIN ≥ 7 V,I_VGG ≤ 100 mA 5 V VGG VIN = 12 V,I_VGG ≤ 80 mA 5.6 6.2 6.8 V Dropout VIN = 4.75V,I_VGG ≤ 100 mA 350 mV DIGITAL INPUT SIGNALS (PWM, SRE) VIH_PWM Positive-goinginputthresholdvoltage 1.8 2 V VIL_PWM Negative-goinginputthresholdvoltage 0.80 0.90 V PWM Inputvoltagehysteresis,(VIH – VIL) 0.90 V VIH_SRE Positive-goinginputthresholdvoltage 1.5 1.7 V VIL_SRE Negative-goinginputthresholdvoltage 0.9 1.00 V SRE Inputvoltagehysteresis,(VIH – VIL) 0.45 V VPWM = 5 V 140 IPWM Inputcurrent VPWM = 3.3V 70 µA VPWM = 0 V –63 VSRE = 5 V 190 ISRE Inputcurrent VSRE = 3.3V 12 µA VSRE = 0 V –330 VPWM transitionfrom0 V to1.65V,tHLD_R 3-statehold-offtime(1) 450 600 750 nsTime untilVLS Gate fallsto0 V VPWM transitionfrom1.65V to0 V,tHLD_R 3-staterecoverytime(1) 150 330 500 nsTime untilVLS Gate risestoVGG PWM minimum pulsetoforceHS gatetmin C L = 3 nF atHS gate,VPWM = 3.3V 50 nspulse(1) PWM frequency(1) Qg HS + Qg LS < 46 nC, VGG = 6.4V 2 MHz OUTPUT CURRENT LIMIT(ILIM) ILIMInputimpedance(1) 250 kΩ ILIMsetpointrange(1) 0.5 3 V FLT outputhighlevel ILOAD = –2 mA 2.7 3.3 V FLT outputlowlevel(1) ILOAD = 2 mA 0.1 0.6 V V(ILIM)= 1.50V,(CSP – CSN) = 20 mV,Faultdetectiontime.DelayuntilHS GatetFAULT_HS 100 150 nsfalling.(1) CSN = 1.80V V(ILIM)= 1.50V,(CSP – CSN) = 20 mV,Faultdetectiontime.DelayuntilLS GatetFAULT_LS 150 200 nsrising.(1) CSN = 1.80V (1) As designedand characterized.Not 100% testedinproduction. Copyright© 2011,Texas InstrumentsIncorporated 5

SLUSAH3 –MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 12V,4.7µF fromVGG toPGND, 1 µF fromBP3 toAGND, 0.22µF fromBST toSW, TA = TJ = –40°C to125°C, RDLY = 8.06kΩ,SRE Mode = 3.3V,VGG DIS tiedtoAGND (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(ILIM)= 1.50V,(CSP – CSN) = 20 mV,Faultdetectiontime.DelayuntilFLTtFAULT_FLT 85 170 nsasserted(2) CSN = 1.80V PWM fallingtoFLT fallingaftera currentlimiteventisPropagationdelayfromPWM toresetFLT (2) 85 200 nscleared.PWM pulsewidth≥100 ns. CURRENT SENSE BLANKING (RDLY, HS Sense) IRDLY RDLY sourcecurrent 8.06kΩ resistorfromRDLY toAGND 80 90 100 µA RDLY resistancerange(2) 7.5 8.06 10 kΩ RDLY = 8.06kΩ.From SW risingtoHS faultcomparatortBLANK HS blankingtime 110 125 140 nsenabled IHS Sense HS Sense sinkcurrent R HS Sense = 2.kΩ toVIN,VIN = 12 V 100 µA HS faultdetectiontime.DelayaftertBLANK RDLY = 8.06kΩ,R HS Sense = 2 kΩ toVIN,VIN = 12 V,tHSFAULT_HS 20 nsuntilHS Gate falling(2) VIN – VSW = 220 mV HS faultdetectiontime.DelayaftertBLANK RDLY = 8.06kΩ,R HS Sense = 2 kΩ toVIN,VIN = 12 V,tHSFAULT_LS 30 nsuntilLS Gate falling(2) VIN – VSW = 220 mV CURRENT SENSE AMPLIFER (IMON ,CSP, CSN) V(IMON )atno load CSP = CSN = 1.8V 460 500 540 mV ClosedloopDC gain CSP – CSN = 10 mV; 0.5V ≤ CSN ≤ 3.3V 48 50.2 52.4 V/V Gain with2.49kresistorsinserieswithCSP, CSN 45.6 47.8 49.9 V/V Inputimpedance(2) Differential,CSP – CSN 100 kΩ VCM Inputcommon mode voltagerange(2) VCM (max)islimitedto(VGG – 1.2V) –0.3 5.6 V V(IMON )MIN CSP = 1.2V;CSN = 1.3V;I(IMON )= –250 µA 0.1 0.15 V V(IMON )MAX CSP = 1.3V;CSN = 1.2V;I(IMON )= 500 µA 3 3.2 3.3 V SamplingRate(2) 5 Msps LOW-SIDE OUTPUT DRIVER (LS Gate) Peak SourceCurrent(2) VGG = 6.2V,PWM = Low, LS Gate = 3 V 6 A Peak SinkCurrent(2) VGG = 6.2V,PWM = High,LS Gate = 3 V 6 A tRL RiseTime(2) C L = 6 nF,VIN = 12 V,VGG = 6.2V 30 ns tFL FallTime(2) C L = 6 nF,VIN = 12 V,VGG = 6.2V 20 ns OutputwithVGG <UVLO (2) VGG = 1 V,Isink= 10 mA 0 0.5 V PropagationDelayfromPWM toLS Gate(2) C L = 3 nF,PWM fallingSW = 0 V,VGG = 6.2V 46 ns HIGH-SIDE OUTPUT DRIVER (HS Gate) VIN = 12 V,BST = 6.2V,PWM = High,Sourcecurrent(2) 4 AHS Gate = 3 V VIN = 12 V,BST = 6.2V,PWM = Low,Sinkcurrent(2) 4 AHS Gate = 3 V tRH Risetime(2) C L = 3 nF HS Gate toSW, VGG = 6.2V 27 ns tFH Falltime(2) C L = 3 nF HS Gate toSW, VGG = 6.2V 21 ns C L = 3 nF HS Gate toSW, PWM rising,PropagationdelayfromPWM toHS Gate(2) 50 nsSW = 0 V,VGG = 6.2V SWITCHING TIME tDLH HS gateturn-offpropagationdelay(2) C L = 3 nF 16 ns tDLL LS gateturn-offpropagationdelay(2) C L = 3 nF 15 ns tDTH Dead timeLS;Gate offtoHS; Gate on(2) C L = 3 nF 12 ns tDTL Dead timeHS; Gate offtoLS;Gate on(2) C L = 3 nF 15 ns BOOTSTRAP DIODE VF Forwardvoltage(2) Forwardbiascurrent100 mA 0.4 V THERMAL SHUTDOWN Risingthreshold(2) 155 165 175 °C Fallingthreshold(2) 135 145 155 °C Hysteresis(2) 20 °C (2) As designedand characterized.Not 100% testedinproduction.

6 Copyright© 2011,Texas InstrumentsIncorporated

www.ti.com SLUSAH3 –MAY 2011 PIN FUNCTIONS PIN I/O FUNCTION QFN-20 NAME 1 HS Sense I High-sidecurrentfaultthresholdsetpin.A resistorisconnectedfromthispindirectlytothedrainofthe high-sideFET. The voltagedropacrossthisresistorsetsthemaximum voltagedropallowedacrossthe high-sideFET aftertheblankingtimesetby RDLY. ExceedingthisthresholdwillassertFLT and truncate theHS Gate pulse.Thispinsinksa constant100µA ofcurrent. 2 FLT O FaultFlag.The FLT signalisa 3.3vdigitaloutputwhichisassertedhighwhen an over-current, over-temperature,orUVLO faultisdetected.Afteran over-currenteventisdetected,theflagisresetlowon thefallingedge ofthenextPWM pin,providedtheover-currentconditionisno longerdetectedduringthe on-timeofthePWM signal.ForUVLO and over-temperaturefaults,theflagisresetwhen thefaultcondition isno longerpresent. 3 SRE Mode I SynchronousRectifierEnableMode selectpin.When high,thehigh-sideand low-sidegatedrivetimingis controlledby thePWM pin.Anti-cross-conductionlogicpreventssimultaneousapplicationofhigh-sideand low-sidegatedrive.When low,independentoperationofthehigh-sideand low-sidegateisselected.The high-sidegateisdirectlycontrolledby thePWM signal.The low-sidegateisdirectlycontrolledby theSRE signal.No anti-cross-conductioncircuitryisactiveinthismode. Thispinshouldnotbe leftfloating. 4 SRE I SynchronousRectifierEnableorLow-SideInput.Thispinisa digitalinputcapableofaccepting3.3Vor5V logiclevelsignals.A Schmitttriggerinputcomparatordesensitizesthispinfromexternalnoise.When SRE Mode ishigh,thissignal,when low,disablesthesynchronousrectifierFET. The LS Gate signalisheldoff. When SRE Mode ishigh,thissignal,when high,allowstheLS Gate signaltofunctionaccordingtothestate ofthePWM pin.When SRE Mode islow,thispinisa directinputtotheLS Gate driver. 5 ILIM I Outputcurrentlimitthresholdsetpin.The voltageon thispinsetsthefaultthresholdvoltageon theIMON pin. The nominalthresholdvoltagerangeis0.5V to3.0V.When V(IMON )exceedsV(ILIM),theFLT pinis assertedand theHS Gate pulseistruncated. 6 IMON O CurrentSense LinearAmplifierOutput.The outputvoltagelevelon thispinrepresentstheaverageoutput current.V(IMON )= 0.5V + 50.2(V(CSP)– V(CSN)). 7 CSN I Invertinginputoftheoutputcurrentsense amplifierand currentlimitcomparator. 8 CSP I Non-invertinginputoftheoutputcurrentsense amplifierand currentlimitcomparator. 9 BP3 O Bypass capacitorforinternal3.3Vsupply.Connecta 1µF (minimum)ceramiccapacitorfromthispinto AGND. 10 PWM I PWM input.Thispinisa digitalinputcapableofaccepting3.3V or5 V logiclevelsignals.A Schmitttrigger inputcomparatordesensitizesthispinfromexternalnoise.When SRE Mode ishigh,thispincontrolsboth gatedrivers.When SRE Mode islow,thispinonlycontrolsthehigh-sidedriver.Thispincan detectwhen theinputdrivesignalhas switchedtoa highimpedance (3-state)mode. When thehighimpedance mode is detected,boththeHS Gate and LS Gate signalsareheldlow.

11 RDLY I Requiresa resistortoAGND forsettingtheCurrentSense blankingtimeforthehigh-sidecurrentsense

comparatorand outputcurrentlimitcircuitry. 12 AGND – AnaloggroundreturnforallcircuitsexcepttheLS Gate driver. 13 VGG DIS I VGG Disablepin.When pulledhigh,theon-chipVGG linearregulatorisdisabled.When disabled,an externallysuppliedgatevoltagemust be connectedtotheVGG pin.ConnectthispintoAGND touse the on-chipregulator. 14 PGND – Power Ground pin.Thispinprovidesa returnpathforthelow-sidegatedriver. 15 LS Gate O The Low-Sidehigh-currentdriveroutput.Drivesthegateofthelow-sidesynchronousMOSFET between VGG and PGND.

16 Vin I InputVoltagetothebuck power stageand drivercircuitry

17 VGG I/O Gate Drivevoltagesupply.When VGG DIS islow,VGG isgeneratedby an on-chiplinearregulator.Nominal outputvoltageis6.2V.When VGG DIS ishigh,an externallysuppliedgatevoltagecan be appliedtothis pin.Connecta 4.7µF capacitorfromthispintoPGND. 18 BST I/O Floatingbootstrapsupplyforhighsidedriver.Connectthebootstrapcapacitorbetween thispinand theSW node.The bootstrapcapacitorprovidesthechargetoturnon thehigh-sideMOSFET. 19 HS Gate O The High-Sidehigh-currentdriveroutput.Drivesthegateofthehighsidebuck MOSFET between BST and SW. 20 SW I/O Switchingnode connectiontobuck inductor.Thispinprovidesa returnpathforthehigh-sidegatedriver. PP PAD – Power Pad.ConnectdirectlytoAGND forbetterthermalperformanceand EMI reduction. Copyright© 2011,Texas InstrumentsIncorporated 7

SLUSAH3 –MAY 2011 www.ti.com DETAILED DESCRIPTION GENERAL The UCD7232 is designed primarilyto be a synchronousbuck driverwithcurrentmeasurement and fault detectioncapabilitiesthatmake itan idealpartnerwithdigitalpower controllers.Thisdeviceincorporatestwo high-currentgatedrivestagesand sophisticatedcurrentmeasurement circuitrythatallowsforthemonitoringand reportingofoutputloadcurrent.Two separatefaultdetectionblocksprotectthepower stagefromexcessiveload currentor shortcircuits.On-chip thermalshutdown protectsthe devicein case of severe over-temperature conditions.Detectedfaultsimmediatelytruncatethe power conversioncyclein progress,withoutcontroller intervention,and asserta digitalfaultflag(FLT).Gate drivevoltageissuppliedby an on-chiplinearregulator.If desired,thisregulatorcan be disabledand an externalgatedrivevoltagecan be supplied.Mode selectionpins allowthedevicetobe used insynchronousmode orindependentmode. Insynchronousmode, thehigh-sideand low-sidegatetimingiscontrolledby a singlePWM input.Anti-cross-conductiondead-timeintervalsare applied automaticallyto the gate drives.In independentmode, the high-sideand low-sidegate drivesignalsare controlleddirectlyby the PWM and SRE pins.The automaticdead-timelogicisdisabledinthismode. When operatinginsynchronousmode, theuse ofthelow-sideFET can be disabledunderthecontroloftheSRE pin. Thisfeaturefacilitatesstart-upintoa pre-biasvoltageand isalsoused insome applicationsto reduce power consumptionatlightloads. PWM INPUT The PWM inputpin acceptsthe digitalsignalfrom the controllerthatrepresentsthe desiredhigh-sideFET on-timeduration.Thisinputisdesignedtoaccept3.3V logiclevels,butisalsotolerantof5V inputlevels.The SRE Mode pinsetsthebehaviorofthePWM pin.When theSRE Mode pinisassertedhigh,thedeviceisplaced insynchronousmode. Inthismode, thetimingdurationofthehigh-sidegatedriveand thelow-sidegatedrive are both controlledPWM inputsignal.When PWM ishigh,the high-sidegate drive(HS Gate) ison and the low-sidegatedrive(LS Gate)isoff.When PWM islow,thehigh-sidegatedriveisoffand thelow-sidegatedrive ison. Automaticanti-cross-conductionlogicmonitorsthe gate to sourcevoltageof the FETs to verifythatthe properFET isturnedoffbeforetheotherFET isturnedon.When theSRE Mode pinisassertedlow,thedevice isplacedinindependentmode. Inthismode thePWM inputonlycontrolsthehigh-sidegatedrive.When PWM is high,thehigh-sidegatedriveison.The low sideFET inindependentmode isdirectlycontrolledby theSRE pin. No anti-cross-conductionlogicisactiveinindependentmode. The user must insurethatthe PWM and SRE signalsdo notoverlap. The PWM inputsupportsa 3-statedetectionfeature.Itcan detectifthePWM inputsignalhas entereda 3-state mode. When 3-statemode isdetected,boththehigh-sideand low-sidegatedrivesignalsareheldoff.To support thismode, thePMW inputpinhas an internalpull-upresistorofapproximately50kΩ to3.3V.Italsohas a 50kΩ pull-downresistortoground.Duringnormaloperation,thePWM inputsignalswingsbelow 0.8V and above 2.5V. Ifthe source drivingthe PWM pin entersa 3-stateor high impedance state,the internalpull-up/pull-down resistorswilltendtopullthevoltageon thePWM pinto1.65V.Ifthevoltageon thePWM pinremainswithinthe 0.8V to 2.5V 3-statedetectionband forlongerthan the tHLD_R 3-statedetectionhold-offtime,then the device enters3-statemode and turnsbothgatedrivesoff.ThisbehavioroccursregardlessofthestateoftheSRE Mode and SRE pins.When exiting3-statemode, PWM shouldfirstbe assertedlow.Thiswillinsurethatthebootstrap capacitorisrechargedbeforeattemptingtoturnon thehigh-sideFET. The logicthresholdof thispin typicallyexhibits900mV of hysteresisto providenoiseimmunityand insure glitch-freeoperationofthegatedrivers. SRE INPUT The SRE (SynchronousRectifierEnable)pinisa digitalinputwithan internal10kΩ pull-upresistorto3.3V.Itis designedtoaccept3.3V logiclevels,butisalsotolerantof5V levels.The SRE Mode pinsetsthebehaviorofthe SRE pin.When theSRE Mode pinisassertedhigh,thedeviceisplacedinsynchronousmode. Inthismode, the input,when assertedhigh,enablesthe operationof the low-sidesynchronousrectifierFET. The stateof the low-sidegatedrivesignalisgovernedby thePWM input.When SRE isassertedlowwhileinsynchronousmode, the low-sideFET gate driveiscontinuouslyheldlow,keepingthe FET off.While heldoff,currentflowinthe low-sideFET isrestrictedto itsintrinsicbody diode.When the SRE Mode pinisassertedlow,the deviceis placedinindependentmode. Inthismode, thestateofthelow-sidegatedrivesignalfollowsthestateoftheSRE signal.ItiscompletelyindependentofthestateofthePWM signal.No anti-cross-conductionlogicisactivein independentmode. The usermust insurethatthePWM and SRE signalsdo notoverlap.

8 Copyright© 2011,Texas InstrumentsIncorporated

sw(max) H S LS 92000F = Qg + Qg UCD7232 www.ti.com SLUSAH3 –MAY 2011 The logicthresholdof thispin typicallyexhibits450mV of hysteresisto providenoiseimmunityand insure glitch-freeoperationofthelow-sidegatedriver. SRE MODE The SRE Mode pinisa digitalinputdesignedtoaccept3.3V logiclevels,butisalsotolerantoflevelsup to5V. Thispinsetstheoperationalmode on thedevice.When assertedhigh,thedevicewillbe placedinsynchronous mode. Inthismode thebehaviorofboththehigh-sideand low-sidegatedrivesignalsareunderthecontrolofthe PWM input.When assertedlow,thispinconfiguresthedeviceforindependentmode. Inthismode thehigh-side FET isunderthecontrolofthePWM pin.The low-sideFET isunderthecontroloftheSRE pin.The SRE Mode pinisdesignedtobe permanentlytiedhighorlow dependingon thepower architecturebeingimplemented.Itis notintendedtobe switcheddynamicallywhilethedeviceisinoperation.Thispincan be tiedtotheBP3 pinto alwaysselectsynchronousmode. VIN VIN suppliespower to the internalcircuitsof the device.The inputpower isconditionedby an internallinear regulatorthatprovidestheVGG gatedrivevoltage.A second regulatorthatoperatesoffoftheVGG railproduces an internal3.3V supplythatpowers the internalanalog and digitalfunctionalblocks.The BP3 pin provides accessfora highfrequencybypass capacitoron thisinternalrail.The VGG regulatorproducesa nominaloutput of 6.2V.The outputof the VGG regulatorismonitoredby the Under-VoltageLock-Out(UVLO) circuitry.The devicewillnot attemptto produce gate drivepulsesuntilthe VGG voltageisabove the UVLO threshold.This insuresthatthereissufficientvoltageavailabletodrivethepower FETs intosaturationwhen switchingactivity begins.To use theinternalVGG regulator,thevoltageon Vinshouldbe atleast4.7V. When performingpower conversionwithlessthan4.7V on theVIN pin,thegatedrivevoltagemust be supplied externally.(See VGG and VGG DIS sectionsfordetails.) VGG The VGG pinisthegatedrivevoltageforthehighcurrentgatedriversstages.The voltageon thispincan be suppliedinternallyby theon-chipregulator,oritcan be externallysuppliedby theuser.When usingtheinternal regulator,theVGG DIS pinshouldbe tiedlow.When an externalsourceofVGG istobe used,theVGG DIS pin must be tiedhigh.Currentisdrawn fromtheVGG supplyinfast,high-currentpulses.A 4.7µF ceramiccapacitor shouldbe connectedfromtheVGG pintothePGND pinas closeas possibletothepackage. Whether internallyor externallysupplied,the voltageon the VGG pinismonitoredby the UVLO circuitry.The voltagemust be higherthantheUVLO thresholdbeforepower conversioncan occur.Note thattheFLT pinis assertedhighwhen VGG isbelowtheUVLO threshold. The average currentdrawn from the VGG supplyisdependant on the switchingfrequencyand the totalgate chargeofthepower FETs connectedtothedriver.Thiscurrentcan be significantand isa majorcontributorto theoverallpower dissipationofthedriver.The totalgatecharge(Qg) isa functionofthevalueofVGG and the power FET construction.A valueforQg can be obtainedfromtheFET manufacturer’s datasheet.A graphofQg vs VGS isusuallysupplied.Use thevalueofVGG as theVGS valueand read thecorrespondingvalueofQg. A valueofQg shouldbe obtainedforboththehigh-sideand low-sideFETs. To keep thecurrentdraw from theVGG supplywithinitscapability,theswitchingfrequencyofthepower stage shouldbe limitedtothefollowing: (1) Where Fsw(max) isthe maximum switchingfrequencyin kHz, Qg HS isthe gate charge of the high-sideFET measured atVGS = 6.2V,and Qg LS isthetotalgatechargeofthelow-sideFET(s)measured atVGS = 6.2V,both specifiedinnanocoulombs (nC).SelectingFETs withlowergatechargewillpermithigheroperatingfrequencies. The formulaabove allowsfora maximum of92mA oftotalgatedrivecurrent.An additional8mA isconsumed by theremainingcircuitrywithinthedevice. The averagegatedrivecurrent,inmA, can be calculatedfromthefollowingequation(withswitchingfrequencyin kHz and chargeinnC): IGATE_AVE = (QgHS + Qg LS)× Fsw × 1000 (2) Copyright© 2011,Texas InstrumentsIncorporated 9

SLUSAH3 –MAY 2011 www.ti.com Assuming VGG = 6.2V and Fsw = 500kHz,a typicalQg fora low-sideFET is50nC. A typicalhigh-sideFET Qg is 13nC. Thiscombinationcreatesan IGATE_AVE of 31.5mA. Ifthe switchingfrequencywas doubled,the current draw would double to 63mA. IfVIN = 12V and the internalVGG linearregulatoris being used, the power dissipationintheVGG regulator,forthiscase,at500kHz operation,is183mW. At 1MHz, itincreasesto365mW. Keep inmind thatthisisnot the totalpower dissipationof the driver,onlythe portiondissipatedinthe VGG regulator.Good thermallayouttechniquesarerequiredforthisdevice. VGG DIS Thispin,when assertedhigh,disablestheon-chipVGG linearregulator.When tiedlow,theVGG linearregulatoris used toderiveVGG from VIN.Thispinisdesignedtobe permanentlytiedhighor low dependingon thepower architecturebeingimplemented.Itisnotintendedtobe switcheddynamicallywhilethedeviceisinoperation. SW The SW pinconnectsto the switchingnode of the power conversionstage.Itactsas the returnpath forthe high-sidegate driver.When configuredas a synchronousbuck stage,the voltageswing on SW normally traversesfrom below ground to wellabove VIN. A power Schottkydiodeshouldbe connectedfrom thispinto PGND toclamp thenegativevoltageswingon thispintolessthan1V. A series1Ω resistorconnectsthispinto the actualswitchingnode. Itactsas a currentlimitingresistorwhen the Schottkydiodeisclampingnegative voltageswings.The diodeshouldbe ratedforatleast0.5A ofcurrentand exhibita breakdown voltageofatleast 30V.Small-signalSchottkydiodesshouldnotbe used. Parasiticinductanceinthehigh-sideFET and theoutputcapacitance(Coss)ofbothpower FETs forma resonant circuitthatcan producehighfrequency(>100MHz) ringingon thisnode.The voltagepeak ofthisringing,ifnot controlled,can exceed twiceVIN.Care must be takentonotallowthepeak ringingamplitudetoexceed twicethe valueoftheinputvoltage,even ifthatvoltageamplitudeiswithintheAbsoluteMaximum ratinglimitforthepin.In many cases,a seriesresistorand capacitorsnubbernetworkconnectedfrom theswitchingnode toPGND can be helpfulindamping the ringingand decreasingthe peak amplitude.Itisrecommended thatprovisionsfor snubbernetworkcomponents be providedduringthelayoutoftheprintedcircuitboard.Iftestingrevealsthatthe ringingamplitudeattheSW pinexceedstwiceVIN,thenthesnubbercomponents need tobe populated. BST The BST pinprovidesthedrivevoltageforthehigh-sideFET. A bootstrapcapacitorisconnectedfromthispinto the SW node. Internally,a diode connectsthe BST pin to the VGG supply.In normal operation,when the high-sideFET isoffand thelow-sideFET ison,theSW node ispulledtogroundand,thus,holdsone sideofthe bootstrapcapacitoratgroundpotential.The othersideofthebootstrapcapacitorisclamped by theinternaldiode to VGG . The voltageacrossthe bootstrapcapacitorat thispointisthe magnitude of the gate drivevoltage availableto switch-onthe high-sideFET. The bootstrapcapacitorshouldbe a low ESR ceramictype,witha recommended minimum valueof0.22µF.A minimum voltageratingof16V orhigherisrecommended. HS GATE The HS Gate signaldirectlydrivesthegateofthehigh-sidepower FET. Itprovideshighcurrentdrivetocharge thegatecapacitanceoftheFET rapidlytoinsurethatitmakes thetransitionfromofftoon as quicklyas possible tominimizeswitchinglosses.When commanded on,theHS Gate isdriventotheBST pinpotential.As theFET beginstoturnon,theSW willquicklyrisetotheVIN potential.Thisvoltageswing iscoupledby thebootstrap capacitortotheBST pin.The netresultisthattheBST pinvoltage,and thustheHS Gate voltage,isalways equaltoVSW + VGG .As theFET gatecharges,thecurrentreturnpathforthedriverisprovidedby theSW pin. When theHS Gate iscommanded off,thedriverpullsthepintotheSW potential.As theFET turnsoff,theSW pinwillswing quicklytoslightlybelow ground.Once again,thisvoltageswing iscoupledtotheBST pinby the bootstrapcap.The HS Gate circuitryisreferencedto the SW pinand floatswiththe SW signalswing.The circuitryloopfromtheHS Gate pintothegateoftheFET and fromthesourceofthehigh-sideFET totheSW pinshouldkeptas smalland tightas possibletolimitstrayinductance.Likewise,theloopfromtheBST pintothe bootstrapcapacitorand back totheSW pinshouldbe keptsmalland tight.

10 Copyright© 2011,Texas InstrumentsIncorporated

L R C VoutSW CSNCSP 2.49k/c87 2.49k/c87 UCD7232 www.ti.com SLUSAH3 –MAY 2011 LS GATE The LS Gate signaldirectlydrivesthegateofthelow-sidepower FET. Itprovideshighcurrentdrivetoquickly charge the gate capacitanceof the FET, which isoftenconsiderablylargerthan the high-sideFET. When commanded on,theLS Gate isdriventotheVGG pinpotential.The currentreturnpathforthedriverisprovided by thePGND pin.When commanded off,theLS Gate pinisdriventothePGND potential.The tracesfromthe LS Gate and thePGND pinstothelow-sideFET gateand sourcepinsshouldbe shortand wide tominimize parasiticinductanceand resistance. CSP, CSN These pins are the inputto the differentialcurrentsense amplifier.The CurrentSense Positive(CSP) pin connectsto the non-invertinginput,the CurrentSense Negative(CSN) connectsto the invertinginput.This amplifierprovidesthemeans tomonitorand measure theoutputcurrentofthepower stage.The circuitrycan be used witha discrete,low value,seriescurrentsense resistor,or can make use of the popularinductorDCR sense method. The DCR method isillustratedinFigure3. A seriesresistorand capacitornetworkisadded acrossthe buck stagepower inductor.Itcan be shown thatwhen thevalueofL/DCR isequaltoRC, thenthevoltagedeveloped acrossthecapacitor,C, isa replicaofthevoltagewaveform theidealcurrentwould induceinthedc resistance (DCR) of the inductor.Thismethod does not detectchanges incurrentdue to changes ininductancevalue caused by saturationeffects.The valueused forC shouldbe in the 0.1µF to 2.2µF range.This keeps the impedance ofthesense networklow,which reducesitssusceptibilitytonoisepickupfrom theswitchingnode. The tracelengthsof the CSP and CSN signalsshouldbe keptshortand parallel.To aidinrejectionof high frequencycommon-mode noise,a series2.49kresistorshouldbe added toboththeCSP and CSN signalpaths, withthe resistorsbeing placedcloseto the pinsat the package.This smallamount of additionalresistance slightlylowersthecurrentsense gain. Power inductorsare selectedforthelowestpossibleDCR tominimizelosses.TypicalDCR valuesrange from 0.5mΩ to5m Ω.With a loadcurrentof20A, thevoltagepresentedacrosstheCSP and CSN pinsisonlyinthe rangeof10mV to100mV. Keep inmind thatthissmalldifferentialsignalisridingon a largecommon mode signal thatisthedc outputvoltage.Thismakes thecurrentsense signalchallengingtoprocess. Figure3. DCR CurrentSense The UCD7232 uses switchedcapacitortechnologytoperformthedifferentialtosingle-endedconversionofthe sensed currentsignal.Thistechniqueoffersexcellentcommon mode rejection.The differentialCSP-CSN signal isamplifiedby a factorof97.8and thena fixed500mV pedestalvoltageisadded totheresult.Thissignalis presentedtotheIMON pin. When usinginductorswithDCR valuesof2m Ω or higher,itmay be necessarytoattenuatetheinputsignalto preventsaturationofthecurrentsense amplifier.ThisiseasilyaccomplishedthroughtheadditionofresistorR2 as shown inFigure4. Copyright© 2011,Texas InstrumentsIncorporated 11

L R1 C Vout CSNCSP SW 2.49 k/c87 2.49 k/c87 OUT LOAD R2V(I ) = 0.5 + 47.8 DCR I R1 + R2 /c230 /c246/c180 /c180 /c180 /c231 /c247 /c232 /c248 UCD7232 SLUSAH3 –MAY 2011 www.ti.com Figure4. AttenuatingtheDCR Sense Signal The amount ofattenuationisequaltoR2/(R1 + R2).The equivalentresistancevaluetouse intheL/DCR = RC formulaistheparallelcombinationofR1 and R2. Thus,when usingthecircuitofFigure4, L/DCR = C × R1 × R2/(R1+ R2) (3) IMON The IMON signalis a voltageproportionalto the outputcurrentdeliveredby the power stage.The voltage magnitudeobeys thefollowingequationwhen usingthecircuitofFigure3.Thisequationtakesintoaccountthe gainreductioncaused by theseries2.49kresistors. V(IOUT )= 0.5+ 47.8× DCR × ILOAD (4) Ifthe calculatedvalueof V(IMON ) exceeds the range of the analog-to-digitalconverter(ADC) or,ifused,the maximum faultcomparatorthresholdlimitof a controllermonitoringthisvoltage,then the circuitof Figure4 shouldbe used.When usingthecircuitofFigure4,thevoltageon IMON obeys thismodifiedequation: (5) In eithercase,the outputvoltageis500mV at no load.Currentthatissourcedto the loadcauses the IMON voltageto riseabove 500mV. Currentthatis forcedintothe power stage (sinkingcurrent)is considered “negative” currentand willcause theIMON voltagetofallbelow 500mV. The usabledynamic range oftheIMON signalisapproximately100mV to3.1V.Keep inmind thatthissignalswingcouldexceed notjustthemaximum range ofan analogtodigitalconverter(ADC) thatmay be used toread or monitortheIMON signal,butalsothe maximum programmable limitforthefaultOC threshold.For example,theUCD92xx familyofdigitalcontrollers has maximum limitof2.5V fortheADC converterand 2.0V forthefaultOC threshold,even thoughtheinputpin can toleratevoltagesup to3.3V. The IMON voltageisinternallyfed to the non-invertinginputof the outputover-currentfaultcomparator.Good practicedictatesthattheover-currentthresholdshouldbe setatapproximately150% oftheratedpower stage outputcurrentplusone halfofthepeak-to-peakinductorripplecurrent.Thismandates thattheIMON signalshould remainwithinitslineardynamic rangeatthisthresholdloadcurrentlevel.Thisrequirementmay forcetheuse of the attenuationcircuitof Figure4. Note thatthe IMON voltage(thatgoes to the outputover-currentfault comparator)isheldduringtheblankingintervalsetby theresistoron theRDLY pin.Thismeans thattheIMON pin willnotreflectoutputcurrentchanges duringtheblankinginterval,and thata faultwillnotbe flaggeduntilthe blankingintervalterminates. ILIM The ILIMpinfeedstheinvertinginputoftheoutputover-currentfaultcomparator.The voltageappliedtothispin setstheover-currentfaultthreshold.When thevoltageon theIMON pinexceeds thevoltageon thispin,a faultis flagged.The voltageon thispincan be setby a voltagedivider,a DAC, orby a filteredPWM output.The usable voltagerangeoftheILIMpinisapproximately0.6Vto3.1V.ThisrepresentsthelinearrangeoftheIMON signalfor sourcedoutputcurrent.When usinga voltagedividertosetthethreshold,a (0.01µF) capacitortoBP3 can be added toimprovenoiseimmunity.

12 Copyright© 2011,Texas InstrumentsIncorporated

BLANKt - 33RDLY = 11.413 UCD7232 www.ti.com SLUSAH3 –MAY 2011 RDLY The RDLY pinsetstheblankingtimeofthehigh-sidefaultdetectioncomparator.A resistortoAGND setsthe blankingtimeaccordingtothefollowingformula,where tBLANK isinnanoseconds and RDLY isinkΩ.Valuesof RDLY ofgreaterthan25kΩ shouldnotbe used. (6) To calculatethenominalblankingtimefora givenvalueofresistance,use theformulabelow. tBLANK = 11.413× RDLY + 33 (7) The blankingintervalbeginson therisingedge ofSW. Duringtheblankingtimethehigh-sidefaultcomparatoris heldoff.A high-sidefaultisflaggedwhen thevoltagedropacrossthehigh-sideFET exceeds thethresholdset by theHS Sense pin.Blankingisrequiredbecause thehighamplituderingingthatoccurson therisingedge of SW would otherwisecause falsetriggeringofthefaultcomparator.The requiredamount ofblankingtimeisa functionofthehigh-sideFET, thePCB layout,and whetherornota snubbernetworkisbeingused.A valueof 125ns isa typicalstartingpoint.An RDLY of8.06kΩ willprovide125ns ofblanking.The blankingintervalshould be keptas shortas possible,consistentwithreliablefaultdetection.The blankingintervalsetstheminimum duty cyclepulsewidthwhere high-sidefaultdetectionispossible.When the duty cycleof the PWM pulsesare narrowerthantheblankingtime,thehigh-sidefaultdetectioncomparatorisheldofffortheentireon-timeand is, therefore,blindtoany high-sidefaults. Internally,theRDLY pinisfedby a 90µA currentsource.When usingthedefaultvalueof8.06kΩ,thevoltage observedon theRDLY pinwillbe approximately725mV. HS SENSE A resistorfrom theHS Sense pintothedrainofthehigh-sideFET setsthehigh-sidefaultdetectionthreshold. When the high-sideFET ison, the currentflowinthe FET producesa voltagedrop acrossthe device.The magnitude of thisvoltageisequal to the R DS(ON) timesthe currentthroughthe FET. An absolutemaximum currentlevelcan be setduringthedesignstageand theresultantvoltagedropacrosstheFET can be calculated. Thismaximum voltagedrop,ΔVMAX ,setsthehigh-sidefaultthreshold. Internally,a highspeed comparatormonitorsthevoltagebetween theSW pinand theHS Sense pinwhen the high-sideFET ison.Whenever thevoltageon theSW pinislowerthanthevoltageon theHS Sense pin,a fault isflagged.To preventfalsetrippingduringtheringingthataccompaniestherisingedge ofSW, theoutputofthe comparatorisheldoff(blanked)fora timeintervalsetby theRDLY pin.The voltageon theHS Sense pinisset by a resistorconnectedfromthepintothehigh-sideFET drain.The HS Sense resistorvalueiscalculatedfrom thefollowingformula,where ΔVMAX isinmV, and R HS Sense isinkilohms. R HS Sense = ΔVMAX /100 (8) Forexample,ifΔVMAX is100mV, thenR HS Sense is1kΩ. The equationcan be restatedas follows,withR HS Sense inkilohms,R DS(ON) inmilliohms,and IMAX inamps: R HS Sense = R DS(ON)HOT × IMAX )/100 (9) The valueof IMAX shouldbe setto approximately150% of the expectedmaximum steady-statecurrent.This allowssome headroom to avoidnuisancefaulteventsdue to transientload currentsand the inductorripple current.Also,keep in mind thatthe R DS(ON) of a FET has a largepositivetemperaturecoefficientof approximately4000ppm/°C. The junctiontemperatureof the FET willbe elevatedwhen operatingat currents neartheIMAX threshold.Intheequationabove,use a valueofR DS(ON)HOT thatisapproximately140% ofitstypical room temperaturevalue.When usingtheinternalVGG gatedrivesupply,theFET, when turnedon,isdriventoa VGS enhancement voltageofapproximately6V. Most FET datasheetsprovideR DS(ON) valuesforVGS valuesof 4.5V and 10V. Do notuse theVGS = 10V valuefortheroom temperatureR DS(ON) value.Some manufacturers providea graphofR DS(ON) vs VGS .Ifprovided,use theVGS = 6V valuefortheroom temperatureR DS(ON) value. A 100µA currentsinkpullscurrentthroughR HS Sense.Thissetsup a referencevoltagedropequaltoΔVMAX .Itis importanttoconnectthefarend oftheR HS Sense resistordirectlytothedrainofthehigh-sideFET. Thisshouldbe made witha separate,non-current-carryingtrace.ThisinsuresthatonlytheR DS(ON) oftheFET influencesthe faultthresholdand nottheresistanceofthepc boardtraces. Copyright© 2011,Texas InstrumentsIncorporated 13

Fault□Detected UCD7232 SLUSAH3 –MAY 2011 www.ti.com FLT The FaultFlag(FLT)isa digitaloutputpinthatisassertedwhen a significantfaultisdetected.Itismeant toalert the host controllerto an event thathas interruptedpower conversion.The FLT pin is held low in normal operation.When a faultisdetecteditisassertedhigh(3.3V).There are foureventsthatcan triggerthe FLT signal:outputover-current,high-sideover-current,UVLO and thermalshutdown.The operationof the device duringfaultconditionsisdescribedintheFaultBehaviorsection.When assertedinresponsetoan over-current fault,the FLT signalisresetlow upon the fallingedge of a subsequentPWM pulse,providedno faultsare detectedduringtheon-timeofthepulse.Ifthefaultisstillpresent,theflagwillremainasserted.When asserted inresponseto an UVLO or thermalshutdown event,the FLT pinwillautomaticallyde-assertitselfwhen the UVLO or thermaleventhas passed.Iftheon-timeofthePWM pulseislessthan100ns,thenmore thanone pulsemay be requiredtoresettheflag. BP3 The BP3 pinprovidesa connectionpointfora bypasscapacitorthatquietstheinternal3.3Vvoltagerail.Connect a 1µF (orgreater)ceramiccapacitorfrom thispintoanalogground.Do notdraw currentfrom thispin.Itisnot intendedtobe a significantsourceof3.3V.Itcan,however,be used toas a sourceof3.3V foran ILIMvoltage dividerand a tiepointfortheSRE Mode pin.Currentdraw shouldbe limitedto100µA orless. FAULT BEHAVIOR When faultsare detected,thedevicereactsimmediatelytominimizepower dissipationintheFETs and protect thesystem.The typeoffaultinfluencesthebehaviorofthegatedrivesignals. When a thermalshutdown faultoccurs,bothHS Gate and LS Gate are immediatelyforcedlow.They willstay low,regardlessofthestateofPWM and SRE, forthedurationofthethermalshutdown. A UVLO faultoccurswhen thevoltageon theVGG pinislessthantheUVLO threshold.Duringthistimeboththe HS Gate and LS Gate aredrivenlow,regardlessofthestateofPWM and SRE. The faultisautomaticallycleared when theVGG voltagerisesabove theUVLO threshold. When eithera high-sidefaultor an outputover-currentfaultisdetected,theFLT pinisassertedhigh,and both gatesignalsareimmediatelypulledlow.Duringa high-sidefault,a high-sidegatepulsewillbe issuedwitheach incomingPWM pulse.Ifthe faultisstillpresent,the HS Gate signalwillagain be truncated.This behavior repeatson a cycle-by-cyclebasisuntilthefaultisgone orthePWM inputisheldlow.Thisbehaviorisillustrated inFigure5. Figure5. High-SideOver-CurrentFaultResponse When a high-sidefaultand outputover-currentfaultare detectedconcurrently,then both FET drivesare immediatelyturnedoffand heldoff.Iftheoutputover-currentfaultisstillpresentatthenextPWM risingedge, then no HS Gate pulsewillbe issuedand both gateswillcontinueto be heldoff.Unlikethe high-sidefault detectioncircuitry,theoutputover-currentfaultcircuitryisnotreseton a cycle-by-cyclebasis.The outputcurrent must fallbelowtheover-currentthresholdbeforeswitchingwillresume.

14 Copyright© 2011,Texas InstrumentsIncorporated

Fault□Detected Fault□Still□Present No□fault□present□during entire□PWM□high interval. FLT□reset□on PWM□falling□edge UCD7232 www.ti.com SLUSAH3 –MAY 2011 FLT RESET With the exceptionof a UVLO faultor a thermalshutdown fault,the FLT flag,once asserted,isclearedby subsequentPWM pulses.The FLT flagwillbe clearedon thefallingedge ofthenextPWM pulse,provideda faultconditionisnotassertedduringtheentireon-timeofthePWM pulse.Ifa faultispresentordetectedduring theon-timeinterval,theFLT pinwillremainasserted.ThisbehaviorisillustratedinFigure6. Figure6. FLT Reset Sequence Whenever thevoltageon theVGG pinisbelow theUVLO fallingthreshold,as atthetimeofinitialpower-up,for example,theFLT pinwillbe asserted.When thevoltageon theVGG pinrisesabove theUVLO risingthreshold, theFLT pinwillbe clearedautomatically.ThispermitstheFLT pintobe used as a “Power Not Good ” signalat initialpower-uptosignifythatthereisinsufficientgatedrivevoltageavailabletopermitproperpower conversion. When FLT goes low,itisan indicationof“Gate DrivePower Good ” and power conversioncan commence. After initialpower-up,theassertionoftheFLT flagshouldbe interpretedthatpower conversionhas stoppedor has been limitedby a faultcondition. THERMAL SHUTDOWN Ifthejunctiontemperatureexceeds approximately165°C, thedevicewillenterthermalshutdown.Thiswillassert theFLT pinand bothgatedriverswillbe turnedoff.When thejunctiontemperaturecoolsby approximately20°C, thedevicewillexitthermalshutdown.The FLT flagisresetupon exitingthermalshutdown. Gate drivertemperaturewillbe stronglyinfluencedby theswitchingfrequencybeingused,thevalueofVIN and VGG , and the totalcapacitiveloadon the HS Gate and LS Gate pins.The driverjunctiontemperatureisnot normallystronglyaffectedby loadcurrent.However,a riseinthePCB substratetemperaturedue toloadcurrent inducedpower dissipationinnearbycomponents willraisethejunctiontemperatureand contributetoa possible thermalshutdownevent. Copyright© 2011,Texas InstrumentsIncorporated 15

(6V - 14V) From controller To controller Vout GND HS Sense BST HS Gate SW VGG LS Gate PGND CSP CSN AGND Vin V DISGG SRE Mode RDLY ILIM BP3 IMON FLT SRE PWM UCD7232 PP PAD 1/c109H, 1.2m/c87 CSD16322Q5 CSD16401Q5 768/c87 0.22/c109F Opt 47/c109F47/c109F 330/c109F 4.7uF 22/c109F 22/c109F 3.01/c87 0.5W 2200pF 8.06k/c87 10.0k/c87 31.6k/c871/c109F 0.1/c109F 1/c109F C11 R2 C7 C8 C9 C12 2.49k/c87 2.49k/c87 R10 0 /c87 (Opt) 0/c87 (Opt) R11 1 /c87 B0540W R12 1.65k/c87 UCD7232 SLUSAH3 –MAY 2011 www.ti.com

APPLICATION INFORMATION

A partialschematicofa 20A power conversionstagedesignedfor500kHz operationisshown inFigure7. Figure7. Example 20A Power Stage Thispower stagehas been designedtooperatewitha nominalinputvoltageof12V.Itwillperformwellwithinput voltagesfrom6V to14V.The outputvoltagerangeisassumed tobe 3.3Vorlower.Ithas been configuredtouse the internalVGG supply and operate strictlyin synchronous mode. The controllerand voltagefeedback components arenotshown.Thisdesignworkswellwithany oftheUCD92xx familyofDigitalPower Controllers. The firststep in designingthe power stage is selectinga nominal operatingfrequency.Lower switching frequencieswillreduceFET switchinglossesand drivergatecurrents,butwillrequirehigherinductorvaluesto keep inductorripplecurrentwithinreasonablevalues.Higherswitchingfrequenciesallowforsmallerinductor values,whichlikelyreducestheirphysicalsizeand DCR, buthigherFET switchinglossesand gatedrivepower may offsettheefficiencygainsachievedfromreducedinductorDCR. 500kHz isa good startingpointforpower stagesinthe15A to25A range. INDUCTOR SELECTION Once a switchingfrequencyhas been selected,an appropriateinductancevaluecan now be selected.Ripple currentand saturationcurrentare thetwo key parametersthatdriveinductorvalueselection.Ripplecurrentis theac variationofthecurrentthroughtheinductor.Itissuperimposedon theaveragedc (load)currentflowing throughtheinductor.High valuesofripplecurrentcause increasedcorelossesintheinductor,and requiremore low ESR capacitancetokeep theoutputripplevoltagetoacceptablelevels.Limittheinductorripplecurrentto approximately30% oftherateddc loadcurrent.The peak-to-peakripplecurrentinan inductordeterminedby the voltageacrosstheinductor,thetimedurationofthatappliedvoltage,and thevalueoftheinductor. ΔIPP = VL × Δt/L (10) In a switchingregulator,thisequationcan be rewrittento use the duty-cycleand switchingfrequencyof the high-sideFET tocalculatetheripplecurrent. ΔIPP = [(VIN – VOUT )× VOUT ]/(VIN × FSW × L) (11)

16 Copyright© 2011,Texas InstrumentsIncorporated

www.ti.com SLUSAH3 –MAY 2011 For a synchronousbuck regulator,theripplecurrentishighestat50% dutycycle,or when Vout isone halfof Vin.Athigherorlowerdutycycles,theripplecurrentdecreases. For thisdesign,themaximum outputcurrentistargetedtobe 20A. Ifthe30% ripplecurrentruleisapplied,the maximum allowableripplecurrentis6APP .The previousequationcan be rearrangedtouse thisvaluetocompute a minimum inductancevaluethatwillmeet ourcriteria. LMIN = [(VIN – VOUT )× VOUT ]/(VIN × FSW × ΔIMAX ) (12) For thisdesign,themaximum rippleoccurswhen Vin= 14V and Vout isatthehighesttargetedoutputvoltageof 3.3V.Thisproducesa valueforLMIN of0.84µH. Thisvalueisroundedup to1µH, whichisa popularvaluethatis availablefrominductorvendors. Now thattheinductancevaluehas been determined,thecurrenthandlingcapacityoftheinductordrivesthenext stepintheselectionprocess.The inductorsaturationlimitand DCR heatinglimitaretwo key parameters.At full load,thepeak currentintheinductorisequaltotheloadcurrentplusone halfoftheΔIPP value.For thisdesign, thepeak inductorcurrentisapproximately23A. The inductormust have a saturationcurrentrating,ISAT ,ofat least23A. The inductorsaturationratingisthecurrentlevelatwhich theinductancevaluefallsby 20 or 30% (dependingon thevendor)from itsno-loadvalue.As currentincreasesabove thisvalue,theinductancevalue may fallsharply,dependingon thecorematerialand constructionoftheinductor.Operatingan inductorinits saturatedregioncauses thecurrentthroughittoincreaserapidly,causingpotentiallydamaging levelsofcurrent toflowinthehigh-sideFET. Good engineeringpracticedictatesthattherebe shouldbe 15% ormore headroom in the inductorsaturationlimitto allowfortransientcurrentsand surges thatwillbe encounteredin normal operation.Forthisdesign,an ISAT ratingofatleast1.15× 23A = 26.5Awouldbe required. For highestefficiency,an inductorwiththe lowestDCR willalways have the lowestI2R losses.However, low resistancerequireswirewitha largecrosssection.Thisforcestheinductortobe physicallylargerthana higher DCR device.The DCR oftheinductorwilllimititscurrenthandlingcapacitydue totheheatingitwillcause when currentflowsthroughit.Inductormanufacturerstypicallygivea maximum currentratingforan inductorbased on the currentthatproduces a 40°C risein the devicetemperature.Keep in mind thatin an 85°C ambient environment,a 40°C risewillresultina devicetemperatureof125°C. Everyinductorhas two maximum current ratings:one isthe 40°C riserating,the otheristhe ISAT rating.The maximum usablecurrentratingforthe inductoris the lower of the two values.In a welldesigned inductor,the 40°C riseratingand ISAT are approximatelyequal.The 40°C riseratingshouldbe atleastequaltothemaximum steadystateloadcurrentof thepower stage.Headroom above thesteadystate40°C riseratingisnotrequired.Momentary surgecurrents above theratingvaluewillnotcause a significanttemperaturerisedue tothethermalmass ofthepart. The lastkey inductorconsiderationisthechoiceofcorematerial.Core materialaffectscost,power dissipation due tocoreloss,and saturationcharacteristics.There arethreepopularcorematerialsused inpower inductors: powdered iron,ferrite,and powdered alloy.Powder ironisinexpensiveand has a desirablesoftsaturation characteristicthatmakes ittolerantofsurgeand transientcurrents.However,athighvaluesofripplecurrentand higherswitchingfrequencies(500kHzand up),corelossesbecome quitelarge.The heatingdue tocorelossisin additiontotheI2R heatingdue tothewindingDCR. Excessivecorelosscan cause thecoretemperaturetorise dramatically.Insome cases,thiscan leadtopermanentdegradationofthecore.Powdered ironcoresarebest used atswitchingfrequenciesatorbelow 350kHz.Ferritehas thelowestcorelosses,making itidealforhigher switchingfrequencies.Ferritesaturateseasily,so ferritebased inductorsareproducedwithsome formofairgap thatlowerstheireffectivepermeabilityand extends theirsaturationlimit.However, once the core reaches saturation,thefalloffininductanceisquitesteep.Thisdictatestheselectionofa devicethathas some extraISAT headroom to allowfortransientcurrentsurges.Ferriteisalsothe most costlycore material.Powdered alloy coresare an improvedversionofpowdered ironcores.By usingmore exoticmetalmixturesinthecore,alloy coresexhibitlowercorelossathighfrequenciesand ripplecurrentscompared topowered iron.Insome cases, they approach the performance of ferrite.The powdered alloycores retainthe desirablesoftsaturation characteristicofpowdered ironcores.Costwise,powdered alloyusuallyfallsbetween powdered ironand ferrite. Now thatthekey inductorrequirementsareknown, a devicecan be selected.Inthisdesign,a BI Technologies HM00-08822LFTR device,forexample,meets therequirements.Thisisa 0.95µH device,with1.2mΩ DCR. It uses a ferritecorewithan ISAT ratingof29A. Copyright© 2011,Texas InstrumentsIncorporated 17

SLUSAH3 –MAY 2011 www.ti.com CALCULATING THE DCR CURRENT SENSE COMPONENTS Withan inductorselected,thenextstepistocalculatethevalueoftheDCR currentsensingcomponents.While theinductorhas a nominalroom temperatureresistanceof1.2mΩ,when inuse,thewindingtemperaturewillbe elevated.Copper has a positivetemperaturecoefficientof3800ppm/°C. Ifwe assume a typicaltemperaturerise of20°,thenthewindingresistancewillincreaseby 7.6% toapproximately1.3mΩ.ThisDCR valuewillbe used in thefollowingcalculations. With20A ofloadcurrentthroughtheinductor,thevoltagedropdue totheDCR willbe 1.3× 20 = 26mV. Thiswill be amplifiedby a factorof48 by thecurrentsense amplifierwithintheUCD7232. Thiswillboostthesignalto 1.25V.The internalcircuitrythenadds a 0.5V pedestaltotheamplifiedsignalwhichresultsin1.75V attheIMON pin.Thisvoltageiswithinthe2.0V dynamic rangeofthecurrentmeasurement and faultdetectioncircuitryofthe controller,so thedesigncan make use ofthecurrentsense networkshown inFigure3.No attenuationofthe signalisnecessary.R2 inFigure7 isnotrequiredand does nothave tobe loaded.(Ifa higherDCR inductor were selected,attenuationof the currentsense signalmight be required,and, in thatcase, R2 would be populated.) The valuesforthe currentsense RC network(R1 and C6) around the inductorcan now be calculated.The requirementisL/DCR = RC. Let C = 1µF. Using 1µH forL and the warm DCR valueof 1.3mΩ forDCR, the calculatedvalueforR is769Ω.The neareststandard1% valueis768Ω.Thus,C6 = 1µF and R1 = 768Ω. The CSP and CSN pinsaresensitivetonoisepickup.Signaltracestothesepinsshouldbe keptshortand away from the switchingnode and the gate drivetraces.They shouldbe shieldedby ground planesand adjacent groundfingersifpossible.Series2.49kΩ resistorsR3 and R4 areadded closetotheCSP and CSN pinstohelp attenuatenoise.Furtherreductioninnoisecan be achievedby placingthecurrentsense capacitor,C6, closeto R3 and R4. FET SELECTION At a minimum, theFETs used inthepower stagemust have a VDS breakdown ratingofatleast1.5timesthe maximum inputvoltage.Thisheadroom isrequiredsincethepeak voltageon theswitchingnode isalwayshigher thantheinputvoltagedue toringingcaused by energystorageintheparasiticinductanceoftheFETs and the PCB traces.Withgood layoutpracticesand theuse ofa snubbernetwork,thepeak voltageon theFETs can be limitedto1.5timesVin.Inthisexample,a minimum VDS ratingof21V isrequiredtoaccommodate a 14V input voltage. The high-sideFET shouldbe selectedtohandlecurrentpulsesequaltotwicethesteadystatecurrentratingof thepower stage.Thisallowsheadroom forripplecurrent,loadtransients,and briefover-currentevents.Note that thisisa pulsedcurrentrequirement,nota continuouscurrentrequirement.The averagecurrentinthehigh-side FET isroughlyequaltotheloadcurrenttimesthedutycycle.For thisexample,an ID peak currentratingof40A orhigheristhetarget.The averagecurrentintheFET willbe highestatfullload,atthelowestinputvoltageand highestoutputvoltage.In thisexample,VIN(min)is6V and Vout(max)is3.3V.At fullload,the average FET currentwillbe 11A. Adding a 20% safetymargin to thisvalueproduces a 13.2A steadystatedraincurrent requirement. When convertingpower frominputvoltagesofapproximately8V and higher,switchinglossesbegintodominate over conductionlossesinthe high-sideFET. That means R DS(ON) isnot the primaryspecificationthatdrives high-sideFET selection.Low gate charge (Qg),low gate-to-draincharge (Qgd),and low gate resistance(Rg) become more importantparameters.One ofthemost usefulfiguresofmeritistheproductofon-resistanceand gatecharge(Qg × R DS(ON) ).The lowerthenumber,thebettertheFET. FETs arecharacterizedatseveralstandardgateenhancement voltages.The most popularareVGS voltagesare 4.5V and 10V. Since our designisusingapproximately6V of gate drive,the datasheetvaluesof R DS(ON) at 4.5VGS willbe ofgreatestinterest.Be cautiousofFETs thatarecharacterizedat2.5VGS .These arelow-threshold FETs thatare usefulwhen convertingpower atinputvoltagesbelow 6V. However, due tosubtle,butserious, sideeffectsofthelowthresholdvoltage,theyarebestavoidedwhen convertingpower atvoltagesabove 6V. For thisdesignthe TI CSD16322Q5 isan excellentchoiceforthe high-sideFET (Q1).Ithas low charge,an impressivefigureofmerit,and low Qgd. Itexhibitslow switchinglosses.Itisproducedinan industrystandard, thermallyenhanced,5 × 6mm package.Ithas more thanenough currenthandlingcapabilityforthis20A design.

18 Copyright© 2011,Texas InstrumentsIncorporated

www.ti.com SLUSAH3 –MAY 2011 Low-sideFET selectionisdrivenprimarilyby R DS(ON) . The lowerthe value,the higherthe efficiency.Lower R DS(ON) requiresa largerdiesize,whichincreasestotalgatechargeand devicecost.For a givenR DS(ON) value, thepartwiththelowestQg islikelytobe thebestchoice.At higherinputvoltagesand narrowerdutycycles,the low-sideFET isconductingcurrentforthemajorityofswitchingcycle.A thermallyenhanced package isa must. The continuouscurrentratingoftheFET shouldatleastbe equaltothecurrentratingofthepower stage. The TICSD16401Q5 isused as thelow-sideFET (Q2)inthisdesign.Ithas an R DS(ON) of1.5mΩ,withonly21nC of Qg at 4.5V.Ithas more than enough currenthandlingcapacity.Its25V minimum BV DSS ratingbeatsour minimum voltagecriteria.Itcomes inthesame 5 × 6mm package as Q1. Inrareinstances,theadditionofa seriesgateresistorcan be ofsome benefitwhen dealingwithhighamplitude ringing.Usually,however,the additionof seriesgate resistanceincreasesswitchinglossesand increasesthe riskofcross-conductionbetween thehigh-sideand low-sideFETs. A tight,low strayinductancePCB layout,ora snubber network are the preferredmethods for reducingringing.ResistorsR9 and R10 are shown as placeholdersin Figure7. They can be added to the PCB layoutto allowforthe possibilitythatseriesgate resistancemay be needed. In most cases theyare not requiredand can be consideredoptional.Iftheyare added tothedesign,thedefaultvalueof0Ω shouldinitiallybe used. SW NODE CLAMP At higheroutputcurrents,the switchingnode can momentarilyswing more than a 1V below ground.This conditioncan interferewiththe properoperationof the chip.To preventthe SW pinfrom beingsubjectedto excessivenegativevoltageswings,a Schottkydiode clamp and currentlimitingresistor,D1 and R11, are insertedbetween the actualswitchingnode and the SW pin(pin20).Diode D1 shouldbe a power Schottky deviceratedata minimum of0.5A ofcurrentand atleast30V breakdown voltage.The deviceshown inFigure7 isa 0.5A,40V deviceina SOD123 package.The diodeshouldbe placedas closeas possibletotheUCD7232 and be connectedbetween theSW pinand PGND pinby short,widetraces.Small-signalSchottkydiodesshould notbe used.Theirforwardvoltagedropathighercurrentsistoohightoprovideeffectiveclamping.Use a value of1Ω forR11. Largervalueswillinterferewiththeanti-crossconductionlogicused tocontroltheturn-onand turn-offofthehigh-sideFET, Q1. SNUBBER NETWORK Energy storedintheparasiticinductanceinthesourceand drainleadsofthepower FETs isreleasedwhen the FETs abruptlyturnon and off.The parasiticinductanceinteractswiththeoutputcapacitanceC OSS )oftheFETs toforma resonantcircuit.The end resultishighamplitude,highfrequencyringingon theswitchingnode thatis most prominentjustafterthe high-sideFET isturnedon. The frequencyof the ringingiscommonly in the 100MHz range.Itspeak amplitudecan be as much as twicetheinputvoltage.Ifnothingisdone todamp the ringing,itcan cause avalanchebreakdown of the low-sideFET, increaseradiatedEMI levels,and, most importantforthisdiscussion,interferewiththedetectionofan over-currentcondition.When leftundamped, the ringingon theswitchingnode can takeseveralhundredsofnanosecondstodieout. A simpleseriesRC networkconnectedtotheswitchingnode iscommonly used todampen or“snub” theringing. The capacitorcouplesthehighfrequencycontenttotheresistor,and theresistordissipatestheenergy.Withthe correctvalues,the ringingcan be made to decay to negligiblelevelsin100ns or less.C5 (2200pF)and R8 (3.01Ω)performthisfunctionintheexample circuit.R8 must be capableofdissipatingseveralhundredmilliwatts ofpower.The amount ofpower dissipatedinR8 isproportionaltotheswitchingfrequencyand thevalueofC5. With the valuesshown, R8 willdissipateapproximately125mW at 500kHz. This willdouble ifthe switching frequencyisincreasedto1MHz. Itisrecommended thata 500mW ratedresistorbe used forR8. The optimum valuesof the snubber R and C are deviceand layoutdependant.Some experimentationmay be needed to achievetheoptimum trade-offbetween damping timeand power lostinthedamping resistor.Inmost cases,the valueof R isbetween 1Ω and 10Ω, and C isbetween 1000pF and 4700pF. Highervaluesof C cause more currenttoflowinR whichincreasesthepower dissipated. Copyright© 2011,Texas InstrumentsIncorporated 19

SLUSAH3 –MAY 2011 www.ti.com COMPUTING VALUES FOR R DLY and R HS Sense R DLY setstheamount ofblankingtimeforthehighspeed comparatorthatmonitorsthevoltagedropacrossthe high-sideFET duringitson-time.Thiscomparatorfireswhen thehigh-sideFET isconductingtoomuch current. Because of the timeittakesforringingto decay on the switchingnode, the comparator“decision” shouldbe delayedfora shortamount oftimeafterthehigh-sideFET isturnedon.Witha propersnubbernetwork,a delay timeof 100ns shouldbe sufficientto allowforproperover-currentdetection.Using the formulainthe RDLY section,valueof 8.03kΩ producesa 100ns delay.The neareststandardvalueis8.06kΩ, so thisisthe value used forR7. Note thatwhen thedutycycleisofshorterdurationthantheblankingtime,thehigh-sidefaultsensingcircuitis blankedforthe entiretime.Thus thereisno high-sideFET protectionwhen the dutycycledurationisshorter thantheRDLY blankingtime.Thisconditioncommonly occursduringsoft-start,when theoutputvoltageisbeing ramped up from zero,or when operatingat highswitchingfrequenciesand attemptingto produce low output voltagesfromhighinputvoltages.Keep thisinmind when settingoperatingfrequencyand inputtooutputvoltage ratios. The firststepinselectinga valueforR HS Sense, isto determinewhat isthe maximum allowablevoltagedrop acrossthehigh-sideFET. Thisiscalculatedfrom theR DS(ON) oftheFETs, takingintoaccountitslikelyjunction temperaturewhen operatingat the maximum currentpoint,and by the maximum allowableFET current.The R DS(ON) valueon thedatasheetisspecifiedat25°C and ata particularVGS voltage,typically4.5V and 10V. In thiscase,neithervalueiscorrect,sincethisdesignwillapplyingapproximately6.2V to the gate.Additionally, FET R DS(ON) has a high,positivetemperaturecoefficientoftypically4000ppm/°C. Thismeans fora 100°C risein junctiontemperature,the on-resistancewillgo up by 40%. For a faultcondition,using a 125°C junction temperatureisa reasonableassumption.A validestimateoftheR DS(ON) with6V ofenhancement at125°C ofthe CSD16322Q5 is5m Ω. The second stepistocalculatea maximum currentvalueforthehigh-sideFET. Use 150% oftheratedoutput currentvalue,plusone halfofthepeak-to-peakinductorripplecurrent.For thisexample thisgivesa valueof 1.5× 20 × ½ × 5 = 32.5A.Thislevelofcurrentprovidesheadroom fortransients,start-upsurgecurrents,and the increasein inductorripplecurrentas the inductancefallswithincreasingcurrent.The maximum allowable voltagedropcan now be calculatedas justtheproductofthemaximum currentvalueand the“hot” R DS(ON) .This producesa valueof162.5mV forthisdesign.Thisshouldnotbe regardedas a precisionvalue.Keep inmind thatthehigh-sideFET protectionismeant tobe thelastprotectionforthepower stagetopreventcatastrophic damage to the power train.The maximum voltagedrop valueshouldbe sethighenough to preventnuisance tripsoftheprotectioncircuitryundernormaloperation. The valueforR HS Sense can now be calculated.Itsresistance,inkΩ,isequaltothemaximum high-sidevoltage drop,inmV, dividedby 100.Inour example thisproducesa valueof1.63kΩ.Rounding thisup tothenearest standardvalueof1.65kΩ givesthevalueforR12. SETTING THE ILIMTHRESHOLD The primaryfaultprotectionmechanism inthe UCD7232 isthe outputcurrentdetectioncircuitry.An internal comparatormonitorsthevoltageon theILIMand IMON pins.When thevoltageon IMON exceeds thevoltageon ILIM,theFLT pinisassertedand power conversionstops.Ifa UCD92xx controllerisused todrivethepower stage,itcan alsomonitorthevoltageon IMON and detectan overcurrentcondition.The thresholdforthefaulttrip pointiseasilysetby firmware,making itflexible.The maximum currentsense inputvoltagethatcan be correctly digitallysampled by a UCD92xx controlleris2.5V.(Themaximum programmablelimitforthefastOC thresholdis 2V.)Forthisdesignitwas decidedtouse this2.5Vlevelas thethresholdfortheILIMcomparator.Inthisway the digitallyprogrammablecontrollerwilldetecta slowlychangingOC fault,and theILIMcomparatorinthedriverwill protectthesystem from a sudden increaseincurrent.Thiscorrespondstoan outputcurrentofapproximately 31A. Allthatneeds tobe done istosetup a voltagedividerthatwillproduce2.5V attheILIMpin.The BP3 pin providesa convenientsourceofclean,regulated3.3V.The valueofR5 was arbitrarilysetto10kΩ.Simplemath producesa valueof31.6kΩ forR6. These valuesproducethedesired2.5V on ILIM.The voltagedivideronly draws 80μA fromtheBP3 pin,whichiswithintheallowablelimits.

www.ti.com SLUSAH3 –MAY 2011 INPUT AND OUTPUT CAPACITORS At thedrainofthehigh-sideFET, currentisdrawn infast,brief,rectangularpulses.Itisimportanttoprovidelow impedance,highfrequencyenergystoragerightatthedrainoftheFET. For this20A power stage,two 22µF, 16V or 25V ceramiccapacitorsare recommended. C1 and C2 shouldbe placedas closetothedrainofQ1 as possible.The groundsideofthecapacitorsshouldbe connectedas closeas possibletothesourceleadofQ2. If designinga multiphasepower supply,these capacitorsshouldbe presentat each power stage.Bulk input bypass capacitancemay also be requiredto minimizevoltagevariationsduringtransientloads.This bulk capacitanceisnotshown on Figure7,butitistypicallyrequired.Bulkcapacitancecan be sharedamong multiple power stages. The inductorripplecurrentmust be absorbedby theoutputcapacitors.The ripplecurrentistriangularinshape and containssignificantenergy at the switchingfrequencyand itsharmonics.To keep the ripplevoltage amplitudetoa minimum, low ESR and low ESL capacitorsmust be used.Multilayerceramiccapacitorsareideal devices.While bulkcapacitanceisalsorequiredto provideenergy storageduringtransientevents,the bulk capacitorsdo not typicallyhandle much ripplecurrentbecause theirhigherESL and ESR make them look inductiveattheripplefrequencies. The outputripplevoltageisdirectlyproportionaltotheinductorripplecurrent.The inductorripplecurrentvaries widely with input voltageand duty cycle.That makes it difficultto come up with a one-size-fits-all recommendationforthe properamount of ceramicoutputcapacitance.A good startingpointisapproximately 100µF.Inthisdesigntwo 47µF capacitorsareused (C7 and C8).These capacitorsshouldbe placedclosetothe inductor,L1,and thegroundsideofthesecaps shouldbe connectedas closeas possibletothesourceleadof thelow-sideFET, Q2. Bulk capacitanceisused not onlyforshortterm transientenergy storage,but alsoas a frequencyresponse tailoringelementinthepower supplyfeedbackloop.Severalhundredmicrofarads,ata minimum, arecommonly used ina power stageofthiscurrentcapability.Inthisexample,330µF isbeingused (C9).More capacitance may be requireddependingon thetransientresponserequirementsoftheload. BYPASS AND BOOTSTRAP CAPACITORS In thisdesign,the bypass capacitorson BP3 (C12),VGG (C4),and the bootstrapcapacitor(C3) use the recommended values.A highfrequency0.1µF bypass capacitor,C11, has alsobeen added attheVinpinofthe UCD7232. Thiscap attenuatesthehighfrequencynoisethatispresenton theVin rail.Itshouldbe placedas closeas possibletopin16 and connecttoanaloggroundwitha short,directtrace. LAYOUT RECOMMENDATIONS Propercomponent placementand traceroutingcan have a significantimpacton overallpower stageefficiency and reducenoisecouplingintonearbycircuits.The followingaresome key layoutconsiderations.

Locatethedriveras closeas possibletothepower FETs, butdo notplaceitdirectlyundereitherFET. The driverisa power deviceand needs itsown thermalcoolingpath.Clusteringmultiplehot partstoo close togethercan increasetheriskofexcessivetemperatureriseand potentiallycause a thermalshutdownevent.
LocatetheVGG bypassand bootstrapcapacitorsas closeas possibletothedriver.
Pay specialattentiontotheGND trace.The ground sideoftheinputbypass capacitors,theground sideof the outputcapacitors,the low-sideFET source leads,and the PGND connectionto the drivershould connectedtogetherina tight“singlepoint” ground,usingwide,low inductancetracesand few,ifany vias. Use ofa groundplaneisstronglyencouraged.
Connect thepower-padon thebottomofthedrivertoanalogground.The power-padisnotintendedtobe a highcurrentcarryingconnection.The analoggroundand power groundshouldbe connectedtogetheratone point,near the AGND pin.Care shouldbe takento insurethatheavy currentsare not pulledthroughthe analoggroundtraces.
The switchingnode traceshouldbe keptshortand compact.Thisisthenoisiestnode inthesystem withhigh dV/dtslewrates.
Use wide tracesfortheHS Gate and LS Gate signalscloselyfollowingtheassociatedswitchingnode and drivetracehas tobe routedfromone layertoanother.
Keep thelow levelinputand outputtracesaway fromtheswitchingnode.The highdV/dtsignalpresentthere can inducesignificantnoiseintotherelativelyhighimpedance nodes.Pay particularattentiontotheroutingof theCSP and CSN traces. Copyright© 2011,Texas InstrumentsIncorporated 21

To□current□sense circuitry Inductor□PCB□pads Inductor□PCB□pads To□current□sense circuitry Right! Wrong! UCD7232 SLUSAH3 –MAY 2011 www.ti.com INDUCTOR CURRENT SENSE TRACE LAYOUT Since matchingof the L/DCR to RC timeconstantsisimportantto obtainan accuratereplicaof the inductor current,the PCB layoutmust be done correctlyto insurethatthe voltagedrop acrossthe inductorissensed properly.For bestresults,the currentsensingconnectionsshouldbe made by separate,non-current-carrying tracesthatconnectdirectlytotheinductorsolderpads.The sensingconnectionsshouldnotbe made tocurrent carryingtracesthatleadtotheswitchingnode or theoutputcapacitors.An example ofa correctand incorrect layoutisgiveninFigure8. Figure8. InductorCurrentSense Trace Layout The currentcarryingtraceshave finiteresistancethatexhibitan additionalvoltagedrop which willcontaminate the sensed readings.Itrepresentsan additionalDCR thatisnot taken intoaccountin the currentsensing equations.The traceresistancevarieswiththethicknessofthePCB copperused on theboard.Thisthickness can varyfrom batchtobatchofpc boards,so theadditionalresistanceofthetracesisnota tightlycontrolled value.Even a shortlengthof PCB tracecan introducea significantamount of added resistance.Remember, milliohmsmatter.By making a Kelvinconnectiontotheinductorpads,theeffectsofPCB traceresistancecan be minimized. LIMITATIONS OF DCR CURRENT SENSING The accuracyoftheDCR currentsense method islimitedby thestabilityoftheDCR and L valuesofthepower inductor.In practice,the inductancevalueof the power inductordecreaseswithincreasingloadcurrent.Most inductorswillexhibita 20% to30% reductionininductanceas loadcurrentchanges from no loadtofullrated current.The DCR sense method cannotdetectinductorsaturationora crackedcore,bothofwhichcause greatly increasedac currenttoflowintheinductor. The resistanceoftheinductorwindingsisstronglyaffectedby temperature.Most inductorsuse copperwire,and copperhas a resistancetemperaturecoefficientofapproximately+3800ppm/°C. Thismeans thatifthewinding temperatureoftheinductorrisesby 40°C, itsDCR willincreaseby 15.2%.Thiswillcause thesensed voltageat CSP and CSN toincreaseby 15.2% as wellforthesame currentflow.Ifhighaccuracyofmeasured currentis important,then some form of temperaturecorrectionneeds to be appliedto the DCR sensed reading.This requiressome form of temperaturesensingand a method to correlatethe sensed temperatureto the actual windingtemperature. Since itisimpracticalto placea temperaturesensorinsidethe inductorto sense the windingtemperature,a practicalalternativeistosense thehigh-sideFET devicetemperature.Testshave shown thata smallanalog- outputtemperaturesensor placedunder the high-sideFET on the back sideof the board works wellas a substitute.Itstemperatureoutput correlatesstronglyto the inductorwinding temperature.The voltage proportionaltotemperaturecan be fedtotheTemp inputoftheUCD92xx familyofDigitalPower Controllers.The firmwareinternaltothecontrollercan use thetemperaturereadingtocorrectforthetemperatureeffectson the DCR currentsense readings.

www.ti.com SLUSAH3 –MAY 2011

RELATED PRODUCTS

DEVICE DESCRIPTION LITERATURE NUMBER UCD9240 DigitalPointofLoad System Controller SLUS766C UCD9220 DigitalPWM System Controller SLUS904 UCD9112 DigitalDual-PhaseSynchronousBuck Controller SLVS711C RELATED LITERATURE DESCRIPTION LITERATURE NUMBER QFN/SON PCB Attachment SLUA271A Quad FlatpackNo-Lead LogicPackages SCBA017D ReducingRingingThroughPCB LayoutTechniques SLPA005 Copyright© 2011,Texas InstrumentsIncorporated 23

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) UCD7232RTJR Active Production QFN (RTJ) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 UCD7232RTJR.B Active Production QFN (RTJ) | 20 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 UCD7232RTJT Active Production QFN (RTJ) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 UCD7232RTJT.B Active Production QFN (RTJ) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 UCD7232RTJTG4 Active Production QFN (RTJ) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 UCD7232RTJTG4.B Active Production QFN (RTJ) | 20 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD7232 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 7-Oct-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD7232RTJR QFN RTJ 20 3000 353.0 353.0 32.0 UCD7232RTJT QFN RTJ 20 250 213.0 191.0 35.0 UCD7232RTJTG4 QFN RTJ 20 250 213.0 191.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTJ 20 PLASTIC QUAD FLATPACK - NO LEAD4 x 4, 0.5 mm pitch 4224842/A

7<3VIA15(1.1)TYP161161015(3.8)2120X (0.24)

R E V I S I O N SREVDESCRIPTIONECRDATEENGINEER / DRAFTSMANA RELEASE NEW DRAWING216073610/24/2016T. TANG / H. DENGSIZESCALEREVAPAGEOF55NTS4219125A

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information

SLPA005 specifications and overview.

Summary

Digital Control Compatible Synchronous-Buck Gate Driver With Current Sense and Fault Protection MAY 2011

Description

Digital Control Compatible Synchronous-Buck Gate Driver With Current Sense and Fault Protection MAY 2011

Source title SLPA005 Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer

SLPA005

Read SLPA005 online.

UCD7232 TI | Alldatasheet

Document overview

Technical content

2 Copyright© 2011,Texas InstrumentsIncorporated

ORDERING INFORMATION

250 UCD7232RTJT

2500 UCD7232RTJR

4 Copyright© 2011,Texas InstrumentsIncorporated

ELECTRICAL CHARACTERISTICS

6 Copyright© 2011,Texas InstrumentsIncorporated

11 RDLY I Requiresa resistortoAGND forsettingtheCurrentSense blankingtimeforthehigh-sidecurrentsense

16 Vin I InputVoltagetothebuck power stageand drivercircuitry

8 Copyright© 2011,Texas InstrumentsIncorporated

10 Copyright© 2011,Texas InstrumentsIncorporated

12 Copyright© 2011,Texas InstrumentsIncorporated

14 Copyright© 2011,Texas InstrumentsIncorporated

APPLICATION INFORMATION

16 Copyright© 2011,Texas InstrumentsIncorporated

18 Copyright© 2011,Texas InstrumentsIncorporated

20 Copyright© 2011,Texas InstrumentsIncorporated

22 Copyright© 2011,Texas InstrumentsIncorporated

RELATED PRODUCTS

SLPA005 specifications and overview.

More parts from the same family.