SLOS490TPA6205A1

TPA6205A1_17 TI1 | Alldatasheet

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C( )BYPASS (Optional) Actual Solution Size 6,9 mm 5,25 mm (1)CB RI RI CS RF RF Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community SLOS490TPA6205A1 SLOS490C –JULY 2006–REVISED NOVEMBER 2015 TPA6205A11.25-WMonoFullyDifferentialAudioPowerAmplifier With1.8-VInputlogicThresholds

1 Features 3 Description

The TPA6205A1 device is a 1.25-W mono fully 1• 1.25 W Into 8-Ω From a 5-V Supply at THD = 1% differential amplifier designed to drive a speaker with(Typical) at least 8-Ω impedance while consuming less than 37• Shutdown Pin has 1.8-V Compatible Thresholds mm2 (ZQV package option) total printed-circuit-board

• Low Supply Current: 1.7 mA Typical (PCB) area in most applications. This device operates from 2.5 V to 5.5 V, drawing only 1.7 mA of quiescent• Shutdown Current < 10 µA supply current. The TPA6205A1 is available in the• Only Five External Components space-saving 2-mm × 2-mm MicroStar Junior BGA – Improved PSRR (90 dB) and Wide Supply package, and the space saving 3-mm × 3-mm QFN Voltage (2.5 V to 5.5 V) for Direct Battery (DRB) package. Operation Features like 85-dB PSRR from 90 Hz to 5 kHz, – Fully Differential Design Reduces RF improved RF-rectification immunity, and small PCB Rectification area makes the TPA6205A1 ideal for wireless handsets. A fast start-up time of 4s with minimal pop– Improved CMRR Eliminates Two Input makes the TPA6205A1 ideal for PDA applications.Coupling Capacitors – C(BYPASS) Is Optional Due to Fully Differential Device Information(1) Design and High PSRR PART NUMBER PACKAGE BODY SIZE (NOM)
• Available in 3-mm × 3-mm QFN Package (DRB) MSOP-PowerPAD (8) 3.00 mm × 3.00 mm
• Available in an 8-Pin PowerPAD™ MSOP (DGN) SON (8) 3.00 mm × 3.00 mmTPA6205A1• Available in a 2-mm × 2-mm MicroStar Junior™ BGA MICROSTAR 2.00 mm × 2.00 mmJUNIOR (8)BGA Package (ZQV) (1) For all available packages, see the orderable addendum at 2 Applications the end of the data sheet.
• Designed for Wireless Handsets, PDAs, and Other Mobile Devices
• Compatible With Low Power (1.8-V Logic) I/O Threshold Control Signals Application Circuit Example Solution Size An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLOS490C –JULY 2006–REVISED NOVEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2008) to Revision C Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

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(SIDE VIEW) SHUTDOWN IN+ VDD VO+ GND VO- IN- A B C 1 2 3 BYP ASS 8SHUTDOWN BYP ASS IN+ IN- VO- GND VDD VO+ SLOS490TPA6205A1 www.ti.com SLOS490C –JULY 2006–REVISED NOVEMBER 2015

5 Device Comparison Table

DEVICE NUMBER SPEAKER SPEAKER AMP OUTPUT POWER (W) PSRR (dB) CHANNELS TYPE TPA6203A1 Mono Class AB 1.25 90 TPA6204A1 Mono Class AB 1.7 85 TPA6205A1 (1.8-V comp SD) Mono Class AB 1.25 90 TPA6211A1 Mono Class AB 3.1 85

6 Pin Configuration and Functions

I/O DESCRIPTIONBGA MICROSTAR SON,NAME JUNIOR MSOP-PowerPAD BYPASS C1 2 I Mid-supply voltage. Adding a bypass capacitor improves PSRR. GND B2 7 I High-current ground IN– C3 4 I Negative differential input IN+ C2 3 I Positive differential input SHUTDOWN B1 1 I Shutdown terminal (active low logic) VDD A3 6 I Supply voltage terminal VO+ B3 5 O Positive BTL output VO– A1 8 O Negative BTL output Connect to ground. Thermal pad must be soldered down in allThermal Pad N/A — — applications to properly secure device on the PCB. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SLOS490TPA6205A1

SLOS490C –JULY 2006–REVISED NOVEMBER 2015 www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage –0.3 6 V VI Input voltage INx and SHUTDOWN pins –0.3 0.3 V See DissipationContinuous total power dissipation Ratings TA Operating free-air temperature –40 85 ºC TJ Junction temperature –40 125 ºC Lead temperature 1.6 mm (1/16 inch) from ZQV, DRB, DGN 260 ºCcase for 10 seconds Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±1500C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 2.5 5.5 V VIH High-level input voltage SHUTDOWN 1.15 V VIL Low-level input voltage SHUTDOWN 0.5 V VIC Common-mode input voltage VDD = 2.5 V, 5.5 V, CMRR ≤ –60 dB 0.5 VDD–0.8 V TA Operating free-air temperature –40 85 °C ZL Load impedance 6.4 8 Ω

7.4 Thermal Information

BGA MICROSTAR MSOPTHERMAL METRIC(1) SON UNITJUNIOR PowerPAD

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 134.4 57.3 109.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 79.8 84.0 67.8 °C/W RθJB Junction-to-board thermal resistance 71.1 32.2 47.6 °C/W ψJT Junction-to-top characterization parameter 5.3 3.7 4.7 °C/W ψJB Junction-to-board characterization parameter 71.0 32.2 47.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 11.8 15.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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www.ti.com SLOS490C –JULY 2006–REVISED NOVEMBER 2015

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output offset voltage[VOO] VI = 0 V, VDD = 2.5 V to 5.5 V 9 mV(measured differentially) PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –90 –70 dB VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD – 0.8 –70 –65 CMRR Common-mode rejection ratio dB VDD = 2.5 V, VIC = 0.5 V to 1.7 V –62 –55 VDD = 5.5 V 0.3 0.46 RL = 8 Ω, VIN+ = VDD, VIN– =VOL Low-level output voltage VDD = 3.6 V 0.22 V0 V or VIN+ = 0 V, VIN– = VDD VDD = 2.5 V 0.19 0.26 VDD = 5.5 V 4.8 5.12 RL = 8 Ω, VIN+ = VDD, VIN– =VOH High-level output voltage VDD = 3.6 V 3.28 V0 V or VIN+ = 0 V, VIN– = VDD VDD = 2.5 V 2.1 2.24 [IIH] High-level input current VDD = 5.5 V, VI = 5.8 V 1.2 µA [IIL] Low-level input current VDD = 5.5 V, VI = –0.3 V 1.2 µA IDD Supply current VDD = 2.5 V to 5.5 V, No load, SHUTDOWN = VIH 1.7 2 mA Supply current in shutdownIDD(SD) SHUTDOWN = VIL , VDD = 2.5 V to 5.5 V, No load 0.01 0.9 µAmode

7.6 Operating Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 5 V 1.25 THD + N = 1%, f = 1PO Output power VDD = 3.6 V 0.63 WkHz VDD = 2.5 V 0.3 VDD = 5 V, PO = 1 W, f = 1 kHz 0.06% Total harmonic distortion plusTHD+N VDD = 3.6 V, PO = 0.5 W, f = 1 kHz 0.07%noise VDD = 2.5 V, PO = 200 mW, f = 1 kHz 0.08% C(BYPASS) = 0.47°F, VDD = 3.6 V to 5.5 V, f = 217 Hz to 2 kHz, VRIPPLE –87Inputs AC-grounded = 200 mVPP with CI = 2 F C(BYPASS) = 0.47 F, VDD = 2.5 V to 3.6 V, f = 217 Hz to 2 kHz, VRIPPLEkSVR Supply ripple rejection ratio –82 dBInputs AC-grounded = 200 mVPP with CI = 2 F C(BYPASS) = 0.47 F, VDD = 2.5 V to 5.5 V, f = 40 Hz to 20 kHz, VRIPPLE ≤ –74Inputs AC-grounded = 200 mVPP with CI = 2 F SNR Signal-to-noise ratio VDD = 5 V, PO= 1 W 104 dB f = 20 Hz to 20 kHz No weighting 17 VRMS Vn Output voltage noise A weighting 13 VDD= 2.5 V to 5.5 V, f = 20 Hz to 1 kHz ≤ –85 dB Resistor tolerance =CMRR Common-mode rejection ratio 0.1%, Gain = 4V/V, f = 20 Hz to 20 kHz ≤ –74 VICM = 200 mVPP ZI Input impedance 2 MΩ ZO Output impedance Shutdown mode >10 kΩ Shutdown attenuation f = 20 Hz to 20 kHz, RF = RI = 20 kΩ –80 dB Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SLOS490TPA6205A1

7.7 Dissipation Ratings

7.8 Typical Characteristics

Table 1. Table of Graphs Figure 1. Output Power vs Supply Voltage Figure 2. Output Power vs Load Resistance

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2.5 V 5 V

Figure 3. Output Power vs Load Resistance Figure 4. Power Dissipation vs Output Power Figure 6. Maximum Ambient Temperature vs PowerFigure 5. Power Dissipation vs Output Power Figure 7. Total Harmonic Distortion + Noise vs Output Figure 8. Total Harmonic Distortion + Noise vs Output

Figure 9. Total Harmonic Distortion + Noise vs Frequency Figure 10. Total Harmonic Distortion + Noise vs Frequency Figure 11. Total Harmonic Distortion + Noise vs Frequency Figure 12. Total Harmonic Distortion + Noise vs Frequency Figure 13. Total Harmonic Distortion + Noise vs Common- Figure 14. Supply Voltage Rejection Ratio vs Frequency

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Figure 21. Common-Mode Rejection Ratio vs Frequency Figure 22. Common-Mode Rejection Ratio vs Common- Figure 23. Closed-Loop Gain / Phase vs Frequency Figure 24. Open-Loop Gain / Phase vs Frequency Figure 26. Start-Up Time vs Bypass CapacitorFigure 25. Supply Current vs Supply Voltage

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C( )BYPASS (Optional) SLOS490TPA6205A1 www.ti.com SLOS490C –JULY 2006–REVISED NOVEMBER 2015

8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Specifications section.

9 Detailed Description

9.1 Overview

The TPA6205A1 is a 1.25-W mono fully differential amplifier. The devices operates in the range of 2.5 V to 5.5 V and with at least 8-Ω impedance load. It's fully differential input allows it to avoid using input coupling capacitors and improves its RF-immunity.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Fully Differential Amplifiers

The TPA6205A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the input.

9.3.1.1 Advantages of Fully Differential Amplifiers

• Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6205A1, allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has mid-supply lower than the mid-supply of the TPA6205A1, the common-mode feedback circuit adjusts for that, and the TPA6205A1 outputs are still biased at mid-supply of the TPA6205A1. The inputs of the TPA6205A1 can be biased from 0.5 V to VDD – 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are required.
• Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a bypass capacitor. This is because any shift in the mid-supply affects both positive and negative channels equally and cancels at the differential output. However, removing the bypass capacitor slightly worsens power supply rejection ratio (kSVR), but a slight decrease of kSVR may be acceptable when an additional component can be eliminated (see Figure 17).
• Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SLOS490TPA6205A1

9.3.2 Fully Differential Amplifier Efficiency and Thermal Information

drop that varies inversely to output power. The second component is due to the sinewave nature of the output. dissipation of the amplifier. waveform. Equation 1 through Equation 7 are the basis for calculating amplifier efficiency. Figure 27. Voltage and Current Waveforms for BTL Amplifiers

• PL = Power delivered to load
• PSUP = Power drawn from power supply
• VLRMS = RMS voltage on BTL load
• RL = Load resistance
• VP = Peak voltage on BTL load (1) Therefore, PL is calculated by Equation 2: (2) And PSUP is calculated by Equation 3: where

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• PSUP = Power drawn from power supply
• IDDavg = Average current drawn from the power supply
• VDD = Power supply voltage (3) IDDavg can be found in Equation 4: (4) Therefore PSUP is calculated by Equation 5: (5) substituting PL and PSUP into Equation 6, where
• (6) Therefore: where
• ηBTL = Efficiency of a BTL amplifier (7)

Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8- Ω BTL Systems the power supply is almost 1.8 W. VDD goes down, efficiency goes up. PDmax for a 5-V, 8-Ω system is 634 mW.

9.3.3 Differential Output Versus Single-Ended Output

voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 11). Figure 28. Differential Output Configuration

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speaker impedance and the coupling capacitance and is calculated with Equation 12. minimized by eliminating the bulky coupling capacitor. Figure 29. Single-Ended Output and Frequency Response

9.4 Device Functional Modes

9.4.1 Summing Input Signals With The TPA6205A1

headphones require summing of the right and left channels to output the stereo signal to the mono speaker.

9.4.1.1 Summing Two Differential Input Signals

input source can be set independently (see Equation 13 and Equation 14, and Figure 30).

Figure 30. Application Schematic With TPA6205A1 Summing Two Differential Inputs

9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal

must see the same impedance for optimum performance, thus the use of RP and CP.

9.4.1.3 Summing Two Single-Ended Input Signals

by low impedance sources even if one of the inputs is not outputting an AC signal.

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Figure 31. Application Schematic With TPA6205A1 Summing Two Single-Ended Inputs

9.4.2 Shutdown Mode

shutdown mode when a HIGH logic level is applied to SHUTDOWN pin. SHUTDOWN pin is 1.8-V compatible.

validate and test their design implementation to confirm system functionality.

10.1 Application Information

common modes of operation. Any design variation can be supported by TI through schematic and layout reviews.

10.2 Typical Applications

Figure 32 through Figure 31 show application schematics for differential and single-ended inputs.

10.2.1 TPA6205A1 With Differential Input

considerations for this application. Figure 32. Typical Differential Input Application Schematic

10.2.1.1 Design Requirements

Table 3 lists the design parameters of the device. Table 3. Design Parameters

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10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Selecting Components

Typical values are shown in Table 4. Table 4. Typical Component Values The input (RI) and feedback resistors (RF) set the gain of the amplifier according to Equation 23. RF and RI should range from 1 kΩ to 100 kΩ. Most graphs were taken with RF = RI = 20 kΩ. better to keep the performance optimized. inputs, IN+ and IN–, is equal. 0.5 V to VDD – 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors.

Figure 33. CI and RI High-Pass Filter Cutoff Frequency The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 100 Hz. Equation 24 is reconfigured as Equation 25. source dc level. It is important to confirm the capacitor polarity in the application. applications because of the high PSRR of this device.

10.2.1.2.2 Using Low-ESR Capacitors

resistance the more the real capacitor behaves like an ideal capacitor.

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10.2.1.3 Application Curves

Figure 34. Output Power vs Supply Voltage Figure 35. Supply Current vs Supply Voltage

10.2.2 TPA6205A1 With Differential Input and Input Capacitors

considerations for this application. Figure 36. Differential Input Application Schematic Optimized With Input Capacitors

10.2.2.1 Design Requirements

Refer to the Design Requirements.

10.2.2.2 Detailed Design Procedure

Refer to the Detailed Design Procedure.

10.2.2.3 Application Curves

Refer to the Application Curves.

10.2.3 TPA6205A1 With Single-Ended Input

considerations for this application. Figure 37. Single-Ended Input Application Schematic

10.2.3.1 Design Requirements

Refer to the Design Requirements.

10.2.3.2 Detailed Design Procedure

Refer to the Detailed Design Procedure.

10.2.3.3 Application Curves

Refer to the Application Curves.

11 Power Supply Recommendations

upper power should not exceed the maximum current limit of the power switch.

11.1 Power Supply Decoupling Capacitors

faster than the board supply, thus helping to prevent any drop in the supply voltage.

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12 Layout

12.1 Layout Guidelines

coverage is approximately 50% of the pad area. In making the pad size for the BGA balls, it is recommended that the layout use soldermask-defined (SMD) land. diameters for a 2 mm × 2 mm MicroStar Junior™ BGA layout. pickup. The TPA6205A1 layout is shown in the next section as a layout example. Figure 38. MicroStar Junior™ BGA Recommended Layout

12.2 Layout Example

Figure 39. TPA6205A1 BGA Layout Figure 40. TPA6205A1 HVSSOP Layout

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Figure 41. TPA6205A1 VSON Layout

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13 Device and Documentation Support

13.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

13.2 Trademarks

MicroStar Junior, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

13.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: SLOS490TPA6205A1

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples HPA00801DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AAOI HPA02153A1DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AAOI TPA6205A1DGN ACTIVE MSOP- PowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AAPI TPA6205A1DGNG4 ACTIVE MSOP- PowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AAPI TPA6205A1DGNR ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AAPI TPA6205A1DGNRG4 ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AAPI TPA6205A1DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AAOI TPA6205A1DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AAOI TPA6205A1DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AAOI TPA6205A1ZQVR ACTIVE BGA MICROSTAR JUNIOR ZQV 8 2500 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR -40 to 85 AANI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

www.ti.com 15-Apr-2017 Addendum-Page 2 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPA6205A1DGNR MSOP- Power PAD TPA6205A1DGNR MSOP- Power PAD TPA6205A1ZQVR BGA MI CROSTA R JUNI OR TPA6205A1ZQVR BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 2-Nov-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA6205A1DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPA6205A1DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 TPA6205A1DRBR SON DRB 8 3000 367.0 367.0 35.0 TPA6205A1DRBR SON DRB 8 3000 367.0 367.0 35.0 TPA6205A1DRBT SON DRB 8 250 210.0 185.0 35.0 TPA6205A1DRBT SON DRB 8 250 210.0 185.0 35.0 TPA6205A1ZQVR BGA MICROSTAR JUNIOR ZQV 8 2500 336.6 336.6 28.6 TPA6205A1ZQVR BGA MICROSTAR JUNIOR ZQV 8 2500 338.1 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 2-Nov-2016 Pack Materials-Page 2

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