SLMA002

TPS55383_16 TI1 | Alldatasheet

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(1) RECOMMENDED OPERATING CONDITIONS TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) DEVICE NUMBER OPERATING FREQUENCY (kHz) PACKAGE MEDIA UNITS (Pieces) TPS55383PWP Tube 300 TPS55383PWPR Tape and Reel 2000 Plastic 16-Pin HTSSOP TPS55386PWP Tube 600 TPS55386PWPR Tape and Reel 2000 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com VALUE UNIT PVDD1, PVDD2, EN1 EN2 BOOT1, BOOT2 V SW SW1, SW2 to SW1, SW2 transient 50ns) to Input voltage range V BP 6.5 SEQ, ILIM2 0.3 to 6.5 COMP1, COMP2 0.3 to 3.5 FB1, FB2 0.3 to SW1, SW2 output current A BP load current mA T stg Storage temperature to +165 T J Operating temperature to +150 C Soldering temperature +260 (1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. MIN MAX UNIT V PVDD2 Input voltage 4.5 V Operating junction T J +125 C temperature Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

(ESD) PROTECTION PACKAGE DISSIPATION RATINGS (1) (2) (3) TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 MIN UNIT Human body model CDM 1.5k V Machine Model 250 THERMAL IMPEDANCE JUNCTION-TO-THERMAL T A +25 C T A +85 C PACKAGE PAD C/W) POWER RATING (W) POWER RATING (W) Plastic 16-Pin HTSSOP (PWP) 2.07 (4) 1.6 1.0 (1) For more information on the PWP package, refer to TI Technical Brief SLMA002A (2) TI device packages are modeled and tested for thermal performance using printed circuit board designs outlined in JEDEC standards JESD 51-3 and JESD 51-7. (3) For application information, see the Power Derating section. (4) T J-A +40 C/W. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

www.ti.com C T J +125 V PVDD1 V PVDD2 unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY (PVDD) V PVDD1 Input voltage range 4.5 V V PVDD2 IDD SDN Shutdown V EN1 V EN2 V PVDD2 150 µ A IDD Q Quiescent, non-switching V FB 0.9 Outputs OFF 1.8 3.0 mA SW node unloaded; Measured as BP sink IDD SW Quiescent, while-switching current V UVLO Minimum turn-on voltage PVDD2 only 3.8 4.1 4.4 V V UVLO(hys) Hysteresis 400 600 mV C BP µ EN1 and EN2 go low t START (1) (2) Time from startup to softstart begin ms simultaneously ENABLE EN V EN1 V EN2 Enable threshold 0.9 1.2 1.5 V Enable threshold hysteresis (1) mV I EN1 I EN2 Enable pull-up current V EN1 V EN2 V µ A t EN (1) Time from enable to soft-start begin Other EN pin GND µ s BP REGULATOR (BP) BP Regulator voltage V P VDD2 V 5.25 5.6 V P VDD2 4.5 switching, no external load on BP LDO Dropout voltage 400 550 mV BP I BP (1) Regulator external load mA I BPS Regulator short circuit 4.5 V P VDD2 V OSCILLATOR TPS55383 255 310 375 f SW Switching frequency kHz TPS55386 510 630 750 t DEAD (1) Clock dead time 140 ns ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF) C T J +85 C 786 800 812 V FB1, V FB2 Feedback input voltage mV C T J +125 C 784 812 I FB1, I FB2 Feedback input bias current nA g M g M (1) Error Amplifier transconductance 220 315 420 µ S f f (1) Error Amplifier dominant pole frequency kHz I SINK(COMP1) Error Amplifier sink current capability V FB1 V FB2 0.9V, V COMP V µ A I SINK(COMP2) I SRC(COMP1) Error Amplifier source current capability V FB1 V FB2 0.7V, V COMP V µ A I SRC(COMP2) SOFT START (SS) T SS1 T SS2 Soft start time 1.5 2.1 2.7 ms (1) Ensured by design. Not production tested. (2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower BP capacitor value. More information can be found in the Input UVLO and Startup section. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

www.ti.com SLUS818 SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) C T J +125 V PVDD1 V PVDD2 unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERCURRENT PROTECTION I CL1 Current limit Channel 3.6 4.5 5.6 V ILIM2 V BP 3.6 4.5 5.6 A I CL2 Current limit Channel V ILIM2 (floating) 2.4 3.0 3.6 V ILIM2 GND 1.15 1.50 1.75 V UV1 Low-level output threshold to declare a fault Measured at feedback pin. 670 730 mV V UV2 T HICCUP (3) Hiccup timeout ms t ON1(oc) (3) Minimum overcurrent pulse width 150 ns t ON2(oc) (3) BOOTSTRAP R BOOT1 From BP to BOOT1 or BP to BOOT2, Bootstrap switch resistance Ω R BOOT2 I EXT mA OUTPUT STAGE (Channel and Channel T J +25 V PVDD2 V R DS(on) (3) MOSFET on resistance plus bond wire resistance m Ω C T J +125 V PVDD2 V 165 t ON(min) (3) Minimum controllable pulse width I SWx peak current A (4) 100 200 ns D MIN Minimum Duty Cycle V FB 0.9 V TPS55383 f SW 300 kHz D MAX Maximum Duty Cycle TPS55386 f SW 600 kHz I SW Switching node leakage current (sourcing) Outputs OFF µ A THERMAL SHUTDOWN T SD (3) Shutdown temperature 148 C T SD(hys) (3) Hysteresis (3) Ensured by design. Not production tested. (4) See Figure for I SWx peak current Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

/c45 50 /c45 25 0 25 50 75 100 125 1.6 1.7 1.9 1.5 2.0 2.1 1.8 T Junction□T emperature C /c176J /c45 /c45 I Quiescent□Current mADDQ /c45 /c45 V 5.25□VBP = 100 120 /c45 50 /c45 25 0 25 50 75 100 125 140 T Junction□T emperature C /c176J /c45 /c45 I Shutdown□Current A /c109 SD /c45 /c45 VPVDDx 12□V= VPVDDx 4.5□V= V 28□VPVDDx = 3.6 3.7 3.8 3.9 4.1 4.2 4.0 UVLO(Off) UVLO(On) /c45 50 /c45 25 0 25 50 75 100 125 T Junction□T emperature C /c176J /c45 /c45 V UVL O /c45 /c45Undervoltage□Lockout V 1.15 1.17 1.21 1.23 1.19 1.25 /c45 50 /c45 25 0 25 50 75 100 125 EN(Off) EN(On) T Junction□T emperature C /c176J /c45 /c45 V Enable□Threshold□Voltage V EN /c45 /c45 TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com QUIESCENT CURRENT (NON-SWITCHING) SHUTDOWN CURRENT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure Figure UNDERVOLTAGE LOCKOUT THRESHOLD ENABLE THRESHOLDS vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

/c45 50 /c45 25 0 25 50 75 100 125 T Junction□T emperature C /c176J /c45 /c45 V 5.25□VBP = f PWM□Frequency kHz PWM /c45 /c45 1.5 2.0 2.5 3.0 3.5 /c45 50 /c45 25 0 25 50 75 100 125 T Junction□T emperature C /c176J /c45 /c45 t Soft□Start□Time msSS /c45 /c45 V 5.25□VBP = 580 640 680 600 660 /c45 50 /c45 25 0 25 50 75 100 125 620 T Junction□T emperature C /c176J /c45 /c45 f PWM□Frequency kHzPWM /c45 /c45 V 5.25□VBP = /c45 50 /c45 25 0 25 50 75 100 125 /c45 3 /c45 5 /c45 1 T Junction□T emperature C /c176J /c45 /c45 I Feedback□Bias□Current nA FB /c45 /c45 TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) SOFT START TIME SWITCHING FREQUENCY (300 kHz) vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure Figure SWITCHING FREQUENCY (600 kHz) FEEDBACK BIAS CURRENT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

4.8 4.6 4.4 4.2 4.0 /c45 50 /c45 25 0 25 50 75 100 125 T Junction□T emperature C /c176J /c45 /c45 VPVDD = 24□V VPVDD = 5□V VPVDD = 12□V I Overcurrent□Limit ACL /c45 /c45 788 793 798 803 808 /c45 50 /c45 25 0 25 50 75 100 125 T Junction□T emperature C /c176J /c45 /c45 V Feedback□Voltage mV FB /c45 /c45 2.6 2.8 3.0 3.2 3.4 /c45 50 /c45 25 0 25 50 75 100 125 T Junction□T emperature C /c176J /c45 /c45 VPVDDx 24□V= VPVDDx 12□V= VPVDDx 5□V= I Overcurrent□Limit ACL /c45 /c45 1.2 1.4 1.6 1.8 /c45 50 /c45 25 0 25 50 75 100 125 T Junction□T emperature C /c176J /c45 /c45 VPVDDx = 24□V VPVDDx = 12□V VPVDDx = 5□V I Overcurrent□Limit ACL /c45 /c45 TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) FEEDBACK VOLTAGE OVERCURRENT LIMIT (CH1, CH2 HIGH LEVEL) vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure Figure 10. OVERCURRENT LIMIT (CH2 MID LEVEL) OVERCURRENT LIMIT (CH2 LOW LEVEL) vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure 11. Figure 12. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

TA = 0°C IL - Load Current - A tON - Minimum Controllable Pulse Width - ns –40 TA(°C) TA = –40°C TA = 25°C TA = 85°C 1.2 150 -50 -25 0 25 50 75 100 125 TJ - Junction Temperature - °C ISW(off) - Switching Node Leakage Current - /c109A 4 8 12 16 20 24 28 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OCL = 4.5 AOCL = 3.0 A OCL = 1.5 A VDD - Supply Voltage - V IOC - Overcurrent Limit - A TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) SWITCHING NODE LEAKAGE CURRENT MINUMUM CONTROLLABLE PULSE WIDTH vs vs JUNCTION TEMPERATURE LOAD CURRENT Figure 13. Figure 14. OVERCURRENT LIMIT vs SUPPLY VOLTAGE Figure 15. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

(bottom side) HTSSOP (PWP) (Top View) 8 9 COMP2COMP1 TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O

DESCRIPTION

NO. Input supply to the high side gate driver for Output Connect a 22-nF to 82-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is BOOT1 I turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor Ω to Ω may be placed in series with the bootstrap capacitor. Input supply to the high side gate driver for Output Connect a 22-nF to 82-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is BOOT2 I turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor Ω to Ω may be placed in series with the bootstrap capacitor. Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7- µ F BP to 10- µ F X7R or X5R) ceramic capacitor. Output of Error Amplifier for Output A series connected R-C network from this pin to GND serves to COMP1 O compensate the feedback loop. See Feedback Loop Compensation Component Selection for further information. Output of Error Amplifier for Output A series connected R-C network from this pin to GND serves to COMP2 O compensate the feedback loop. See Feedback Loop Compensation Component Selection for further information. Active low enable input for Output If the voltage on this pin is greater than 1.55 Output is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output and allows soft start of EN1 I Output to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. Active low enable input for Output If the voltage on this pin is greater than 1.55 Output is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output and allows soft start of EN2 I Output to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. Voltage feedback pin for Output The internal transconductance error amplifier adjusts the PWM for Output to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from FB1 I Output to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Compensation for the feedback loop is provided externally to the device. See Feedback Loop Compensation Component Selection section for further information. Voltage feedback pin for Output The internal transconductance error amplifier adjusts the PWM for Output to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from FB2 I Output to ground, with the center connection tied to this pin, determines the value of the regulated Output voltage. Compensation for the feedback loop is provided externally to the device. See Feedback Loop Compensation Component Selection section for further information. GND Ground pin for the device. Connect directly to Thermal Pad. Current limit adjust pin for Output only. This function is intended to allow a user with asymmetrical load currents (Output load current much greater than Output load current) to optimize component ILIM2 I scaling of the lower current output while maintaining proper component derating in a overcurrent fault condition. The discrete levels are available as shown in Table Current Limit Threshold Adjustment for Output Note: An internal 2-resistor divider (150-k Ω each) connects BP to ILIM2 and to GND. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

www.ti.com SLUS818 SEPTEMBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL I/O NO. Power input to the Output high side MOSFET only. This pin should be locally bypassed to GND with a PVDD1 I low ESR ceramic capacitor of 10- µ F or greater. The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins and provides power to the Output high-side MOSFET. This pin should be locally bypassed to PVDD2 I GND with a low ESR ceramic capacitor of 10- µ F or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.1 This pin configures the output startup mode. If the SEQ pin is connected to BP, then when Output is enabled, Output is allowed to start after Output has reached regulation; that is, sequential startup where Output is slave to Output If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN1 to ground. If the SEQ pin is connected to GND, then when Output is enabled, Output is allowed to start after Output has reached regulation; that is, sequential startup where Output is slave to Output If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, SEQ I and the output voltages decay according to the load that is present. For this sequence configuration, tie EN2 to ground. If left floating, Output and Output start ratio-metrically when both outputs are enabled at the same time. They will soft start at a rate determined by their final output voltage and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently NOTE: An internal two resistor (150-k Ω each) divider connects BP to SEQ and to GND. See the Sequence States table. Source (switching) output for Output PWM. A snubber is recommended to reduce ringing on this SW1 O node. See SW Node Ringing for further information. Source (switching) output for Output PWM. A snubber is recommended to reduce ringing on this SW2 O node. See SW Node Ringing for further information. Thermal Pad This pad must be tied externally to a ground plane and the GND pin. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

R Current Comparator BP f(IDRAIN1) + DC(ofst) Anti-Cross Conduction

1.2 MHz

R Current Comparator BP Anti-Cross Conduction BP CLK2 Weak Pull-Down MOSFET 13BP 11ILIM2 150 k/c87 150 k/c87 BP CLK2 9COMP2 Level Select 5.25-V Regulator References BOOT1 PVDD1 SW1 BOOT2 PVDD2 SW2 f(IDRAIN2) + DC(ofst)

0.8 VREF

IMAX2 (Set to one of three limits) f(IDRAIN1) f(IMAX1) Overcurrent Comp f(ISLOPE1) Level Shift Level Shift f(IDRAIN2) f(IMAX2)f(ISLOPE2) FET Switch TSD PVDD2 f(ISLOPE1) f(ISLOPE2) SD1 SD2 UVLO www.ti.com Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

(UVLO) and Startup Enable and Timed Turn On of the Outputs TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 The TPS55383 and TPS55386 are dual output, non-synchronous converters. Each PWM channel contains an externally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, enable, and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, clock oscillator, and output voltage sequencing functions. NOTE: Unless otherwise noted, the term TPS5538x applies to both the TPS55383 and TPS55386. Also, unless otherwise noted, a label with a lowercase x appended implies the term applies to both outputs of the two modulator channels. For example, the term ENx implies both EN1 and EN2 Unless otherwise noted, all parametric values given are typical. Refer to the Electrical Characteristics for minimum and maximum values. Calculations should be performed with tolerance values taken into consideration. The bandgap cell common to both outputs is trimmed to 800 mV. The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are internally configured to operate on alternating switch cycles (that is, 180 out-of-phase). When the voltage at the PVDD2 pin is less than 4.1 a portion of the internal bias circuitry is operational, and all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises above the UVLO turn-on threshold, the state of the enable pins determines the remainder of the internal startup sequence. If either output is enabled ENx pulled low), the BP regulator turns on, charging the BP capacitor with a 20-mA current. When the BP pin is greater than PWM is enabled and soft start begins, depending on the SEQ mode of operation and the EN1 and EN2 settings. Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be higher or lower than PVDD2. (See the Dual Supply Operation section.) Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the associated output is enabled and soft start is initiated. If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is shut down and minimal functions are active. The total standby current from both PVDD pins is approximately µ A at 12-V input supply. An R-C connected to an ENx pin may be used to delay the turn-on of the associated output after power is applied to PVDDx (see Figure After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards ground. Once the voltage decays to approximately 1.2 then the output is enabled and the startup sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to PVDD2, then omit these two components and tie the ENx pin to GND directly. If an R-C circuit is used to delay the turn-on of the output, the resistor value must be much less than 1.2 V µ A or 200 k Ω A suggested value is k Ω This resistor value allows the ENx voltage to decay below the 1.2-V threshold while the µ A bias current flows. The capacitor value required to delay the startup time (after the application of PVDD2) is shown in Equation Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

/c61 /c230 /c246 /c45 /c180 /c180/c180 /c231 /c247 /c45 /c180/c232 /c248 /c108 (1) TPS5538x ENxC R VDD2 VDDx 5 /c109A 1.25 V T Time/c45 tDELAY0 tDELAY +□tSS PVDDx ENx VOUTx 1.2-V Threshold Output Voltage Sequencing TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com where: R and C are the timing components V TH is the 1.2-V enable threshold voltage I ENx is the µ A enable pin biasing current Additional enable pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing section.) Figure 16. Startup Delay Schematic Figure 17. Startup Delay with R-C on Enable DESIGN HINT If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to GND. This configuration allows the outputs to start immediately on valid application of PVDD2. If ENx is allowed to go high after the Outputx has been in regulation, the upper MOSFET shuts off, and the output decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remains in the OFF state. (See the Bootstrap for N-Channel MOSFET section.) The TPS5538x allows single-pin programming of output voltage startup sequencing. During power-on, the state of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs function as described in Table Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

(2 V/div) 3.3-V VOUT2 (2 V/div) T - Time - 1 ms/div SEQ = BP Sequential CH2 then CH1 T - Time - 1 ms/div SEQ = GND Sequential CH1 then CH2 5-V VOUT1 (2 V/div) 3.3-V VOUT2 (2 V/div) TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 Table Sequence States SEQ PIN STATE MODE EN1 EN2 Ignored by the device.when V EN2 enable threshold voltage Tie EN1 to enable threshold voltage for BP to be active when V EN2 BP Sequential, Output then Output Active enable threshold voltage Tie EN1 to enable threshold voltage for low quiescent current (BP inactive) when V EN2 enable threshold voltage Ignored by the device.when V EN1 enable threshold voltage Tie EN2 to enable threshold voltage for BP to be active when V EN1 GND Sequential, Output then Output Active enable threshold voltage Tie EN2 to enable threshold voltage for low quiescent current (BP inactive) when V EN1 enable threshold voltage Independent or Ratiometric, Output Active. EN1 and EN2 must be tied Active. EN1 and EN2 must be tied (floating) and Output together for Ratio-metric startup. together for Ratio-metric startup. If the SEQ pin is connected to BP, then when Output is enabled, Output is allowed to start approximately 400 µ s after Output has reached regulation; that is, sequential startup where Output is slave to Output If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. If the SEQ pin is connected to GND, then when Output is enabled, Output is allowed to start approximately 400 µ s after Output has reached regulation; that is, sequential startup where Output is slave to Output If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. Figure 18. SEQ Pin TIed to BP Figure 19. SEQ Pin Tied to GND NOTE: An R-C network connected to the ENx pin may be used in addition to the SEQ pin in sequential mode to delay the startup of the first output voltage. This approach may be necessary in systems with a large number of output voltages and elaborate voltage sequencing requirements. See Enable and Timed Turn On of the Outputs Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

(2 V/div) 3.3-V VOUT2 (2 V/div) T - Time - 1 ms/div Soft Start TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com If the SEQ pin is left floating, Output and Output each start ratiometrically when both outputs are enabled at the same time. Output and Output soft start at a rate that is determined by the respective final output voltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently. Figure 20. SEQ Pin Floating Each output has a dedicated soft-start circuit. The soft-start voltage is an internal digital reference ramp to one of two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total ramp time for the FB voltage to charge from V to 0.8 V is about 2.1 ms. During a soft-start interval, the TPS5538x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the internal 0.8-V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains at the reference voltage. During the soft-start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the Output Overload Protection section.) There is no pulse skipping if a current limit pulse is not detected. DESIGN HINT If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired regulation voltage by the time soft-start has completed, then the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage. See Operating Near Maximum Duty Cycle and Maximum Output Capacitance for related information. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

R2□=□R1/c180 (2) PVDD2 BOOT2 SW2 BP PVDD1 BOOT1 SW1 GND TPS5538x SEQ ILIM2 FB2 EN1 EN2 FB1 OUTPUT1 UDG-08041 8 9COMP2COMP1 Feedback Loop Compensation Component Selection TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulse width modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and GND (see Figure Assuming the value of the upper voltage setting divider is known, the value of the lower divider resistor for a desired output voltage is calculated by Equation where V REF is the internal 0.8-V reference voltage Figure 21. Voltage Setting Divider Network for Channel DESIGN HINT There is a leakage current of up to µ A out of the SW pin when a single output of the TPS5538x is disabled. Keeping the series impedance of less than k Ω prevents the output from floating above the referece voltage while the controller output is in the OFF state. In the feedback signal path, the output voltage setting divider is followed by an internal g M -type error amplifier with a typical transconductance of 315 µ An external series connected R-C circuit from the g M amplifier output (COMPx pin) to ground serves as the compensation network for the converter. The signal from the error amplifier output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure NOTE: Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow pulse width operation, especially at load currents less than See SW Node Ringing for further information on reducing noise on the SWx node. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

11.5 k/c87 Error Amplifier Offset f(IDRAIN) PWM to SwitchISLOPE ICOMP UDG-08040 COMP RCOMP CCOMP ICOMP – I SLOPE VREF VIN VOU T Compensation N etw ork Modulator Filter Current Feedback N etw ork VC TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com Figure 22. Feedback Loop Equivalent Circuit A more conventional small-signal equivalent block diagram is shown in Figure Here, the full closed-loop signal path is shown. Because the TPS5538x contains internal slope compensation, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. Figure 23. Small Signal Equivalent Block Diagram Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

(3) Maximum Output Capacitance /c40 /c41 SS CLx RIPPLE LOADOUT max OUT t 1C I I I V 2 /c230 /c246 /c230 /c246/c61 /c45 /c180 /c45 /c231 /c247 /c231 /c247 /c232 /c248/c232 /c248 (4) Minimum Output Capacitance Compensation For The Feedback Loop /c40 /c41 600000FmTPS55386 61.5 10 t V - VON -6 IN OUT19.7 e 50 10 L /c61 /c233 /c249/c180 /c180 /c230 /c246/c234 /c250/c180 /c43 /c180 /c180 /c231 /c247/c234 /c250/c231 /c247 /c232 /c248/c234 /c250/c235 /c251 (5) TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 Calculate the inductance value so that an output ripple current between 300 mA and 900 mA results. Lower ripple current results in discontinuous mode (DCM) operation at a lower DC load current, while higher ripple current generally allows for higher closed loop bandwidth. NOTE: For wide input range converters, highest input voltage results in the highest ripple current. NOTE: The load current at which the overcurrent protection (OCP) engages is dependent on the amount of ripple current, because it is the peak current in the switch that is monitored. See Output Overload Protection With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance which may be used before startup problems begin to occur. If the output capacitance is large enough so that the device enters a current-limit protection mode during startup, then there is a possibility that the output never reaches regulation. Instead, the TPS5538x simply shuts down and attempts a restart as if the output were short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is given by Equation Ensure the value of capacitance selected for closed-loop stability is compatible with the requirements of Soft Start To determine the components necessary for compensating the feedback loop, the controller frequency response characteristics must be understood and the desired crossover frequency selected. The best results are obtained if 10% of the switching frequency is used as this closed loop crossover frequency. In some cases, up to 20% of the switching frequency is also possible. With the output filter components selected, the next step is to calculate the DC gain of the modulator. For the TPS55386: The gain of the TPS55383 modulator is approximated by: Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

/c40 /c41 300000FmTPS55383 55.6 10 t V VON 6 IN OUT19.7 e 50 10 L /c61 /c233 /c249/c180 /c180 /c45/c230 /c246/c234 /c250/c45/c180 /c43 /c180 /c180 /c231 /c247/c234 /c250/c231 /c247 /c232 /c248/c234 /c250/c235 /c251 (6) 4V Fm 2 10INfc 6V Fm 50 10IN1 RLOAD /c45/c180 /c180 /c180 /c61 /c180 /c180 /c180 /c43 /c230 /c230 /c246 /c246 /c231 /c231 /c247 /c247 /c231 /c231 /c247 /c247 /c232 /c232 /c248 /c248 (7) EA CO LOAD OUT fcK 20 log 1 2 f R C /c230 /c246/c61 /c45 /c180 /c231 /c247 /c43 /c112 /c180 /c180 /c180/c232 /c248 (8) PVDD2 BOOT2 SW2 BP PVDD1 BOOT1 SW1 GND TPS5538x SEQ ILIM2 FB2 EN1 EN2 FB1 L COUT Output1 R2C2 (optional) UDG-08042 8 9COMP2COMP1 RCOMPCCOMP (optional) ZUPPER ZLOWER L C OUTC 1 R1 /c180 /c61 (9) TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com The overall DC gain of the of the converter control-to-output transfer function is approximated by: The next step is to find the desired gain of the error amplifier at the desired crossover frequency. Assuming a single pole roll off, evaluate the following expression at the desired crossover frequency. Figure 24. Loop Compensation Components If operating at wide duty cycles (over 50%), a capacitor may be necessary across the upper resistor of the voltage setting divider. (Ref Figure If duty cycles are less than 50%, this capacitor may be omitted. If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to instability. To compensate, a small capacitor is placed in parallel with the lower voltage setting divider resistor (Ref Figure The value of the capacitor is determined such that a pole is placed at the same frequency as the ESR zero. If low ESR capacitors are used, this capacitor may be omitted. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

/c40 /c41ESR OUT R R2 R1C2 C R2 R1 /c180 /c43/c61 /c180 /c180 (10) /c40 /c41 EAK

20 LOWER UPPER

10 Z ZR g Z

/c180 /c43/c61 /c180 (11) COMP POLE COMP 1C 2 R/c61 /c112 /c180 /c180f (12) POLE LOAD OUT 1f 2 R C/c61 /c112 /c180 /c180 (13) Bootstrap for the N-Channel MOSFET Operating Near Maximum Duty Cycle TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 Next, calculate the value of the error amplifier gain setting resistor and capacitor. where NOTE: Once the filter and compensation component values have been established, laboratory measurements of the physical design should be performed to confirm converter stability. A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the MOSFET gate is derived from the voltage on this capacitor. To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW to GND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during light load operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces the SW node toward ground and allow the bootstrap capacitor to charge. Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge requirement of the MOSFET being used. DESIGN HINT For the bootstrap capacitor, use a ceramic capacitor with a value between nF and nF. NOTE: For 5-V input applications, connect PVDDx to BP directly. This connection bypasses the internal control circuit regulator and provides maximum voltage to the gate drive circuitry. In this configuration, shutdown mode IDD SDN is the same as quiescent IDD Q If the TPS5538x operates at maximum duty cycle, and if the input voltage is insufficient to support the output voltage (at full load or during a load current transient), then there is a possibility that the output voltage will fall from regulation and trip the output UV comparator. If this should occur, the TPS5538x protection circuitry declares a fault and enter a shut down-and-restart cycle. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

/c43/c100 /c61 /c43 (14) Light Load Operation IDCM = /c1801 /c180/c32/c100/c32/c180 TS V VIN OUT/c45 L (15) Inductor Current VOUT Ripple SW Waveform Steady State VIN = 12 V VOUT = 5 V SW Waveform VOUT Ripple Inductor Current Skipping VIN = 12 V VOUT = 5 V SW Node Ringing TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com DESIGN HINT Ensure that under ALL conditions of line and load regulation, there is sufficient duty cycle to maintain output voltage regulation. To calculate the operating duty cycle, use Equation where V DIODE is the forward voltage drop of the rectifier diode There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronous converter is to operate in the discontinuous conduction mode (DCM) at an average load current less than one-half of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function of input voltage, output voltage, inductor value, and operating frequency, as shown in Equation During discontinuous mode operation the commanded pulse width may become narrower than the capability of the converter to resolve. To maintain the output voltage within regulation, skipping switching pulses at light load conditions is a natural by-product of that mode. This condition may occur if the output capacitor is charged to a value greater than the output regulation voltage and there is insufficient load to discharge the capacitor. A by-product of pulse skipping is an increase in the peak-to-peak output ripple voltage. Figure 25. Steady State Figure 26. Skipping DESIGN HINT If additional output capacitance is required to reduce the output voltage ripple during DCM operation, be sure to recheck the Maximum Output Capacitance section. A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to decrease the voltage waveform ringing at the SW node to less than 5-V peak and of a duration of less than 30-ns. In addition to following good printed circuit board (PCB) layout practices, there are a couple of design techniques for reducing ringing and noise. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

www.ti.com SLUS818 SEPTEMBER 2008 SW Node Snubber Voltage ringing at the SW node is caused by fast switching edges and parasitic inductance and capacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, an R-C snubber may be used to dampen the ringing and ensure proper operation over the full load range. DESIGN HINT A series-connected R-C snubber between 330 pF and nF, R Ω connected from SW to GND reduces the ringing on the SW node. Bootstrap Resistor A small resistor in series with the bootstrap capacitor reduces the turn-on time of the internal MOSFET, thereby reducing the rising edge ringing of the SW node. DESIGN HINT A resistor with a value between Ω and Ω may be placed in series with the bootstrap capacitor to reduce ringing on the SW node. DESIGN HINT Placeholders for these components should be placed on the initial prototype PCBs in case they are needed. In the event of an overcurrent during soft-start on either output (such as starting into an output short), pulse-by-pulse current limiting and PWM frequency division are in effect for that output until the internal soft-start timer ends. At the end of the soft-start time, a UV fault is declared. During this fault, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This process ensures that both outputs discharge to GND in the event that overcurrent is on one output while the other is not loaded. The converter then enters a hiccup mode timeout before attempting to restart. Frequency Division describes a condition when an overcurrent pulse is detected and six clock cycles are skipped before a next PWM pulse is initiated, effectively dividing the operating frequency by six and preventing excessive current build up in the inductor. In the event of an overcurrent condition on either output after the output reaches regulation, pulse-by-pulse current limit is in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (that follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This design ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the other is not loaded. The converter then enters a hiccup mode timeout before attempting to restart. The overcurrent threshold for Output is set nominally at 4.5 The overcurrent level of Output is determined by the state of the ILIM2 pin. The ILIM setting of Output is not latched in place and may be changed during operation of the converter. Table Current Limit Threshold Adjustment for Output ILIM2 Connection OCP Threshold for Output BP 4.5 A nominal setting (floating) 3.0 A nominal setting GND 1.5 A nominal setting Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

www.ti.com DESIGN HINT The OCP threshold refers to the peak current in the internal switch. Be sure to add one-half of the peak inductor ripple current to the dc load current in determining how close the actual operating point is to the OCP threshold. It is possible to operate a TPS5538x from two supply voltages. If this application is desired, then the sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This level requirement ensures that the internal regulator and the control circuitry are in operation before PVDD1 supplies energy to the output. In addition, Output must be held in the disabled state EN1 high) until there is sufficient voltage on PVDD1 to support Output in regulation. (See the Operating Near Maximum Duty Cycle section.) The preferred sequence of events is: PVDD2 rises above the input UVLO voltage PVDD1 rises with Output disabled until PVDD1 rises above level to support Output regulation. With these two conditions satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1. DESIGN HINT An R-C delay on EN1 may be used to delay the startup of Output for a long enough period of time to ensure that PVDD1 can support Output load. It is possible to source PVDD1 from Output as depicted in Figure and Figure This configuration may be preferred if the input voltage is high, relative to the voltage on Output Figure 27. Schematic Showing Cascading PVDD1 from Output Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

www.ti.com SLUS818 SEPTEMBER 2008 Figure 28. Waveforms Resulting from Cascading PVDD1 from Output In this configuration, the following conditions must be maintained: Output must be of a voltage high enough to maintain regulation of Output under all load conditions. The sum of the current drawn by Output load plus the current into PVDD1 must be less than the overload protection current level of Output The method of output sequencing must be such that the voltage on Output is sufficient to support Output before Output is enabled. This requrement may be accomplished by: a a delay of the enable function b selecting sequential sequencing of Output starting after Output is in regulation The TPS5538x may be configured to operate as a two-channel multiphase converter capable of delivering up to Figure indicates the recommended pin connections. In this configuration, FB2 must be tied to BP for the maximum current configuration and the two output filter inductors must be the same value. Calculate R COMP and C COMP as outlined for a single channel output, then use one-half the R COMP value and two times the C COMP value as the compensation components. Contact the factory for further support. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

/c40 /c41 /c40 /c41

2 OUTPUTx

RMS(outputx ) OUTPUTx II D I 12 /c230 /c246 /c230 /c246 /c68/c231 /c247 /c231 /c247/c61 /c180 /c43 /c231 /c247 /c231 /c247/c231 /c247 /c232 /c248/c232 /c248 (16) TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com Figure 29. Multiphase Operation Schematic As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible. PVDD1 to GND: Use a 10- µ F ceramic capacitor PVDD2 to GND: Use a 10- µ F ceramic capacitor BP to GND: Use a 4.7- µ F to 10- µ F ceramic capacitor The overtemperature thermal protection limits the maximum power to be dissipated at a given operating ambient temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is limited by the maximum allowable junction operating temperature. The device junction temperature is a function of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature should reach the thermal shutdown level, the TPS5538x shuts off both PWMs and remains in this state until the die temperature drops below the hysteresis value, at which time the device restarts. The first step to determine the device junction temperature is to calculate the power dissipation. The power dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by each MOSFET is composed of conduction losses and output (switching) losses incurred while driving the external rectifier diode. To find the conduction loss, first find the RMS current through the upper switch MOSFET. where D is the duty cycle I OUTPUTx is the dc output current Δ I OUTPUTx is the peak ripple current in the inductor for Outputx Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

D(cond) RMS(outputx ) DS(on)P I R /c61 /c180 (17) 2PD(SW) = (V ) C fIN J S /c180 /c180 (18) D D(cond)output1 D(SW )output1 D(cond)output2 D(SW )outpu t2 INP P P P P V Iq/c61 /c43 /c43 /c43 /c43 /c180 (19) /c40 /c41J A D TH(pkg) TH(pad amb)T T P /c45/c61 /c43 /c180 /c113 /c43 /c113 (20) Power Derating TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 Notice the impact of the operating duty cycle on the result. Multiplying the result by the R DS(on) of the MOSFET gives the conduction loss. The switching loss is approximated by: where where C J is the prallel capacitance of the rectifier diode and snubber (if any) f S is the switching frequency The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal regulator. The temperature rise of the device junction depends on the thermal impedance from junction to the mounting pad (See the Package Dissipation Ratings table), plus the thermal impedance from the thermal pad to ambient. The thermal impedance from the thermal pad to ambient depends on the PCB layout (PowerPAD interface to the PCB, the exposed pad area) and airflow (if any). See the PCB Layout Guidelines, Additional References section. The operating junction temperature is shown in Equation The TPS5538x delivers full current at ambient temperatures up to +85 C if the thermal impedance from the thermal pad maintains the junction temperature below the thermal shutdown level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure illustrates the power derating for elevated ambient temperature under various airflow conditions. Note that these curves assume that the PowerPAD is properly soldered to the recommended thermal pad. (See the References section for further information.) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

0.4 0.6 0.8 1.0 1.8 0.2 0 20 40 60 140 80 100 120 TA - Ambient Temperature - °C PD - Power Dissipation - W 150 250 500 LFM 1.2 1.6 1.4 LFM = 0 LFM = 150 LFM = 250 LFM = 500 PowerPAD Package TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com POWER DISSIPATION vs AMBIENT TEMPERATURE Figure 30. Power Derating Curves The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. (See the Additional References section.) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

www.ti.com SLUS818 SEPTEMBER 2008 The layout guidelines presented here are illustrated in the PCB layout examples given in Figure and Figure Power pad must be connected to low current ground with available surface copper to dissipate heat. Recommend extending ground land beyond device package area. Connect the GND pin to the PowerPAD through a 10-mil (.010 in, or 0.0254 mm) wide trace. Place the ceramic input capacitors close to PVDD1 and PVDD2; Connect ceramic input capacitor ground to PowerPad with min 50mil wide trace. Maintain tight loop of wide traces from SW1 or SW2 through switch node, inductor, output capacitor and rectifier diode. Avoid using vias in this loop. Use wide ground connection from input capacitor to rectifier diode as close to power path as possible. Recommend directly under diode and switch node. Locate bootstrap capacitor close to BOOT pin to minimize gate drive loop. Locate feedback and compensation components over GND and away from switch node and rectifier diode to input capacitor ground connection. Locate snubber components close to rectifier diode with minimize loop area. Locate BP bypass capacitor very close to device. Recommend minimal loop area. Locate output ceramic capacitor close to inductor output terminal between inductor and electrolytic capacitors if used. Figure 31. Top Layer Copper Layout and Component Figure 32. Bottom Layer Copper Layout Placement Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

a 12-V to 5-V and 3.3-V Converter DESIGN EXAMPLE GENERAL www.ti.com The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dual non-synchronous buck regulator using the TPS55386 converter. Design Example and List of Materials is found at the end of this section. PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT INPUT CHARACTERISTICS V IN Input Voltage 9.6 12.0 13.2 V I IN Input Current V IN Nom, I OUT1 I OUT2 Max 2.4 2.6 A No Load Input Current V IN Nom, I OUT A mA V IN_UVLO Input UVLO I OUT Min to Max 4.0 4.2 4.4 V OUTPUT CHARACTERISTICS V OUT1 Output Voltage V IN Nom, I OUT Nom 4.80 5.0 5.20 V V OUT2 Output Voltage V IN Nom, I OUT Nom 3.20 3.3 3.40 V Line Regulation V IN Min to Max Load Regulation I OUT Min to Max V OUT_ripple Output Voltage Ripple V IN Nom, I OUT Max mVpp I OUT1 Output Current V IN Min to Max 3.0 A I OUT2 Output Current V IN Min to Max 3.0 A I OCP1 Output Over Current Channel V IN Nom, VOUT V OUT1 3.3 4.2 5.2 A I OCP2 Output Over Current Channel V IN Nom, VOUT V OUT2 3.3 4.2 5.2 A Transient Response Δ Vout from load transient Δ I OUT A at µ s 200 mV Settling Time To of Vout ms SYSTEM CHARACTERISTICS f SW Switching Frequency 500 600 700 kHz η pk Peak Efficiency V IN Nom, I OUT1 I OUT2 93% η Full Load Efficiency VI N Nom, I OUT1 I OUT2 Max 86% Top Operating Temperature Range V IN Min to Max, I OUT Min to Max C Figure 33. Design Example Schematic Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

/c40 /c41 OUT1 FD MAX1 FDIN min /c43 /c43/c61 /c61/c43 /c43 (21) /c40 /c41 OUT2 FD MAX2 FDIN min /c43 /c43/c61 /c61/c43 /c43 (22) /c40 /c41 OUT1 FD MIN1 FDIN m ax /c43 /c43/c61 /c61/c43 /c43 (23) /c40 /c41 OUT2 FD MIN2 FDIN max /c43 /c43/c61 /c61/c43 /c43 (24) /c40 /c41 /c40 /c41Lrip max OUT maxI 0.25 I 0.25 3.0 A 0.750 A/c61 /c180 /c61 /c180 /c61 (25) /c40 /c41 OUT1IN m ax m in 1 m in 1 Lrip1 (m ax) SW /c45 /c45/c187 /c180 /c180 /c61 /c180 /c180 /c61 /c109 (26) /c40 /c41 OUT2IN max min 2 min 2 Lrip2(max) SW /c45 /c45/c187 /c180 /c180 /c61 /c180 /c180 /c61 /c109 (27) /c40 /c41 OUT1IN max RIPPLE1 min1 1 SW /c45 /c45/c187 /c180 /c180 /c61 /c180 /c180 /c61 /c109 (28) /c40 /c41 OUT2IN max RIPPLE2 min 2 2 SW /c45 /c45/c187 /c180 /c180 /c61 /c180 /c180 /c61 /c109 (29) /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 2 22 2 2 21 1 1RIPPLE1 RIPPLE1L1 rms L1 avg OUT1 max 12 12 12I I I I I 3.0 0.661 A 3.0 A/c61 /c43 /c187 /c43 /c61 /c43 /c61 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 2 22 2 2 21 1 1RIPPLE2 RIPPLE2L2 rms L2 avg OUT2 max 12 12 12I I I I I 3.0 0.547 A 3.0 A/c61 /c43 /c187 /c43 /c61 /c43 /c61 TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 The bill of materials for this application is shown below in Table The efficiency, line and load regulation measurements from boards built using this design are shown in Figure and Figure Duty Cycle Estimation The duty cycle of the main switching FET of each channel is estimated by: Inductor Selection The peak-to-peak ripple is to be limited to 25% of the max output current, so that The minimum inductor size is estimated by: The standard inductor value of 8.2 µ H is selected for both Channel and Channel The resulting ripple currents are estimated by: RMS current through the inductor is approximated by: (30) (31) The RMS inductor current is 3.0 for both channels. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

/c40 /c41 /c40 /c41 1 1RIPPLEL1 peak OUT1 max 2 2I I I 3.0 A 0.661A 3.3 A/c187 /c43 /c61 /c43 /c61 (32) /c40 /c41 /c40 /c41 1 1RIPPLEL2 peak OUT2 max 2 2I I I 3.0 A 0.547 A 3.3 A/c187 /c43 /c61 /c43 /c61 (33) /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 IN max BR R min IN max V (34) /c40 /c41 /c40 /c41 /c40 /c41 MIN 1D1 avg OUT1 maxI I 1 D 3.0 A (1 0.397) 1.81A/c187 /c180 /c45 /c61 /c180 /c45 /c61 (35) /c40 /c41 /c40 /c41 /c40 /c41 MIN2D2 avg OUT2 maxI I 1 D 3.0 A (1 0.272) 2.18 A/c187 /c180 /c45 /c61 /c180 /c45 /c61 (36) /c40 /c41 /c40 /c41D peak L peakI I /c61 (37) /c40 /c41 /c40 /c41 FMD1 max D1 avgP V I 0.4 V 1.81 0.72 W/c187 /c180 /c187 /c180 /c61 (38) D2(max) FM D2(avg)P V I 0.4V 2.18 0.87W/c187 /c180 /c187 /c180 /c61 (39) /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 2TRAN MAX OUT1 min OUT1 OVER I L 1 A 8.2 HC 8.2 F5.0 V 0.2 VV V /c180 /c180 /c109/c61 /c61 /c61 /c109 /c180/c180 (40) /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 2TRAN MAX OUT 2 min OUT 2 OVER I L 1 A 8.2 HC 12.4 F3.3 V 0.2 VV V /c180 /c180 /c109/c61 /c61 /c61 /c109 /c180/c180 (41) TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com A DC current with 30% peak to peak ripple has an RMS current approximately 0.4% above the average current. The peak inductor current is estimated by: An 8.2- µ H inductor with a minimum RMS current rating of 3.0 A and minimum saturation current rating of 3.3 A must be selected. A Coilcraft MSS1048-822ML 8.2- µ 4.38-A inductor is chosen for both outputs. Rectifier Diode Selection A low forward voltage drop schottky diode is used as a rectifier diode to minimize power dissipation and maximize efficiency. Allowing 20% over VIN for ringing on the switch node, the rectifier diode s minimum reverse break-down voltage is given by: Reviewing 20-V and 30-V schottky diodes, the MBRS330T3, 30-V, 3-A diodes in an SMC package are selected for both channels. This diode has a forward voltage drop of 0.4 V at so the conduction power dissipation is: For this design, the maximum power dissipation is estimated as 0.72 W and 0.87 W respectively. Output Capacitor Selection Output capacitors are selected to support load transients and output ripple current. The minimum output capacitance to meet the transient specification is given by: Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

/c40 /c41 RIPPLE1 RIPPLE1 ( total) OUT1 SW m ax RIPPLE1 /c230 /c246 /c230 /c246/c45 /c45/c231 /c247 /c231 /c247/c180 /c180 /c180 /c109 /c180/c232 /c248 /c232 /c248/c61 /c61 /c61 /c87 (42) /c40 /c41 RIPPLE RIPPLE(total) OUT1 SW max RIPPLE /c230 /c246 /c230 /c246/c45 /c45/c231 /c247 /c231 /c247/c180 /c180 /c180 /c109 /c180/c232 /c248 /c232 /c248/c61 /c61 /c61 /c87 (43) /c40 /c41 /c40 /c41RMS _ CIN OUTI I D 1 D 3 A 0.5 1 0.5 1.5 A/c61 /c180 /c180 /c45 /c61 /c180 /c180 /c45 /c61 (44) FB FB BIAS OUT FB V RR V V /c180/c61 /c45 (45) /c40 /c41 6 6 7ON M 1 1.5 10 t (1.5 10 6.68 10 ) 66 IN OUT1 600000 600000F 5.82 10 /c45/c180 /c180 /c180 /c180 /c180 /c45/c45 /c61 /c61 /c61 /c180 /c230 /c246 /c45/c45/c230 /c246 /c180 /c43 /c180 /c180/c180 /c43 /c180 /c180 /c231 /c247/c231 /c247 /c109/c232 /c248/c232 /c248 TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 The maximum ESR to meet the ripple specification is given by: A single 22- µ F ceramic capacitor with approximately 2.5 m Ω of ESR is selected to provide sufficient margin for capacitance loss due to DC voltage bias. Input Capacitor Selection The TPS55386 datasheet recommends a µ F (minimum) ceramic bypass capacitor on each PVDD pin. While out of phase operation reduces input RMS current, the input capacitors must be sized to support the greater of the two input RMS currents, or 1.5A to allow operation when one channel is at maximum load and the other is un-loaded. The ceramic capacitor must handle the RMS input ripple current of the converter. The RMS current in the input capacitors is estimated by: One 1210 size 10- µ 25-V, X5R ceramic capacitor with a 2-m Ω ESR and a 2-A RMS current rating are selected to bypass each PVDD input. Higher voltage capacitors minimize capacitance loss under DC bias voltage, ensuring the capacitors have sufficient capacitance at their working voltage. Voltage Feedback The primary feedback divider resistor FB from V OUT to FB should be selected between k Ω and 100 k Ω to maintain a balance between power dissipation and noise sensitivity. For a 3.3-V and 5-V output, 20.5 k Ω is selected, so the lower resistor is given by: For R FB 20.5 k Ω and V FB 0.80V, R BIAS1 3.90k Ω and R BIAS2 6.5k Ω (R4 3.83k Ω and 6.49 k Ω selected) for 5.0 V and 3.3 V respectively. Compensation Components The TPS55386 controller uses an internal transconductance error amplifier, which compares the feedback voltage to the internal 0.80-V reference and sources a current proportional to the resulting error out of the COMP pin. A series resistor and capacitor to ground generate an integrator with zero while a high frequency capacitor provides a second pole to reduce the high frequency gain. The compensation loop components are selected by the following equations with the 5.0-V output used in example calculations: Calculate the modulator gain at DC: (46) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 4 3 4 IN m 1 6 3 6 IN LOAD1 V F 2 10 13.2 5.82 10 2 10fc 4.63 V Fm 50 10 13.2 5.82 10 50 101 1 R 1.67 /c45 /c45 /c45 /c45 /c180 /c180 /c180 /c180 /c180 /c180 /c180/c61 /c61 /c61 /c230 /c246 /c230 /c246 /c180 /c180 /c180 /c180 /c180 /c180 /c180/c231 /c247 /c231 /c247/c43 /c43 /c231 /c247 /c231 /c247 /c87/c232 /c248 /c232 /c248 (47) EA1 CO LOAD1 OUT1 fc 4.65K 20 log 20 log 5.80 dB1 2 f R C 1 2 35 kHz 1.67 22 F /c230 /c246 /c230 /c246/c61 /c45 /c180 /c61 /c45 /c180 /c61/c231 /c247 /c231 /c247/c43 /c112 /c180 /c180 /c180 /c43 /c112 /c180 /c180 /c87 /c180 /c109 /c232 /c248/c232 /c248 (48) /c40 /c41 /c40 /c41 EAK 5.80 dB 20 20LOWER UPPER COMP1 M LOWER /c180 /c43 /c180 /c87 /c43 /c87/c61 /c61 /c61 /c87 /c222 /c61 /c87 /c180 /c109 /c180 /c87 (49) ZERO1 OUT1 LOAD1 1 1f 4.4 kHz2 C R 2 22 F 1.67/c61 /c61 /c61/c112 /c180 /c180 /c112 /c180 /c109 /c180 /c87 (50) COMP1 POLE1 COMP1 1 1C 967 pF C21 1nF2 f R 2 4.4 kHz 3.83 k/c61 /c61 /c61 /c222 /c61/c112 /c180 /c180 /c112 /c180 /c180 /c87 (51) HF1 CO COMP 1 1C 29.6 pF C23 33 pF2 4 f R 2 4 35 kHz 38.3 k/c61 /c61 /c61 /c222 /c61/c112 /c180 /c180 /c180 /c112 /c180 /c180 /c180 /c87 (52) TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com Then calculate the converter gain at DC: Calculate the required error amplifier gain at the desired crossover frequency of kHz: Then compensation resistor at the output of the error amplifier is: Calculate the required compensation zero frequency: Then calculate the compensation capacitor: The high-frequency pole is placed at eight times the crossover frequency: Boot-Strap Capacitor To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 47-nF boot strap capacitor is used. ILIM2 The current limit must be set above the peak inductor current I Lpeak Comparing I Lpeak to the available minimum current limits, I LIM is connected to BP for a 3.6-A minimum current limit. SEQ The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tied together, the two supplies start-up ratio-metrically. SEQ could also be connected to BP or GND to provide sequential start-up. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 2 2 2 CON 1 OUTDS on QSW RMS DS onP R I R I D 0.085 3 A 0.540 0.562 W/c61 /c180 /c187 /c180 /c180 /c61 /c87 /c180 /c180 /c61 (53) /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 2 2 2 CON2 OUTDS on QSW RMS DS onP R I R I D 0.085 3 A 0.370 0.465 W/c61 /c180 /c187 /c180 /c180 /c61 /c87 /c180 /c180 /c61 (54) /c40 /c41/c40 /c41 /c40 /c41 2Dj OSS SWIN max SW1 SW 2 V (C C ) f 13.2 (200 pF 250 pF) 600 kHzP P 23.5 mW2 2 /c180 /c43 /c180 /c180 /c43 /c180/c61 /c187 /c61 /c61 (55) /c40 /c41 /c40 /c41 /c40 /c41REG DD BP BP IN max IN maxP I V I V V 5 mA 13.2 V 66 mW/c187 /c180 /c43 /c180 /c45 /c61 /c180 /c61 (56) DESIGN EXAMPLE TEST RESULTS 0.15 1.15 100 h – Efficiency – % VIN (V) VIN = 14 V VIN = 12 V VIN = 8 V ILOAD – Load Current – A VOUT= 5 V ILOAD – Load Current – A 100 h – Efficiency – % VIN (V) VIN = 14 VVIN = 12 V VIN = 8 V VOUT= 3.3 V TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 Power Dissipation The power dissipation in the TPS55386 is from FET conduction losses, switching losses and regulator losses. Conduction losses are estimated by: The switching losses are estimated by: The regulator losses are estimated by: Total power dissipation in the device is the sum of conduction and switching losses for both channels plus regulator losses, and are estimated to total 1.2 EFFICIENCY EFFICIENCY vs vs LOAD CURRENT LOAD CURRENT Figure 34. Figure 35. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

www.ti.com Table TPS55386 Design Example List of Materials REFERENC E QTY VALUE C2, C14 µ F Capacitor, Ceramic, 6.3V, X5R, 20% 1206 C3216X5R0J226M TDK C3, C13 470 pF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std C4, C11 0.047 µ F Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std C5, C10 µ F Capacitor, Ceramic, 25V, X5R, 20% 1210 C3225X5R1E106M TDK C12 4.7 µ F Capacitor, Ceramic, 10V, X5R, 20% 0805 Std Std C9, 1.0 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std pF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std pF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std D1, MBRS330T3 Diode, Schottky, 3-A, 30-V SMC MBRS330T3 OnSemi L1, 8.2 µ H Inductor, SMT, 4.38A, 20milliohm 0.402 x 0.394 inch MSS1048-822L Coilcraft 23.7 k Ω Resistor, Chip, 1/16W, 0603 Std Std 38.3 k Ω Resistor, Chip, 1/16W, 0603 Std Std R3, R12 20.5 k Ω Resistor, Chip, 1/16W, 0603 Std Std R2, R11 Ω Resistor, Chip, 1/16W, 0603 Std Std 3.83 k Ω Resistor, Chip, 1/16W, 0603 Std Std R10 6.49 k Ω Resistor, Chip, 1/16W, 0603 Std Std TPS55386PWP IC, Dual 600kHz Non-Sync BUCK with Interal HTSSOP-16 TPS55386PWP TI FET Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

Configuration: V to V at A then 3.3 V at A U ILOAD – Load Current – A 100 /c104– Efficiency – % VOUT= 3.3 V 3.3 VOUT (V) VOUT= 12 V TPS55383 TPS55386 www.ti.com SLUS818 SEPTEMBER 2008 This example illustrates a cascaded configuration. To accommodate the low duty cycle of a 24-V to 3.3-V supply, PVDD1 is connected to VOUT2, a 12-V output. VOUT2 is used as the source supply for VOUT1. The sequence pin is connected to BP, ensuring the 12-V supply is in regulation before the 3.3-V is allowed to turn on. Figure 36. Design Example TPS55386 in a Cascaded Configuration EFFICIENCY vs LOAD CURRENT Figure 37. Figure 38. Design Example Outputs and Switch Nodes Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

V to 5.0 V at A 0 3 1 64 7 ILOAD – Load Current – A 100 /c104– Efficiency – % VOUT= 5 V 2 5 TPS55383 TPS55386 SLUS818 SEPTEMBER 2008 www.ti.com The combination of current mode control and a transconductance amplifier allows the TPS55386 to serve as a single-output 2-phase supply. This configuration allows this part to serve as a 6-A non-synchronous converter at an effective 1.2 MHz. COMP2 is connected to COMP1 and FB2 is connected to BP. While not implemented in this example, EN2 could be used to disable Channel at light load, improving efficiency. Figure 39. Design Example TPS55386 as a Phase Non-Synchronous Buck Converter EFFICIENCY vs LOAD CURRENT Figure 40. Figure 41. Design Example Output and Switch Nodes Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS55383 TPS55386

www.ti.com SLUS818 SEPTEMBER 2008 The following devices have characteristics similar to the TPS55383/TPS55386 and may be of interest. Table Devices Related to the TPS55383 and TPS55386 TI LITERATURE DEVICE Input, 1.6-A Non-Synchronous Buck Converter TPS54283 SLUS749 2-A Dual Non-Synchronous Converter with Integrated High-Side MOSFET TPS54286 TPS54383 SLUS774 3-A Dual Non-Synchronous Converter with Integrated High-Side MOSFET TPS54386 3.5 V to Single 3-A Non-Synchronous Buck Converter with Integrated High-Side SLVS839 TPS54331 MOSFET These references, design tools and links to additional references, including design software, may be found at http:www.power.ti.com Table References TI LITERATURE Converters. SEM1500 Topic 2002 Seminar Series SLVA057 Understanding Buck Power Stages in Switchmode Power Supplies SLUP173 Designing Stable Control Loops. SEM 1400, 2001 Seminar Series The following pages outline the mechanical dimensions of the 16-Pin PWP package and provide recommendations for PCB layout. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS55383 TPS55386

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS55383PWPR HTSSOP PWP 16 2000 367.0 367.0 38.0 TPS55386PWPR HTSSOP PWP 16 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 2

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