SLM4681

LTM4681_V01 AD | Alldatasheet

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Technical content

Rev. AFor more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Quad 31.25A or Single 125A µModule Regulator with Digital Power System Management The LTM®4681 is a quad 31.25A or single 125A step- down µModule ® (power module) DC/DC regulator fea - turing remote configurability and telemetry-monitoring of power management parameters over PMBus. The LTM4681 is comprised of digitally programmable analog control loops, precision mixed-signal circuitry, EEPROM, power MOSFETs, inductors and supporting components. The LTM4681’s 2-wire serial interface allows outputs to be margined, tuned and ramped up and down at pro - grammable slew rates with sequencing delay times. True in put current sense, output currents and voltages, output power, temperatures, uptime and peak values are read - able. Custom configuration of the EEPROM contents is not required. At start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin- strapping resistors. The LTpowerPlay® GUI and DC1613 USB-to-PMBus converter and demo kits are available. The LTM4681 is offered in a 15mm × 22mm × 8.17mm BGA package available with SnPb or RoHS compliant terminal finish.

APPLICATIONS

n Quad Digitally Adjustable Analog Loops with Digital Interface for Control and Monitoring n Wide Input Voltage Range: 4.5V to 16V n Output Voltage Range: 0.5V to 3.3V n ±0.5% Maximum DC Output Error Over Temperature n ±4% Current Readback Accuracy: 0°C to 125°C n Integrated Input Current Sense Amplifier n 400kHz PMBus-Compliant I2C Serial Interface n Supports Telemetry Polling Rates Up to 125Hz n Integrated 16-Bit ∆Σ ADC n Parallel and Current Share Multiple Modules n 15mm × 22mm × 8.17mm BGA Package Readable Data: n Input and Output Voltages, Currents, and Temperatures n Running Peak Values, Uptime, Faults and Warnings n Onboard EEPROM Fault Log Record Writable Data and Configurable Parameters: n Output Voltage, Voltage Sequencing and Margining n Digital Soft-Start/Stop Ramp, Program Analog Loop n OV/UV/OT , UVLO, Frequency and Phasing n Multi-Rail Processor Power, Configurable Core Power All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide. Quad 31.25A µModule Regulator with Digital Interface for Control and Monitoring Channel Efficiency vs Load Current POWER GOOD MONITORS FAUL T INTERRUPTS ON/OFF CONTROL 4.5V TO 16V 4.5V TO 16V CBULK 22µF ×622µF LOAD 1.5V AT 31.25A CBULKLOAD 1.2V AT 31.25A CBULKLOAD 1V AT 31.25A CBULKLOAD 0.9V AT 31.25A CER CER CER CER

4681 TA01a

PGOOD0,1,2,3 WP_23 WP_01 SYNC_01 SYNC_23 SHARE_CLK_01 SHARE_CLK_23 ALERT_01 ALERT_23 SDA_01 SDA_23 SCL_01 GND SGND_23 SGND_01 SCL_23 FAUL T0,1,2,3 RUN0,1,2,3 RUNP V IN_VBIAS SVIN_23 VIN23 IN_23– IN_23+ SVIN_01 VIN01 IN_01– IN_01+ VOSNS3– VOSNS3+ VOUT3 VOSNS2– VOSNS2+ VOUT2 VOSNS1– VOSNS1+ VOUT1 VOSNS0– VOSNS0+ VOUT0 L TM4681 I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER SYNCHRONIZATION TIME BASE REGISTER WRITE PROTECTION FOR COMPLETE CIRCUIT SEE FIGURE 48 (FROM 4.5V TO 5.5V CONNECT VIN, SVIN, AND INTVCC TOGETHER) RSENSE1 RSENSE2 OUTPUT CURRENT (A) EFFICIENCY (%) 2515

4681 TA01b

12VIN, 0.9VOUT, 250kHz 12VIN, 1.0VOUT, 250kHz 12VIN, 1.2VOUT, 350kHz 12VIN, 1.5VOUT, 425kHz Configurable Output Array 31.25A 31.25A 31.25A 31.25A 62.5A 31.25A 31.25A 93.75A 31.25A 62.5A 62.5A 125A

Rev. A For more information www.analog.com TABLE OF CONTENTS T

Description

T T Operation P EE P S Ti V Sh L S P O IN O utput Current Sensing and Sub Milliohm DCR I P I RCO T able 1. VOUTn _CFG Pin Strapping Look-Up Table for the LTM4 681’s Output Voltage, Coarse Setting (Not Applicable if MFR_CONFIG_ALL[6] = T able 2. VTRIMn_CFG Pin Strapping Look-Up Table for the LTM4681’s Output Voltage, Fine Adjustment Setting (Not Applicable if MFR_ Table 3. FSWPH_nn_CFG Pin Strapping Look-Up or 2,3 Channels, set top resistor to 14.3k.

Table 7. PMBus Commands Summary (Note: The

Rev. A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Terminal Voltages: VINnn (Note 4), SVIN_nn, IIN_nn+, IIN_nn−, 18V, −5V to 18V Transient 3V to 5.5V FSWPH_nn_CFG, VOUTn_CFG, FAULTn, SYNC_nn, SHARE_CLK_nn, 3V to 2.7V 3V to 0.8V n = 0, 1, 2, 3 and nn = 01, 23 VDD33_nn and VDD25_nn are outputs not to be driven. Temperatures Internal Operating Temperature Range (Notes 2, 13, 16, 17) C to 125°C Peak Solder Reflow Package Body Temperature ... 24 5°C (Note 1) 5 6 7 8 9 10 11 12 13 141 4 3 2 15 A B C D E F G H K J L T R P N M U AB AA Y W V VOUT0 GND GND GND GND RUN0 RUN1 FSWPH_01_CFGVTRIM3_CFG VOUT0_CFG VOUT1_CFG TOP VIEW BGA PACKAGE 330-LEAD (15mm × 22mm × 8.17mm) TJMAX = 125°C, θJCtop = 2.8°C/W , θJCbottom = 1.4°C/W , θJA = 4.73°C/W VOUT1 VOUT2 VOUT3 SW0 SW1 SW3 VIN23 VIN01 SW2 ASEL_01 SHARE_CLK_01VTRIM0_CFG VDD25_01 VTRIM1_CFG VIN_VBIAS COMP1b VDD33_01 VOSNS1– COMP1a VOSNS1+ VOSNS2+ INTVCC_01 SVIN_01 SCL_23 ALERT_23 RUN3 SYNC_23 SDA_23 PGOOD0 PGOOD1 COMP2b COMP2a RUNP FAUL T0 ALERT_01 SYNC_01 TSNS0TSNS1 TSNS3 SVIN_23 INTVCC_23 COMP0b COMP0a IN_01+ VOSNS0– IN_01– IN_23– VOSNS2– TSNS2 IN_23+ VOSNS0+ PGOOD2 VOSNS3+ PGOOD3 VOSNS3– FAUL T2 COMP3a FAUL T3 COMP3b VDD33_23 WP_23 VBIAS SGND01 SGND23 FAUL T1 RUN2 SDA_01 VOUT3_CFG SCL_01 WP_01 VDD25_23 VTRIM2_CFGFSWPH_23_CFG VOUT2_CFG SHARE_CLK_23 ASEL_23 NOTE: 1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS, WEIGHT = 10g. 2) θJA VALUE IS OBTAINED WITH DEMO BOARD. 3) REFER TO PAGES 71, 75, 76 FOR LAB MEASUREMENT AND DERATING INFORMATION. ORDER INFORMATION PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4681EY#PBF SAC305 (RoHS) LTM4681Y BGA 4 –40°C to 125°CLTM4681IY#PBF LTM4681Y LTM4681IY SnPb (63/37) LTM4681Y e0

• Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
• LGA and BGA Package and Tray Drawings

Rev. AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, RUNP = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VINnn Input DC Voltage Test Circuit 1 Test Circuit 2; VIN_OFF < VIN_ON = 4V l l 5.75 4.5 5.75 V V VOUTn Range of Output Voltage Regulation for Each Channel V OUTn Differentially Sensed on VOSNSn+/VOSNSn– Pin-Pair; Commanded by Serial Bus or with Resistors Present at Start-Up on V OUTn_CFG l 0.5 3.34 V V VOUTn(DC) Output Voltage, Total Variation with Line and Load for Each Channel Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) V OUTn Commanded to 1.000V, VOUTn Low Range (MFR_PWM_MODEn[1] = 1b) (Notes 5, 6) l 0.995 0.985 1.000 1.000 1.005 1.015 V V V UVLO Undervoltage Lockout Threshold, When V IN < 4.3V VINTVCC_nn Falling VINTVCC_nn Rising 3.55 3.90 V V Input Specifications I INRUSH(VINn) Input Inrush Current at Start-Up Test Cir cuit 1, VOUTn =1V, VIN = 12V; No Load Besides Capacitors; TON_RISEn = 3ms 400 mA IQ(SVIN) Input Supply Bias Current Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b RUNn = 3.3V Shutdown, RUN0 = RUN1 = 0V mA mA I S(VINn,PSM) Input Supply Current in Pulse- Skipping Mode Operation Pulse-Skipping Mode, MFR_PWM_MODEn[0] = 0b, I OUTn = 100mA 20 mA IS(VINn,FCM) Input Supply Current in Forced- Continuous Mode Operation Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b 12V to 1V I OUTn = 31.25A 2.89 A IS(VINn,SHUTDOWN) Input Supply Current in Shutdown Shutdown, RUNn = 0V 50 µA Output Specifications IOUTn Output Continuous Current Range Each Channel (Note 6) Utilizing MFR_PWM_MODE[7] = 1 and Using OUT = 40A for IOUT_OC_FAULT_LIMIT, Page 98 0 31.25 A ∆VOUTn(LINE) VOUTn Line Regulation Accuracy Each Channel Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) SV IN and VINn Electrically Shorted Together and INTVCC Open Circuit; IOUTn = 0A, 5.75V ≤ VIN ≤ 16V, VOUT Low Range (MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH = 350kHz (Note 5) l 0.03 0.03 ±0.2 %/V %/V ∆VOUTn(LOAD) VOUTn Load Regulation Accuracy Each Channel Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) 0A ≤ I OUTn ≤ 31.25A, VOUT Low Range, (MFR_PWM_ MODEn[1] = 1b) (Notes 5, 6) l 0.03 0.2 0.5 V OUTn(AC) Output Voltage Ripple 10 mVP-P fS (Each Channel) V OUTn Ripple Frequency FREQUENCY_SWITCH Set to 350kHz (0xFABC) l 320 350 370 kHz ∆VOUTn(START) Turn-On Overshoot TON_RISEn = 3ms (Note 12) 8 mV tSTART Turn-On Start-Up Time Time from VIN Toggling from 0V to 12V to Rising Edge PGOODn. TON_DELAYn = 0ms, TON_RISEn = 3ms l 30 ms tDELAY(0ms) Turn-On Delay Time Time from First Rising Edge of RUNn to Rising Edge of PGOODn . TON_DELAYn = 0ms, TON_RISEn = 3ms, VIN Having Been Established for at Least 70ms l 2.75 3.3 3.8 ms ∆VOUTn(LS) Peak Output Voltage Deviation for Dynamic Load Step Load: 10A to 20A and 20A to 10A at 10A/µs, V OUTn = 1.2V, VIN = 12V (Note 12) See T ransient Graph 50 mV

Rev. A For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, RUNP = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tSETTLE Settling Time for Dynamic Load Step per Channel Load: 10A to 20A and 20A to 10A at 10A/µs, V OUTn = 1.2V, VIN = 12V (Note 12) See T ransient Graphs 25 µs IOUTn(OCL_PK) Output Current Limit, Peak High Range per Channel Cycle-by-Cycle Inductor Peak Current Limit Inception, Utilizing MFR_PWM_MODE[7] = 1, Using ~I OUT = 34A for IOUT_OC_FAULT_LIMIT, Page 98 46 A IOUTn(OCL_AVG) Output Current Limit, Time Averaged per Channel Time-Averaged Output Inductor Current Limit Inception Threshold, Commanded by IOUT_OC_FAULT_LIMIT n (Note 12) Utilizing MFR_PWM_MODE[7] = 1, Using ~I OUT = 40A, Page 98 40; See IO-RB-ACC Specification (Output Current Readback Accuracy) Control Section VFBCMn Channel 0–3 Feedback Input Common Mode Range VOSNSn– Valid Input Range (Referred to SGND) VOSNSn+ Valid Input Range (Referred to SGND) l l –0.1 0.3 3.6 V V V OUT-RNGL Full-Scale Command Voltage, Range Low (0.5V to 2.75V, Note 15) per Channel V OUTn Commanded to 2.750V, MFR_PWM_MODEn[1] = 1b Set Point Accuracy Resolution LSB Step Size −0.5 2.75 0.688 +0.5 V Bits mV VOUT-RNGH Full-Scale Command Voltage, Range High (0.5V to 3.6V, Note 15) per Channel V OUTn Commanded to 3.6V, MFR_PWM_MODEn[1] = 0b Limit Design to 3.6V Operating for Module Set Point Accuracy Resolution LSB Step Size −0.5 3.6 1.375 +0.5 V Bits mV R VSNSn+ VOSNSn+ Impedance to SGND 0.05V ≤ V VOSNSn+ – VSGND ≤ 3.3V 50 kΩ tON(MIN) Minimum On-Time (Note 8 ) per Channel 60 ns RCOMPn Resolution Compensation Resistor R TH(MAX) Compensation Resistor RTH(MIN) MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1, Note Section) 0.5 Bits kΩ kΩ g mn Resolution Error Amplifier g m(MAX) Error Amplifier gm(MIN) LSB Step Size COMPn = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7 3 5.76 0.68 Bits mmho mmho mmho Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors) NOV/UV_COMP Resolution, Output Voltage Supervisors (Notes 14, 15) 9 Bits V OV-RNG Output OV Comparator Threshold Detection Range High Range Scale, MFR_PWM_MODE n[1] = 0b Low Range Scale, MFR_PWM_MODE n[1] = 1b 0.5 3.6 2.7 V V V OUSTP Output OV and UV Comparator Threshold Programming LSB Step Size (Note 15) High Range Scale, MFR_PWM_MODE n[1] = 0b Low Range Scale, MFR_PWM_MODE n[1] = 1b 11.2 5.6 mV mV V OV-ACC-n Output OV Comparator Threshold Accuracy Channel 0 – 3 (See Note 14) ≤ VVOSNSn+ – VVOSNSn– ≤ 2.7V, MFR_PWM_MODE[1] = 1b 0.5V ≤ VVOSNSn+ – VVOSNSn– ≤ 1V, MFR_PWM_MODE[1] = 1b 2.0V ≤ VVOSNSn+ – VVOSNSn– ≤ 3.6V, MFR_PWM_MODE[1] = 0b l l l ±1.5 ±2.5 ±1.5 V UV-RNGn Output UV Comparator Threshold Detection Range High Range Scale, MFR_PWM_MODEn[1] = 0b Low Range Scale, MFR_PWM_MODEn[1] = 1b 0.5 3.6 2.7 V V V UV-ACCn Output UV Comparator Threshold Accuracy Channel 0 – 3 (See Note 14) ≤ VVOSNSn+ – VVOSNSn– ≤ 2.7V, MFR_PWM_MODE[1] = 1b 0.5V ≤ VVOSNSn+ – VVOSNSn– ≤ 1V, MFR_PWM_MODE[1] = 1b 2.0V ≤ VVOSNSn+ – VVOSNSn– ≤ 3.6V, MFR_PWM_MODE[1] = 0b l l l ±1.5 ±2.5 ±1.5

Rev. AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, RUNP = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPROP-OV Output OV Comparator Response Times Overdrive to 10% Above Programmed Threshold 100 µs tPROP-UV Output UV Comparator Response Times Under Drive to 10% Below Programmed Threshold 100 µs Analog OV/UV SV IN_nn Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF) NSVIN-OV/UV-COMP SVIN_nn OV/UV Comparator Threshold-Programming Resolution (Notes 14, 15) 9 Bits SVIN-OU-RANGE SVIN_nn OV/UV Comparator Threshold-Programming Range Limited to Abs Max = 18V for LTM4681 Module l 4.5 18 V SVIN-OU-STP SVIN_nn OV/UV Comparator Threshold- Programming LSB Step Size (Note 15) 76 mV SVIN-OU-ACC SVIN_nn OV/UV Comparator Threshold Accuracy 9V < SVIN ≤ 16V 4.5V ≤ SVIN ≤ 9V l l ±270 mV tPROP-SVIN-HIGH-VIN SVIN_nn OV/UV Comparator Response Time, High VIN Operating Configuration Test Circuit 1, and: VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V l l 100 100 µs µs t PROP-SVIN-LOW-VIN SVIN_nn OV/UV Comparator Response Time, Low VIN Operating Configuration Test Circuit 2, and: VIN_ON = 4.5V; SV IN Driven from 4.225V to 4.725V VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V l l 100 100 µs µs Channeln Output Voltage Readback (READ_VOUTn) NVO-RB Output Voltage Readback Resolution and LSB Step Size (Note 15) 16 244 Bits µV V O-F/S Output Voltage Full-Scale Digitizable Range V RUNn = 0V (Note 15), Limited to 3.6V Max Operating 8 V VO-RB-ACC Output Voltage Readback Accuracy Channel n: 1V ≤ V VOSNS+ – VVOSNS– ≤ 3.3V Channel n: 0.5V ≤ VVOSNS+ – VVOSNS– < 1V l l Within ±0.5% of Reading Within ±5mV of Reading tCONVERT-VO-RB Output Voltage Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x01 through 0x0C (Notes 9, 15) MFR_ADC_CONTROL Section ms ms ms Input Voltage (SV IN_nn ) Readback (READ_VIN) NSVIN-RB Input Voltage Readback Resolution and LSB Step Size (Notes 10, 15) Limited to Abs Max = 18V for LTM4681 Module 15.625 Bits mV SVIN-F/S Input Voltage Full-Scale Digitizable Range (Notes 11, 15) 43 V SV IN-RB-ACC Input Voltage Readback Accuracy READ_VIN, 4.5V ≤ SV IN ≤ 16V l Within ±2% of Reading tCONVERT-SVIN-RB Input Voltage Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x01 (Notes 9, 15) ms ms Channel n Output Current (READ_IOUT n), Duty Cycle (READ_DUTY_CYCLEn), and Computed Input Current (MFR_READ_IINn) Readback NIO-RB Output Current Readback Resolution and LSB Step Size (Notes 10, 15) 10 34.1 Bits mA

Rev. A For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, RUNP = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IO-F/S Output Current Full-Scale Digitizable Range (Note 15) Utilizing MFR_PWM_MODE[7] = 1, Using IOUT_OC_ FAULT_LIMIT = 61A, Page 98 54 A IO-RB-ACC Output Current, Readback Accuracy READ_IOUTn, Channels 0–3, 0 ≤ I OUTn ≤ 30A, Forced-Continuous Mode, MFR_PWM_MODEn[0] = 1b 0°C to 125°C –40°C to 125°C See Histograms in Typical Performance Characteristics (Note 12) l Within 1.25A of Reading Within 1.5A of Reading IO-RB(31.25A) Full Load Output Current Readback (Note 12). See Histograms in Typical Performance Characteristics 31.25 A tCONVERT-IO-RB Output Current Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x06 (C H0,2 IOUT) or 0x0A (CH1,3 IOUT) (Notes 9, 15) See MFR_ADC_CONTROL SECTION ms ms Input Current Readback N Resolution (Note 10) 10 Bits V IINSTP LSB Step Size Full-Scale Range = 16mV LSB Step Size Full-Scale Range = 32mV LSB Step Size Full-Scale Range = 64mV Gain = 8, 0V ≤ |VIIN+ – VIIN–| ≤ 5mV Gain = 4, 0V ≤ |VIIN+ – VIIN–| ≤ 20mV Gain = 2, 0V ≤ |VIIN+ – VIIN–| ≤ 50mV 15.26 30.52 µV µV µV IIN_TUE Total Unadjusted Error Gain = 8, 2.5mV ≤ |VIIN+ – VIIN–| (Note 7) Gain = 4, 4mV ≤ |VIIN+ – VIIN–| (Note 7) Gain = 2, 6mV ≤ |VIIN+ – VIIN–| (Note 7) l l l ±1.3 ±1.2 V OS Zero-Code Offset Voltage (Note 15) ±50 µV tCONVERT Update Rate (Notes 9,15) See MFR_ADC_CONTROL SECTION for Faster Update Rates 90 ms Supply Current Readback N Resolution (Note 10) 10 Bits V ICHIPSTP LSB Step Size Full-Scale Range = 256mV Offboard 1Ω Resistor 244 µV ICHIP_RB ICHIP Readback SVIN_nn Current ±50 mA tCONVERT Update Rate (Notes 9,15) See MFR_ADC_CONTROL SECTION for Faster Update Rates 90 ms Temperature Readback (T0, T1) T RES-RB Temperature Readback Resolution Channel n, and Controller (Note 15) 0.25 °C T0_TUE External Temperature Total Unadjusted Readback Error Supporting Only ∆VBE Sensing 2.5 T1_TUE Internal TSNS TUE VRUNn = 0.0, fSYNC = 0kHz (Note 7) ±1 °C tCONVERT Update Rate (Note 9) MFR_ADC_CONTROL = 0x04 or 0x0C (Notes 9, 15) ms ms INTVCC_nn Regulator/VBIAS VINTVCC_nn Internal VCC Voltage No Load 6V ≤ SV IN_nn ≤ 16V l 5.25 5.5 5.75 V VLDO_INT INTVCC Load Regulation ICC = 0mA to 20mA, 6V ≤ SVIN_nn ≤ 16V 0.5 ±2 % VIN_VBIAS Input Range for VIN_VBIAS 4.5 16 V RUNP VBIAS Enable RUNP Rising 0.8 0.85 V VBIAS 5.5V Internal Regulator 7V ≤ VIN_VBIAS ≤ 16V 5.25 5.5 5.75 V

Rev. AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, RUNP = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SVIN_THR VSVIN_nn Threshold to Enable VBIAS Switchover SVIN_nn Rising 7 7.5 V SVIN_THF VSVIN_nn Threshold to Disable VBIAS Switchover SVIN_nn Falling 6.5 V VDD33_nn Regulator VVDD33nn Internal VDD33 Voltage 4.5V < VINTVCC_nn 3.2 3.3 3.4 V ILIM VDD33 Current Limit VDD33_nn = GND, VIN_nn = INTVCC_nn = 4.5V 100 mA VVDD33_OV VDD33 Overvoltage Threshold (Note 15) 3.5 V VVDD33_UV VDD33 Undervoltage Threshold (Note 15) 3.1 V VDD25_nn Regulator VVDD25nn Internal VDD25 Voltage 2.5 V ILIM VDD25 Current Limit VDD25_nn = GND, VIN_nn = INTVCC_nn = 4.5V 80 mA Oscillator and Phase-Locked Loop (PLL) fRANGE PLL SYNC Range Synchronized with Falling Edge of SYNC l 250 1000 kHz fOSC Oscillator Frequency Accuracy Frequency Switch = 250kHz to 1000kHz (Note 15) l ±7.5 % VTH(SYNC_nn) SYNC Input Threshold (Note 15) V SYNC Falling VSYNC Rising 1.5 V V VOL(SYNC_nn) SYNC Low Output Voltage ILOAD = 3mA (Note 15) 0.2 0.4 V ILEAK(SYNC_nn) SYNC Leakage Current in Slave Mode 0V ≤ VPIN ≤ 3.6V ±5 µA θSYNC-θ0,-θ2 SYNC to Ch0, Ch2 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of SW0, SW2 MFR_PWM_CONFIG[2:0] = 0,2,3 MFR_PWM_CONFIG[2:0] = 5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0]= 4,6 120 Deg Deg Deg Deg θSYNC- θ1,-θ3 SYNC to Ch1, Ch3 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of SW1, SW3 MFR_PWM_CONFIG[2:0] = 3 MFR_PWM_CONFIG[2:0] = 0 MFR_PWM_CONFIG[2:0] = 2,4,5 MFR_PWM_CONFIG[2:0] = 1 MFR_PWM_CONFIG[2:0] = 6 120 180 240 270 300 Deg Deg Deg Deg Deg EEPROM Characteristics Endurance (Note 13) 0°C ≤ T J ≤ 85°C During EEPROM Write Operations l 10,000 Cycles Retention (Note 13) TJ < 125°C l 10 Years Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < T J < 85°C During EEPROM Write Operation 440 4100 ms Leakage Current SDA_ nn, SCL_nn, ALERT_nn, RUNn IOL Input Leakage Current OV ≤ VPIN ≤ 5.5V l ±5 µA Leakage Current FAUL Tn, PGOODn I GL Input Leakage Current OV ≤ VPIN ≤ 3.6V l ±2 µA Digital Inputs SCL_nn, SDA_nn, RUNn V IH Input High Threshold Voltage l 1.35 V VIL Input Low Threshold Voltage l 0.8 V VHYST Input Hysteresis SCL, SDA 0.08 V CPIN Input Capacitance 10 pF

Rev. A For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V, RUNP = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Input WP_nn IPUWP Input Pull-Up Current WP 10 µA Open-Drain Outputs SCL_nn, SDA_nn, FAULT_nn, ALERT_nn, RUNn, SHARE_CLK_nn, PGOODn V OL Output Low Voltage ISINK = 3mA 0.4 V Digital Inputs SHARE_CLK_nn, WP_nn V IH Input High Threshold Voltage l 1.5 1.8 V VIL Input Low Threshold Voltage l 0.6 1 V Digital Filtering of FAUL Tn I FL TG Input Digital Filtering FAUL Tn 3 µs Digital Filtering of PGOODn I FL TG Output Digital Filtering PGOODn 100 µs Digital Filtering of RUNn I FL TG Input Digital Filtering RUN 10 µs PMBus Interface Timing Characteristics f SCL Serial Bus Operating Frequency l 10 400 kHz tBUF Bus Free Time Between Stop and Start l 1.3 µs tHD(STA) Hold Time After Repeated Start Condition After This Period, the First Clock is Generated l 0.6 µs tSU(STA) Repeated Start Condition Setup Time l 0.6 10000 µs tSU(ST0) Stop Condition Setup Time l 0.6 µs tHD(DAT) Date Hold Time Receiving Data T ransmitting Data l l 0.3 0.9 µs µs tSU(DAT) Data Setup Time Receiving Data 0.1 µs t TIMEOUT_SMB Stuck PMBus Timer Non-Block Reads Stuck PMBus Timer Block Reads Measured from the Last PMBus Start Event 32 255 ms tLOW Serial Clock Low Period l 1.3 10000 µs tHIGH Serial Clock High Period l 0.6 µs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4681 is tested under pulsed-load conditions such that T J ≈ TA. The LTM4681E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4681I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. T J is calculated from the ambient temperature TA and the power dissipation PD according the formula: TJ = TA + (PD • θJA)

Rev. AFor more information www.analog.com

ELECTRICAL CHARACTERISTICS

Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified Note 4: The two power inputs—V IN01 and VIN23—and their respective power outputs—VOUT0,1 and VOUT2,3—are tested independently in production. A shorthand notation is used in this document that allows these parameters to be referred to by “VINnn” and “VOUTn”, where n is permitted to take on a value of 0–3. This italicized, subscripted “n” notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. For example, VOUT_COMMANDn refers to the VOUT_COMMAND command code data located in Pages 0 and 1, which in turn relate to channel 0,2 (V OUT0,2) and channel 1,3 (VOUT1,3). Registers containing non-page-specific data, i.e., whose data is “global” to the module or applies to all of the module’s channels lack the italicized, subscripted “n”, e.g., FREQUENCY_SWITCH. Note 5: V OUTn (DC) and line and load regulation tests are performed in production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b) and low V OUTn range selected MFR_PWM_MODEn[1] = 1b. The digital servo control loop is exercised in production (setting MFR_PWM_ MODEn[6] = 1b), but convergence of the output voltage to its final settling value is not necessarily observed in final test—due to potentially long time constants involved—and is instead guaranteed by the output voltage readback accuracy specification. Evaluation in application demonstrates capability; see the Typical Performance Characteristics section. Note 6: See output current derating curves for different V IN, VOUT, and TA, located in the Applications Information section. Note 7: Part tested with PWM disabled. Evalution in appliction demonstrates capability. TUE(%) = ADC Gain Error (%) + 100 (zero code offset + ADC Linearity Error)/Actual Value. Note 8: Minimum on-time is tested at wafer sort. Note 9: The data conversion is done by default in round robin fashion. All inputs signals are continuously converted for a typical latency of 90ms. Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4681 can do fast data conversion with only 8ms to 10ms. See section PMBus Command for details. Note 10: The following telemetry parameters are formatted in PMBus- defined “Linear Data Format”, in which each register contains a word comprised of 5 most significant bits—representing a signed exponent, to be raised to the power of 2—and 11 least significant bits—representing a signed mantissa: input voltage (on SV IN_nn), accessed via the READ_VIN command code; output currents (IOUTn), accessed via the READ_IOUTn command codes; module input current (IVIN_nn + IVIN_nn + ISVIN_nn), accessed via the READ_IIN command code; channel input currents (IVIN_nn + 1/2 • ISVIN_nn), accessed via the MFR_READ_IINn command codes;and duty cycles of channel 0 and channel 1 switching power stages, accessed via the READ_DUTY_CYCLE n command codes. This data format limits the resolution of telemetry readback data to 10 bits even though the internal ADC is 16 bits and the LTM4681’s internal calculations use 32-bit words. Note 11: The absolute maximum rating for the SV IN_nn pin is 18V. Input voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled down from the SV IN_nn pin. Note 12: These typical parameters are based on bench measurements and are not production tested. Note 13: EEPROM endurance and retention are guaranteed by wafer-level testing for data retention. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification, and whose EEPROM data was written to at 0°C ≤ T J ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over the entire operating temperature range and does not influence EEPROM characteristics. Note 14: Channel 0–3 OV/UV comparator threshold accuracy for MFR_PWM_MODEn[1] = 0b tested in ATE at V VOSNSn+ – VVOSNSn– = 3.6V. 1V condition tested at IC-level only. Channel 0–3 OV/UV comparator threshold accuracy for MFR_PWM_MODEn[1] = 1b tested in ATE with V VOSNSn – VSGND = 0.5V. 1.5V condition tested at IC-level only. MFR_PWM_MODEn[1] = 1b is the low range. Note 15: Tested at IC-level ATE. Note 16: The LTM4681’s EEPROM temperature range for valid write commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention, execution of the “STORE_USER_ALL” command—i.e., uploading RAM contents to NVM—outside this temperature range is not recommended. However , as long as the LTM4681’s EEPROM temperature is less than 130°C, the LTM4681 will obey the STORE_USER_ALL command. Only when EEPROM temperature exceeds 130°C, the LTM4681 will not act on any STORE_USER_ALL transactions: instead, the LTM4681 NACKs the serial command and asserts its relevant CML (communications, memory, logic) fault bits. EEPROM temperature can be queried prior to commanding STORE_USER_ALL; see the Applications Information section. Note 17: The LTM4681 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Figure 1. Programmable RCOMPn

4680 F01

Rev. A For more information www.analog.com Single Channel Efficiency, 5VIN, VIN = SVIN = INTVCC = 5V, RUNP = 0V, CCM Mode Single Channel Efficiency, 8VIN, VIN = SVIN = VIN_VBIAS = 8V, RUNP = 8V,CCM Mode Single Channel Efficiency, 12VIN VIN = SVIN = VIN_VBIAS = RUNP = 12V, CCM Mode 0.9VOUT, 250kHz 1.0VOUT, 250kHz 1.2VOUT, 350kHz 1.5VOUT, 425kHz 1.8VOUT, 500kHz 2.5VOUT, 575kHz 3.3VOUT, 650kHz LOAD CURRENT (A) 100 EFFICIENCY (%)

4681 G01

0.9VOUT, 250kHz 1.0VOUT, 250kHz 1.2VOUT, 350kHz 1.5VOUT, 425kHz 1.8VOUT, 500kHz 2.5VOUT, 575kHz 3.3VOUT, 650kHz LOAD CURRENT (A) 100 EFFICIENCY (%)

4681 G02

0.9VOUT, 250kHz 1.0VOUT, 250kHz 1.2VOUT, 350kHz 1.5VOUT, 425kHz 1.8VOUT, 500kHz 2.5VOUT, 575kHz 3.3VOUT, 650kHz LOAD CURRENT (A) 100 EFFICIENCY (%)

4681 G03

TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. 100 120 100 EFFICIENCY (%) LOAD CURRENT (A)

4681 G04

0.9VOUT, 250kHz 1.0VOUT, 250kHz 1.2VOUT, 350kHz 1.5VOUT, 425kHz 1.8VOUT, 500kHz 2.5VOUT, 575kHz 3.3VOUT, 650kHz Quad Channel Single Output Efficiency V IN = SVIN = 12V, RUNP = 0V, VBIAS = 5.5V External, CCM Mode

Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. Single Channel Load T ransient Response (10A) to (20A) Load Step, 10A/µs 12V IN to 0.9VOUT Single Channel Load T ransient Response (10A) to (20A) Load Step, 10A/µs V IN = 12V, VOUT = 2.5V, fSW = 500kHz Single Channel Load T ransient Response (10A) to 1 (20A) Load Step, 10A/µs V IN = 12V, VOUT = 3.3V, fSW = 500kHz Single Channel Load T ransient Response (10A) to (20A) Load Step, 10A/µs V IN = 12V, VOUT = 1.2V, fSW = 350kHz Single Channel Load T ransient Response (10A) to (20A) Load Step, 10A/µs V IN = 12V, VOUT = 1.5V, fSW = 350kHz 50mV/DIV LOAD STEP 10A/DIV 200/uni03BCS/DIV FIGURE 48 CIRCUIT , 12V TO 0.9V , FREQ = 350kHz COUT = 470µF ×3 POSCAP , 100µF ×5 CERAMIC RCOMP = 11k, EA-GM = 4.36ms COMPna = 2.2nF , COMPnb = 150pF ILIM RANGE HIGH, VOUT RANGE LOW

4681 G05

200µs/DIV FIGURE 48 CIRCUIT , 12V TO 1.2V , FREQ = 350kHz COUT = 470µF ×2 POSCAP , 100µF ×2 CERAMIC RCOMP = 7k, EA-GM = 4.36ms COMPna = 2.2nF , COMPnb = 150pF ILIM RANGE HIGH, V OUT RANGE LOW

4681 G06

200µs/DIV FIGURE 48 CIRCUIT , 12V TO 1.5V , FREQ = 350kHz COUT = 470µF ×2 POSCAP , 100µF ×2 CERAMIC RCOMP = 7k, EA-GM = 3.69ms COMPna = 2.2nF , COMPnb = 150pF ILIM RANGE HIGH, V OUT RANGE LOW

4681 G07

200µs/DIV FIGURE 48 CIRCUIT, 12V TO 2.5V , FREQ = 500kHz COUT = 470µF ×1 POSCAP , 100µF ×1 CERAMIC RCOMP = 6k, EA-GM = 2.35ms, COMPna = 2.2nF , COMPnb = 220pF ILIM RANGE HIGH, V OUT RANGE LOW

4681 G08

200µs/DIV FIGURE 48 CIRCUIT, 12V TO 3.3V , FREQ = 500kHz COUT = 470µF ×1 POSCAP , 100µF ×1 CERAMIC RCOMP = 11k, EA-GM = 1.68ms, COMPna = 2.2nF , COMPnb = 100pF ILIM RANGE HIGH, V OUT RANGE HIGH

4681 G09

Rev. A For more information www.analog.com Single Phase Single Output Short-Circuit Protection, No Load Single Phase Single Output Short-Circuit Protection, 30A Load Quad Output Concurrent Rail, Start-Up/Shut Down Quad Output Concurrent Rail, Start-Up/Shut Down, Pre-Bias TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. 5ms/DIV FIGURE 48 CIRCUIT , 12VIN, 30A ON VOUT0 NO LOAD ON OTHER OUTPUTS

4681 G10

VOUT1, 1.8V 1V/DIV VOUT2, 2.5V 1V/DIV VOUT3, 3.3V 1V/DIV VOUT0, 30A 1V/DIV IOUT0 20A/DIV RUN0,1,2,3 5V/DIV VOUT1, 1.8V 1V/DIV VOUT2, 2.5V 1V/DIV VOUT3, 3.3V 1V/DIV VOUT0, 30A 1V/DIV IOUT0 20A/DIV RUN0,1,2,3 5V/DIV 5ms/DIV 4681 G11 FIGURE 48 CIRCUIT , 12VIN, 30A ON VOUT0 NO LOAD ON OTHER OUTPUTS AND 0.5V PREBIAS ON VOUT1 VOUT0, 1V 0.5V/DIV IIN 2A/DIV 50/uni03BCs/DIV 4681 G12 FIGURE 48 CIRCUIT , 12VIN, NO LOAD ON VOUT0 PRIOR TO APPLICATION OF SHORT-CIRCUIT USE HIGH RANGE OF I LIMIT SYSTEM SHORT-CIRCUIT USING LOW IMPEDANCE COPPER ACROSS OUTPUT (HARD SHORT) VOUT0, 1V 0.5V/DIV IIN 2A/DIV 50µs/DIV FIGURE 48 CIRCUIT , 12VIN, 30A LOAD ON VOUT0 PRIOR TO APPLICATION OF SHORT-CIRCUIT USE HIGH RANGE OF I LIMIT SYSTEM SHORT-CIRCUIT USING LOW IMPEDANCE COPPER ACROSS OUTPUT (HARD SHORT)

4681 G13

Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, 12VIN to 1VOUT, unless otherwise noted. CHANNEL NUMBER 29.6 29.8 30.0 30.2 30.4 30.6 30.8 31.0 31.2 31.4 31.6 31.8 OUTPUT CURRENT (A)

4681 G17

29.0 29.2 29.4 29.6 29.8 30.0 30.2 30.4 30.6 30.8 31.0 OUTPUT CURRENT (A)

4681 G18

28.8 29.0 29.2 29.4 29.6 29.8 30.0 30.2 30.4 30.6 30.8 OUTPUT CURRENT (A)

4681 G19

Supply Current vs Load Current Comparison, RSENSE = 2mΩ, 12V to 3.3VOUT, 650kHz Supply Current vs Load Current Comparison, R SENSE = 2mΩ, 12V to 1.0VOUT, 250kHz Supply Current vs Load Current Comparison, R SENSE = 2mΩ, 12V to 1.8VOUT, 500kHz LOAD CURRENT (A) INPUT CURRENT (A) 5030

4681 G15

4681 G16

LOAD CURRENT (A) INPUT CURRENT (A) LOAD CURRENT (A) INPUT CURRENT (A) 5030

4681 G14

READ_IOUT of 12 LTM4681 Channels 12VIN, 1VOUT, TJ = –40°C, IOUTn = 30A, System Having Reached Thermally Steady-State Condition, No Airflow READ_IOUT of 12 LTM4681 Channels 12V IN, 1VOUT, TJ = 25°C, IOUTn = 30A, System Having Reached Thermally Steady-State Condition, No Airflow READ_IOUT of 12 LTM4681 Channels 12V IN, 1VOUT, TJ = 125°C, IOUTn = 30A, System Having Reached Thermally Steady-State Condition, No Airflow

Rev. A For more information www.analog.com PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y . GND (A1- A4, A7, A12, B1- B4, B7, B12, C3- C4, C7, C12, D3- D4, D7, D12, E3- E4, E7, E12, F1- F4, F7, F12, G3- G4, G7, G12, H3- H4, H7, H12, J3- J4, J7, J12, K1-K4, K7-K12, L1-L15, M1-M15, N1-N4, N7-N8, N12, P3-P4, P7, P12, R3-R4, R7, R12, T3-T4, T7, T12, U1-U4, U7, U12, V3-V4, V7, V12, W3-W4, W7, W12, Y3-Y4, Y7, Y12, AA1-AA4, AA7, AA12, AB1-AB4, AB7, AB12): Power Ground of the LTM4681. Power return for V IN01 VIN23 VOUT0,1 and VOUT2,3. Return input and output capacitors to this point. VOUT0 ( A13-A15, B13- B15, C13- C15, D13- D15, E13- E15): Channel 0 Output Voltage. Place recommended output capacitors from this shape to GND. See recom - mended layout. VOSNS0+ (J11): Channel 0 Positive Differential Voltage Sense Input. Together , VOSNS0+ and V OSNS0– serve to Kelvin-sense the V OUT0 output voltage at V OUT0’s point of load (POL) and provide the differential feedback signal directly to channel 0’s feedback loop. Command V OUT0’s target regulation voltage by serial bus. Its initial command value at SVIN_01 power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or , option- ally, may be set by configuration resistors; see VOUT0_ CFG, VTRIM0_CFG and the Applications Information section. VOSNS0– (H11): Channel 0 Negative Differential Voltage Sense Input. See VOSNS0+. VOUT1 ( F13-F15, G13 -G15, H13 -H15, J13 -J15, K13 - K15): Channel 1 Output Voltage. Place recommended output capacitors from this shape to GND. See recom - mended layout. VOSNS1+ ( G8): Channel 1 Positive Differential Voltage Sense Input. Together , VOSNS1+ and V OSNS1– serve to Kelvin-sense the V OUT1 output voltage at V OUT1’s point of load (POL) and provide the differential feedback signal directly to channel 1’s feedback loop. Command V OUT1’s target regulation voltage by serial bus. Its initial command value at SVIN_01 power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or , option- ally, may be set by configuration resistors; see VOUT1_ CFG, VTRIM1_CFG and the Applications Information section. VOSNS1– (F8): Channel 1 Negative Differential Voltage Sense Input. See VOSNS1+. VOUT2 (N13-N15, P13- P15, R13- R15, T13-T15, U13- U15): Channel 2 Output Voltage. Place recommended output capacitors from this shape to GND. See recom - mended layout. VOSNS2+ ( P8): Channel 2 Positive Differential Voltage Sense Input. Together , VOSNS2+ and V OSNS2– serve to Kelvin-sense the V OUT2 output voltage at V OUT2’s point of load (POL) and provide the differential feedback signal directly to channel 2’s feedback loop. Command V OUT2’s target regulation voltage by serial bus. Its initial command value at SVIN_23 power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or , option- ally, may be set by configuration resistors; see VOUT2_ CFG, VTRIM2_CFG and the Applications Information section. VOSNS2– (R8): Channel 2 Negative Differential Voltage Sense Input. See VOSNS2+. VOUT3 ( V13-V15, W13-W15, Y13-Y15, AA13- AA15, AB13-AB15): Channel 3 Output Voltage. Place recom - mended output capacitors from this shape to GND See recommended layout. VOSNS3+ (R11): Channel 3 Positive Differential Voltage Sense Input. Together , VOSNS3+ and V OSNS3– serve to Kelvin-sense the V OUT3 output voltage at V OUT3’s point of load (POL) and provide the differential feedback signal directly to channel 3’s feedback loop. Command V OUT3’s target regulation voltage by serial bus. Its initial command value at SVIN_23 power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or , option- ally, may be set by configuration resistors; see VOUT3_ CFG, VTRIM3_CFG and the Applications Information section. VOSNS3– (T11): Channel 3 Negative Differential Voltage Sense Input. See VOSNS3+.

Rev. AFor more information www.analog.com PIN FUNCTIONS SGND01, SGND23 (F10-F11, U10-U11): SGND is the sig- nal ground return path of the LTM4681 internal controllers. SGND is not internally connected to GND. Connect SGND to GND local to the LTM4681. See recommended layout. VIN01 ( A5-A6, B5- B6, C5- C6, D5- D6, E5- E6, F5- F6, G5-G6, H5-H6, J5-J6, K5-K6): Positive Power Input to Channel 0 and 1 Switching Stages. Provide sufficient decoupling capacitance in the form of multilayer ceramic capacitors (MLCCs) and low ESR electrolytic (or equiv - alent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4681 as physically possible. See Layout Recommendations in the Applications Information section. VIN23 ( N5-N6, P5- P6, R5- R6, T5-T6, U5- U6, V5- V6, W5-W6, Y5-Y6, AA5- AA6, AB5- AB6): Positive Power Input to Channel 2 and 3 Switching Stages. Provide suf- ficient decoupling capacitance in the form of MLCCs and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4681 as physically possible. See Layout Recommendations in the Applications Information section. SW0 (C1-C2, D1-D2, E1-E2): Switching Node of Channel 0 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of channel 0, if desired, but do not route near any sensitive signals; otherwise, leave electrically isolated (open). SW1 (G1-G2, H1-H2, J1-J2): Switching Node of Channel 1 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of channel 1, if desired, but do not route near any sensitive signals; otherwise, leave open. SW2 (P1-P2, R1-R2, T1-T2): Switching Node of Channel 2 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of channel 2, if desired, but do not route near any sensitive signals; otherwise, leave open. SW3 (V1-V2, W1-W2, Y1-Y2): Switching Node of Channel 3 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of channel 3, if desired, but do not route near any sensitive signals; oth- erwise, leave open. SVIN_01 (J8): Input Supply for LTM4681’s Internal Control IC for channel 0 and 1. In most applications, SVIN_01 con- nects to VIN01. SVIN_01 can be operated from an auxiliary supply separate from VIN01 for powering the V IN01 from a lower supply like 6V. The SV IN_01 pin has an offboard 1Ω and 1µF decoupling capacitor . The 1Ω resistor is used to measure the actual control chip current. See MFR_ READ_ICHIP and MFR_ADC_CONTROL COMMAND sec- tion. When operating from 4.5V to 5.75V with no auxiliary bias supply, then the main input supply should connect to SVIN_01 and INTVCC_01. See Test Circuit 2 for an example. In this configuration, the ICHIP current will not be relevant since INTVCC_01 is connected to SVIN_01. SVIN_23 ( P11): Input Supply for LTM4681’ s Internal Control IC for channel 2 and 3. In most applications, SVIN_23 connects to VIN_23. SVIN_23 can be operated from an auxiliary supply separate from VIN23 for powering the VIN23 from a lower supply like 6V. The SV IN_23 pin has an offboard 1Ω and 1µF decoupling capacitor . The 1Ω resistor is used to measure the actual control chip cur - rent. See MFR_READ_ICHIP and MFR_ADC_CONTROL COMMAND section. When operating from 4.5V to 5.75V with no auxiliary bias supply, then the main input sup - ply should connect to SV IN_23 and INTVCC_23. See Test Circuit 2 for an example. In this configuration, the I CHIP current will not be relevant since INTVCC_23 is connected to SVIN_23. VIN_VBIAS (N9): Input pin to the internal step down regula- tor that produces 5.5V (VBIAS pin) to power both internal controllers to reduce power dissipation after power up. Each internal controller has an INTV CC_01 or INTV CC_23 regulator that is powered from SV IN_01 or SV IN_23. To eliminate this power loss through these linear regulators, the V BIAS powers both at very high efficiency.

Rev. A For more information www.analog.com PIN FUNCTIONS RUNP (N11): This pin enables the Internal 5.5V VBIAS Step Down Regulator . Pulling this pin above 0.85V will enable the Internal regulator . The pin is rated to V IN, so tie to VIN to enable, and tie to GND to disable. When the input voltage is between 4.5V to 5.75V, pull the RUNP pin to GND, and connect SVIN_01 and SVIN_23 to INTVCC_01 and INTVCC_23 respectively. VBIAS (N10): 5.5V step down output that powers both internal controllers to reduce power loss. Provide a 22µF ceramic bypass capacitor on this pin to GND. SV IN_01 and SV IN_23 must be higher than 7V for this V BIAS to supply the controllers. When the input voltage is between 4.5V to 5.75V, pull the RUNP pin to GND, and connect SVIN_01 and SVIN_23 to INTVCC_01 and INTVCC_23, respec- tively. Powering up the VBIAS regulator with the SV IN_01 and SVIN_23 greater than 7V will power the INTV CC_01, INTVCC_02, the V DD33_01 , V DD33_23 , V DD25_01 , and VDD25_23 from V BIAS. Otherwise these sources will get their power from SVIN_01 and SVIN_23. This will allow pro- gramming each internal controller’ s EEPROM with the power regulator channels in the off position. IIN_01+ (H10): Positive Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the I IN_01– and SV IN_01 pin. See Applications Information section for detail about the input current sensing. IIN_01– (J10): Negative Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN_01+ and SVIN_01 pin. See Applications Information section for detail about the input current sensing. IIN_23+ (R9): Positive Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the I IN_23– and SV IN_23 pin. See Applications Information section for detail about the input current sensing. IIN_23– (P9): Negative Current Sense Amplifier Input. If the input current sense amplifier is not used, this pin must be shorted to the I IN_23+ and SV IN_23 pin. See Applications Information section for detail about the input current sensing. INTVCC_01 (J9): Internal Regulator , 5.5V Output. When operating the LTM4681 from 5.75V ≤ SVIN_01 ≤ 16V, an internal LDO generates INTV CC_01 from SV IN_01 to bias internal control circuits and the MOSFET drivers of the LTM4681’s channel 0 and 1. An external 4.7µF ceramic decoupling capacitor is required. INTV CC_01 is on regu- lated regardless of the RUNn pin state. When operating the LTM4681 with 4.5V ≤ SVIN_01 < 5.75V, INTVCC_01 must be electrically shorted to SV IN_01, and the RUNP pin must be pulled to GND. VBIAS takes over after startup when the input voltage is greater than 7V. INTVCC_23 (P10): Internal Regulator , 5.5V Output. When operating the LTM4681 from 5.75V ≤ SVIN_23 ≤ 16V, an internal LDO generates INTV CC_23 from SV IN_23 to bias internal control circuits and the MOSFET drivers of the LTM4681’s channel 2 and 3. An external 4.7µF ceramic decoupling i capacitor s required. INTVCC_23 is on regu- lated regardless of the RUNn pin state. When operating the LTM4681 with 4.5V ≤ SVIN_23 < 5.75V, INTVCC_23 must be electrically shorted to SV IN_23, and the RUNP pin must be pulled to GND. VBIAS takes over after startup when the input voltage is greater than 7V. VDD33_01 (E8): Internally Generated 3.3V Power Supply Output Pin for Channel 0 and 1 Circuits. This pin should only be used to provide external current for the pull-up resistors required for FAULT_nn, SHARE_CLK_nn, and SYNC_nn, and may be used to provide external current for pull-up resistors on RUNn, SDA_nn, SCL_nn, ALERT_nn and PGOODn. Where nn is either 0,1 or 2,3 channels, and n is the actual channel. No external decoupling is required. VDD33_01 can be powered from VBIAS, such that this con- troller 1 can be programmed with RUNn low. VDD33_23 (Y10): Internally Generated 3.3V Power Supply Output Pin for Channel 2 and 3 Circuits. This pin should only be used to provide external current for the pull-up resistors required for FAULT_nn, SHARE_CLK_nn, and SYNC_nn, and may be used to provide external current for pull-up resistors on RUNn, SDA_nn, SCL_nn, ALERT_nn and PGOODn. Where nn is either 0,1 or 2,3 channels, and n is the actual channel. No external decoupling is required. VDD33_23 can be powered from VBIAS, such that this con- troller 2 can be programmed with RUNn low.

Rev. AFor more information www.analog.com PIN FUNCTIONS VDD25_01 (C8): Internally Generated 2.5V Power Supply Output Pin for Channel 0 and 1 Circuits. Do not load this pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resis - tors connected to the configuration-programming pins. No external decoupling is required. VDD25_23 (AB11): Internally Generated 2.5V Power Supply Output Pin for Channel 2 and 3 Circuits. Do not load this pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resis - tors connected to the configuration-programming pins. No external decoupling is required. ASEL_01 (B9): Serial Bus Address Configuration Pin for Channel 0 and 1 Controller . On any given I2C/SMBus serial bus segment, every device must have its own unique slave address. If this pin is left open, the LTM4681 powers up to its default slave address of 0x4E (hexadecimal), i.e., 1001110b (industry-standard convention is used through- out this document: 7-bit slave addressing). The lower four bits of the LTM4681’s slave address can be altered from this default value by connecting a resistor from this pin to SGND. Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. It is recommended to use a resistor to set the address. The ASEL_01 address will be used to address channels 0 and 1, and a different ASEL_23 address will be used to address channels 2 and 3. For addressed ASEL_01, Page 0x00 corresponds to channel 0 and Page 0x01 cor- responds to Channel 1. See PAGE description section. The GUI will represent Channel 0 as U0:A0 and Channel 1 as U0:A1. See Page 67. ASEL_23 (AA10): Serial Bus Address Configuration Pin for Channel 2 and 3 Controller . On any given I 2C/SMBus serial bus segment, every device must have its own unique slave address. If this pin is left open, the LTM4681 powers up to its default slave address of 0x4F (hexa - decimal), i.e., 1001111b (industry-standard convention is used throughout this document: 7-bit slave addressing). The lower four bits of the LTM4681’s slave address can be altered from this default value by connecting a resistor from this pin to SGND. Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. It is recommended to use a resistor to set the address. The ASEL_23 address will be used to address channels 2 and 3, and a different ASEL_01 address will be used to address channels 0 and 1. For addressed ASEL_23, Page 0x00 corresponds to channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section. The GUI will represent Channel 2 as U1:B0 and Channel 3 as U1:B1. See Page 67. FSWPH_01_CFG (A9): Switching Frequency, Channel Phase-Interleaving Angle and Phase Relationship to SYNC Configuration Pin for Channel 0 and 1. If this pin is left open—or , if the LTM4681 is configured to ignore pin- strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then LTM4681’s switching frequency (FREQUENCY_ SWITCH) and channel phase relationships (with respect to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated at SVIN_01 power-up according to the LTM4681’ s NVM contents for channel 0 and 1. Default factory values are: 350kHz operation; channel 0 at 0°; and channel 1 at 180°C (convention throughout this document: a phase angle of 0° means the channel’s switch node rises coincident with the falling edge of the SYNC pulse). Connecting a resistor divider from 2.5V to SGND (and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b) allows a con- venient way to configure multiple LTM4681s with identi- cal NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channels — all, without GUI intervention or the need to custom pre-program module NVM contents. (See the Applications Information sec - tion.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. FSWPH_23_CFG (AA9): Switching Frequency, Channel Phase-Interleaving Angle and Phase Relationship to SYNC Configuration Pin for Channel 2 and 3. If this pin is left open—or , if the LTM4681 is configured to ignore pin- strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = 1b—then LTM4681’s switching frequency (FREQUENCY_ SWITCH) and channel phase relationships (with respect to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dic - tated at SV IN_23 power-up according to the LTM4681’s NVM contents for channel 2 and 3. Default factory values

Rev. A For more information www.analog.com are: 350kHz operation; channel 2 at 0°; and channel 3 at 180°C (convention throughout this document: a phase angle of 0° means the channel’s switch node rises coinci- dent with the falling edge of the SYNC pulse). Connecting a resistor divider from 2.5V to SGND (and using the factory- default NVM setting of MFR_CONFIG_ALL[6] = 0b) allows a convenient way to configure multiple LTM4681s with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra-module-paralleled channels—all, without GUI intervention or the need to custom pre-program module NVM contents. (See the Applications Information sec - tion.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. VOUT0_CFG (A8): Output Voltage Select Pin for V OUT0, Coarse Setting. If the VOUT0_CFG and VTRIM0_CFG pins are both left open—or , if the LTM4681 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b—then the LTM4681s target V OUT0 output voltage setting (VOUT_COMMAND0 ) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_01 power-up according to the LTM4681’s NVM contents. A resistor divider connected to 2.5V and to SGND (see Table 1)—in combination with resistor pin settings on VTRIM0_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4681’s channel 0 output to power- up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresh- olds) different from those of NVM contents. (See the Applications Information section.) Connecting resistor(s) from VOUT0_CFG to SGND and/or VTRIM0_CFG to SGND in this manner allows a convenient way to configure mul- tiple LTM4681s with identical NVM contents for different output voltage settings all without GUI intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT0_CFG/VTRIM0_CFG can affect the VOUT0 range setting ( MFR_PWM_MODE0[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to channel 0 and Page 0x01 corresponds to Channel 1. See PAGE description section. VTRIM0_CFG (D9): Output Voltage Select Pin for V OUT0, Fine Setting. Works in combination with VOUT0_CFG to affect the VOUT_COMMAND (and associated output volt- age monitoring and protection/fault-detection thresholds) of channel 0, at SVIN_01 power-up. (See VOUT0_CFG and the Applications Information section.) A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value. See Table 2. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of R CONFIGs on VOUT0_ CFG/VTRIM0_CFG can affect the V OUT0 range setting (MFR_PWM_MODE0[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to channel 0 and Page 0x01 corresponds to Channel 1. See PAGE command description section. VOUT1_CFG (B8): Output Voltage Select Pin for V OUT1, Coarse Setting. If the VOUT1_CFG and VTRIM1_CFG pins are both left open—or , if the LTM4681 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b—then the LTM4681 s target V OUT1 output voltage setting (VOUT_COMMAND1 ) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_01 power-up according to the LTM4681’s NVM contents. A resistor divider connected to 2.5V and to SGND to this pin— in combination with resistor pin settings on VTRIM1_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4681’s channel 1 output to power- up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresh- olds) different from those of NVM contents. (See the Applications Information section.) Connecting resistor(s) from VOUT1_CFG to SGND and/or VTRIM1_CFG to SGND in this manner allows a convenient way to configure mul- tiple LTM4681s with identical NVM contents for different output voltage settings all without GUI intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT1_CFG/VTRIM1_CFG can affect the VOUT1 range setting ( MFR_PWM_MODE1[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to channel 0 and Page 0x01 corresponds to Channel 1. See PAGE description section. PIN FUNCTIONS

Rev. AFor more information www.analog.com VTRIM1_CFG (C9): Output Voltage Select Pin for VOUT1, Fine Setting. Works in combination with VOUT1_CFG to affect the VOUT_COMMAND (and associated output volt- age monitoring and protection/fault-detection thresholds) of channel 1, at SVIN_01 power-up. (See VOUT1_CFG and the Applications Information section.) A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value. See Table 2. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of R CONFIGs on VOUT1_CFG/ VTRIM1_CFG can affect the V OUT1 range setting (MFR_ PWM_MODE1[1]) and loop gain. For addressed ASEL_01, Page 0x00 corresponds to channel 0 and Page 0x01 cor- responds to Channel 1. See PAGE description section. VOUT2_CFG (AA8): Output Voltage Select Pin for VOUT2, Coarse Setting. If the VOUT2_CFG and VTRIM2_CFG pins are both left open—or , if the LTM4681 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b—then the LTM4681s target V OUT2 output voltage setting (VOUT_COMMAND0 ) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_23 power-up according to the LTM4681’s NVM contents. A resistor divider connected to 2.5V and to SGND to this pin— in combination with resistor pin settings on VTRIM2_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4681’s channel 2 output to power- up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresh- olds) different from those of NVM contents. (See the Applications Information section.) Connecting resistor(s) from VOUT2_CFG to SGND and/or VTRIM2_CFG to SGND in this manner allows a convenient way to configure mul- tiple LTM4681s with identical NVM contents for different output voltage settings all without GUI intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT2_CFG/VTRIM2_CFG can affect the VOUT2 range setting ( MFR_PWM_MODE0[1]) and loop gain.For addressed ASEL_23, Page 0x00 corresponds to channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section. VTRIM2_CFG (AB10): Output Voltage Select Pin for VOUT2, Fine Setting. Works in combination with VOUT2_CFG to affect the VOUT_COMMAND (and associated output volt- age monitoring and protection/fault-detection thresholds) of channel 2, at SVIN_23 power-up. (See VOUT2_CFG and the Applications Information section.) A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value. See Table 2. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of R CONFIGs on VOUT2_CFG/ VTRIM2_CFG can affect the V OUT2 range setting (MFR_ PWM_MODE0[1]) and loop gain. For addressed ASEL_23, Page 0x00 corresponds to channel 2 and Page 0x01 cor- responds to Channel 3. See PAGE description section. VOUT3_CFG (AB8): Output Voltage Select Pin for VOUT3, Coarse Setting. If the VOUT3_CFG and VTRIM3_CFG pins are both left open—or , if the LTM4681 is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ ALL[6] = 1b—then the LTM4681 s target V OUT3 output voltage setting (VOUT_COMMAND1 ) and associated power-good and OV/UV warning and fault thresholds are dictated at SVIN_23 power-up according to the LTM4681’s NVM contents. A resistor divider connected to 2.5V and to SGND to this pin— in combination with resistor pin settings on VTRIM3_CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used to configure the LTM4681’s channel 3 output to power- up to a VOUT_COMMAND value (and associated output voltage monitoring and protection/fault-detection thresh- olds) different from those of NVM contents. (See the Applications Information section.) Connecting resistor(s) from VOUT3_CFG to SGND and/or VTRIM3_CFG to SGND in this manner allows a convenient way to configure mul- tiple LTM4681s with identical NVM contents for different output voltage settings all without GUI intervention or the need to custom-preprogram module NVM contents. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of RCONFIGs on VOUT3_CFG/VTRIM3_CFG can affect the VOUT3 range setting ( MFR_PWM_MODE1[1]) and loop gain. For addressed ASEL_23, Page 0x00 corresponds to channel 2 and Page 0x01 corresponds to Channel 3. See PAGE description section. PIN FUNCTIONS

Rev. A For more information www.analog.com VTRIM3_CFG (AB9): Output Voltage Select Pin for VOUT3, Fine Setting. Works in combination with VOUT3_CFG to affect the VOUT_COMMAND (and associated output volt- age monitoring and protection/fault-detection thresholds) of channel 3, at SVIN_23 power-up. (See VOUT3_CFG and the Applications Information section.) A resistor divider from 2.5V to SGND connected to the pin will set the TRIM value. See Table 2. Minimize capacitance especially when the pin is left open to assure accurate detection of the pin state. Note that use of R CONFIGs on VOUT3_CFG/ VTRIM3_CFG can affect the V OUT3 range setting (MFR_ PWM_MODE0[1]) and loop gain. For addressed ASEL_23, Page 0x00 corresponds to channel 2 and Page 0x01 cor- responds to Channel 3. See PAGE description section. RUN0, RUN1 (B10, B11 Respectively): Enable Run Input for Channels 0 and 1, respectively. Open-drain input and output. Logic high on these pins enables the respective outputs of the LTM4681. These open-drain output pins hold the pin low until the LTM4681 is out of reset and SVIN_01 is detected to exceed V IN_ON. A pull-up resistor to 3.3V is required in the application. The LTM4681 pulls RUN0 and/or RUN1 low, as appropriate, when a global fault and/or channel-specific fault occurs whose fault response is configured to latch off and cease regulation; issuing a CLEAR_FAULTS command via I 2C or power- cycling SVIN_01 is necessary to restart the module, in such cases. Do not pull RUN logic high with a low impedance source. INTV CC is active when SVIN_01 is above UVLO. This provides power to the VDD33 and VDD25 to allow programming the EERROM. RUN2, RUN3 (Y9, Y8): Enable Run Input for Channels 2 and 3, respectively. Open-drain input and output. Logic high on these pins enables the respective outputs of the LTM4681. These open-drain output pins hold the pin low until the LTM4681 is out of reset and SV IN_23 is detected to exceed VIN_ON. A pull-up resistor to 3.3V is required in the application. The LTM4681 pulls RUN2 and/or RUN3 low, as appropriate, when a global fault and/or channel- specific fault occurs whose fault response is configured to latch off and cease regulation; issuing a CLEAR_FAULTS command via I 2C or power-cycling SVIN_23 is necessary to restart the module, in such cases. Do not pull RUN logic high with a low impedance source. INTVCC is active when SVIN_23 is above UVLO. This provides power to the VDD33 and VDD25 to allow programming the EEPROM. PGOOD0, PGOOD1, PGOOD2, PGOOD3 (H9, H8, R10, T10): Power Good Indicator Outputs. Open-drain logic output that is pulled to ground when the output exceeds the UV and OV regulation window. The output is de- glitched by an internal 100µs filter . A pull-up resistor to 3.3V is required in the application. FAUL T0, FAUL T1, FAUL T2, FAUL T3 (A11, A10, V10, W10): Digital Programmable FAUL T Inputs and Outputs. Open-drain output. A pull-up resistor to 3.3V is required in the application. COMP0b, COMP1b, COMP2b, COMP3b (G10, F9, T9, W11): Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel’s current comparator tripping threshold increases with its compen- sation voltage. Each channel has a 22pF to SGND. COMP0a, COMP1a, COMP2a, COMP3a (G11, G9, T8, V11): Loop Compensation Nodes. The internal PWM loop compensation resistors R COMPn of the LTM4681 can be adjusted using bit[4:0] of the MFR_PWM_COMP command. The transconductance of the LTM4681 PWM error amplifier can be adjusted using bit[7:5] of the MFR_ PWM_COMP command. These two loop compensation parameters can be programmed when device is in opera- tion. Refer to the Programmable Loop Compensation sub- section in the Applications Information section for further details. See Figure 1. SYNC_01, SYNC_23 (D11, V9): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to ground. A resistor pull-up to 3.3V is required in the application if the LTM4681 is the master . SCL_01, SCL_23 (D10, W9): Serial Bus Clock Open-Drain Input (Can Be an Input and Output, if Clock Stretching is Enabled). A pull-up resistor to 3.3V is required in the PIN FUNCTIONS

Rev. AFor more information www.analog.com application for digital communication to the SMBus master(s) that nominally drive this clock. The LTM4681 will never encounter scenarios where it would need to engage clock stretching unless SCL communication speeds exceed 100kHz—and even then, LTM4681 will not clock stretch unless clock stretching is enabled by means of setting MFR_CONFIG_ALL[1] = 1b. The factory-default NVM configuration setting has MFR_CONFIG_ALL[1] = 0b: clock stretching disabled. If communication on the bus at clock speeds above 100kHz is required, the user’s SMBus master(s) needs to implement clock stretching support to assure solid serial bus communications, and only then should MFR_CONFIG_ALL[1] be set to 1b. When clock stretching is enabled, SCL becomes a bidi - rectional, open-drain output pin on LTM4681. SDA_01, SDA_23 (C10, V8): Serial Bus Data Open-Drain Input and Output. A pull-up resistor to 3.3V is required in the application. SDA_01 is for Channel 0 and 1, and SDA_23 is for Channel 2 and 3. ALERT_01, ALERT_23 (C11, W8): Open-Drain Digital Output. A pull-up resistor to 3.3V is required in the application only if SMBALERT interrupt detection is imple- mented in one’s SMBus system. SHARE_CLK_01, SHARE_CLK_23 (D8, AA11): Share Clock, Bidirectional Open-Drain Clock Sharing Pin. Nominally 100kHz. Used for synchronizing the time base between multiple LTM4681s (and any other Analog Devices products with a SHARE_CLK pin)— to realize well-defined rail sequencing and rail tracking. Tie the SHARE_CLK pins of all such devices together; all devices with a SHARE_CLK pin will synchronize to the fastest clock. A pull-up resistor to 3.3V is only required when synchronizing the time base between devices. TSNS0, TSNS1, TSNS2, TSNS3 (E11, E10, U8, U9): Power stage temperature monitors for the 4channels. See Applications Information section. WP_01, WP_23 (E9, Y11): Write Protect Pin, Active High. An internal 10µA current source pulls this pin to VDD33. If WP is open circuit or logic high, only I2C writes to PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and MFR_EE_UNLOCK are supported. Additionally, Individual faults can be cleared by writing 1b’s to bits of interest in registers prefixed with STATUS. If WP is low, I 2C writes are unrestricted. PIN FUNCTIONS

4681 F02

Figure 2. Simplified LTM4681 Block Diagram of the 1/2 Function TA = 25°C. Using Figure 2 configuration.

Figure 3. Functional LTM4681 Block Diagram

4681 F03

Rev. A For more information www.analog.com VDD33_23 VDD33_01 VDD25_23 VDD25_01 POWER GOOD FAUL T INTERRUPTS ON_OFF_CONFIG 10k VIN VIN VDD33_01 1m/uni03A9 1/uni03A9 1µF 150µF 10k 10k 2.43k 2200pF 2200pF 100pF 100pF 2200pF 100pF 2200pF 100pF 14.3kVDD25_01 VIN, 5.75V TO 16V 1m/uni03A9 1/uni03A9 1µF 10k 4.99k 10k 10k 10k 4.7µF 4.7µF 22µF 100µF 22µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 100µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 100µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 100µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 2.43k 14.3kVDD25_01 2.43k 14.3kVDD25_23 2.43k 14.3kVDD25_23 1.65k 14.3kVDD25_23 22.6k 14.3kVDD25_01 32.4k 22.6k PGOOD3 PGOOD2 PGOOD1 PGOOD0 COMP1b COMP1a ALERT_01 ALERT_23 SHARE_CLK_01 SHARE_CLK_23 SYNC_01 SYNC_23 SDA_01 SDA_23 SCL_01 SCL_23 WP_23 WP_01 V DD33_23 VDD33_01 VDD25_23 INTVCC_01 VDD25_01 TSNS1 TSNS0 TSNS3 TSNS2 COMP0b COMP0a FAUL T3 FAUL T2 FAUL T1 FAUL T0 RUN3 RUN2 RUN1 RUN0 RUNP* V IN_VBIAS SVIN_23 VIN23 IN_23– IN_23+ SVIN_01 VIN01 IN_01– IN_01+ VOSNS3– VOSNS3+ VOUT3 SW3 COMP2b COMP2a COMP3b COMP3a VTRIM0_CFG VOUT0_CFG INTVCC_23 VBIAS SGND_01 SGND_23 GND VOSNS2– VOSNS2+ VOUT2 SW2 VOSNS1– VOSNS1+ VOUT1 SW1 VOSNS0– VOSNS0+ VOUT0 SW0 VTRIM1_CFG VOUT1_CFG VTRIM2_CFG VOUT2_CFG VTRIM3_CFG VOUT3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23 L TM4681 I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER *RUNP CAN BE CONNECTED TO GND FOR ALL VIN, BUT EFFICIENCY WILL BE IMPROVED BY CONNECTING RUNP TO VIN FOR VIN > 7V . CONFIG RESISTORS ARE TO BE 1%, 50PPM SLAVE ADDRESS:100_ 1110_R/W FOR 2,3 DEVICE MFR_CONFIG_ALL bit[4] =1 FOR 0,1 DEVICE SLAVE ADDRESS:100_1111_R/W 4681TC01 VDD33_01 TEST CIRCUITS Test Circuit 1.

Rev. AFor more information www.analog.com VDD33_23 VDD33_01 VDD33_01 VDD25_23 VDD25_01 POWER GOOD FAUL T INTERRUPTS ON_OFF_CONFIG 10k VIN VDD33_01 1m/uni03A9 1/uni03A9 1µF 150µF 10k 10k 2.43k 2200pF 2200pF 100pF 100pF 2200pF 100pF 2200pF 100pF 14.3kVDD25_01 VIN, 4.5V TO 5.75V 1m/uni03A9 1/uni03A9 1µF 10k 4.99k 10k 10k 10k 4.7µF 4.7µF 22µF 100µF 22µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 100µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 100µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 100µF LOAD 1V AT 31.25A ADJUSTABLE TO 3.3V 2.43k 14.3kVDD25_01 2.43k 14.3kVDD25_23 2.43k 14.3kVDD25_23 1.65k 14.3kVDD25_23 22.6k 14.3kVDD25_01 32.4k 22.6k 4681TC02 PGOOD3 PGOOD2 PGOOD1 PGOOD0 COMP1b COMP1a ALERT_01 ALERT_23 SHARE_CLK_01 SHARE_CLK_23 SYNC_01 SYNC_23 SDA_01 SDA_23 SCL_01 SCL_23 WP_23 WP_01 V DD33_23 VDD33_01 VDD25_23 INTVCC_01 VDD25_01 TSNS1 TSNS0 TSNS3 TSNS2 COMP0b COMP0a FAUL T3 FAUL T2 FAUL T1 FAUL T0 RUN3 RUN2 RUN1 RUN0 RUNP V IN_VBIAS SVIN_23 VIN23 SVIN_01 SVIN_23 IN_23– IN_23+ SVIN_01 SVIN_23 SVIN_01 VIN01 IN_01– IN_01+ VOSNS3– VOSNS3+ VOUT3 SW3 COMP2b COMP2a COMP3b COMP3a VTRIM0_CFG VOUT0_CFG INTVCC_23 VBIAS SGND_01 SGND_23 GND VOSNS2– VOSNS2+ VOUT2 SW2 VOSNS1– VOSNS1+ VOUT1 SW1 VOSNS0– VOSNS0+ VOUT0 SW0 VTRIM1_CFG VOUT1_CFG VTRIM2_CFG VOUT2_CFG VTRIM3_CFG VOUT3_CFG FSWPH_23_CFG FSWPH_01_CFG ASEL_01 ASEL_23 L TM4681 I2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER CONFIG RESISTORS ARE TO BE 1%, 50PPM SLAVE ADDRESS:100_ 1110_R/W FOR 2,3 DEVICE MFR_CONFIG_ALL bit[4] =1 FOR 0,1 DEVICE SLAVE ADDRESS:100_1111_R/W TEST CIRCUITS Test Circuit 2.

Rev. A For more information www.analog.com OPERATION POWER MODULE INTRODUCTION The LTM4681 is a highly configurable quad 31.25A out - put standalone nonisolated switching mode step-down DC/DC power supply with built-in EEPROM NVM (non- volatile memory) with ECC and I2C-based PMBus/ SMBus 2-wire serial communication interface capable of 400kHz SCL bus speed. Four output voltages can be regulated (VOUT0, VOUT1, VOUT2, VOUT3) with a few external input and output capacitors and pull-up resistors. Readback telemetry data of input and output voltages and input and output currents, and module temperatures are continually digitized cyclically by an integrated 16-bit ADC (analog-to- digital converter). Many fault thresholds and responses are customizable. Data can be autonomously saved to EEPROM when a fault occurs, and the resulting fault log can be retrieved over I2C at a later time, for analysis. See Figure 2 and Figure 3 for Block Diagrams. One controller for channels 0 and 1, 2nd controller for channels 2 and 3. POWER MODULE OVERVIEW , MAJOR FEATURES Major Features Include: n Dedicated Power Good Indicators n Direct Input and Chip Current Sensing n Programmable Loop Compensation Parameters n TINIT Start-Up Time: 30ms n PWM Synchronization Circuit, (See Frequency and Phasing Section for Details) n MFR_ADC_CONTROL for Fast ADC Sampling of One Parameter (as Fast as 8ms) (See PMBus Command for Details) n Fully Differential Output Sensing for All Four Channels; VOUT0/VOUT1/VOUT2/VOUT3 All Programmable Up to 3.3V n Power-Up and Program EEPROM with VBIAS n Input Voltage Up to 16V n ∆VBE Temperature Sensing n SYNC Contention Circuit (Refer to Frequency and Phase Section for Details) n Fault Logging n Programmable Output Voltage n Programmable Input Voltage On and Off Threshold Voltage n Programmable Current Limit n Programmable Switching Frequency n Programmable OV and UV Threshold voltage n Programmable ON and Off Delay Times n Programmable Output Rise/Fall Times n Phase-Locked Loop for Synchronous PolyPhase Operation (2, 3, 4 or 6 Phases) n Nonvolatile Configuration Memory with ECC n Optional External Configuration Resistors for Key Operating Parameters n Optional Time Base Inter connect for Synchronization Between Multiple Controllers n WP Pin to Protect Internal Configuration n Stand Along Operation After User Factory Configuration n PMBus, Version 1.2, 400kHz Compliant Interface The PMBus interface provides access to important power management data during system operation including: n Internal Controller Temperature n Internal Power Channel Temperature n Average Output Current n Average Output Voltage n Average Input Voltage n Average Input Current n Average Chip Input Current from VIN n Configurable, Latched and Unlatched Individual Fault and Warning Status Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1.

Rev. AFor more information www.analog.com OPERATION Fault reporting and shutdown behavior are fully configu- rable. Four individual FAUL T0, FAUL T1, FAUL T2, FAUL T3, outputs are provided, both of which can be masked independently. Six dedicated pins for ALERT_01, ALERT_23, PGOOD0, PGOOD1, PGOOD2, PGOOD3 functions are provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes. Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following: n Output Undervoltage/Over voltage n Input Undervoltage/Over voltage n Input and Output Overcurrent n Internal Overtemperature n Communication, Memory or Logic (CML) Fault EEPROM WITH ECC The LTM4681 contains internal EEPROM with ECC (Error Correction Coding) to store user configuration settings and fault log information for channels 0 and 1, and channels 2 and 3. EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations above TJ = 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between –40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. The fault logging function, which is useful in debugging sys- tem problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, the slight degrada - tion in the data retention characteristics of the fault log will not take away from the usefulness of the function. It is recommended that the EEPROM not be written when the die temperature is greater than 85°C. If the die tem - perature exceeds 130°C , the LTM4681 will disable all EEPROM write operations. All EEPROM write operations will be re-enabled when the die temperature drops below 125°C. (The controller will also disable all the switching when the die temperature exceeds the internal overtem - perature fault limit 160°C with a 10°C hysteresis). The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimen - sionless acceleration factor using the following equation: AF = e Ea k ⎝⎜ ⎞ ⎠⎟• 1 TUSE+273– 1 TSTRESS+273 where: AF = acceleration factor Ea = activation energy = 1.4eV k = 8.617 • 10 –5 eV/K TUSE = 125°C specified junction temperature TSTRESS = actual junction temperature in °C Example: Calculate the effect on retention when operating at a junction temperature of 130°C for 10 hours. TSTRESS = 130°C TUSE = 125°C, The equivalent operating time at 125°C = 16.6 hours. Thus the overall retention of the EEPROM was degraded by 6.6 hours as a result of operating at a junction tempera- ture of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM reten- tion rating of 87,600 hours at a maximum junction tem - perature of 125°C. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also

Rev. A For more information www.analog.com OPERATION respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. See the Applications Information section or con- tact the factory for details on efficient in-system EEPROM programming, including bulk EEPROM Programming, which the LTM4681 also supports. The LTM4681 contains two dual internal constant fre - quency current mode control buck regulators (channel 0 and channel 1, and channel 2 and 3) and whose power MOSFETs are capable of fast switching speed. Reference to the signal pins will be Name_nn, where n is either 01 or 23, or with namen when referring to signal pins that are related to the actual channel. The factory NVM-default switching frequency clocks SYNC_nn at 350kHz, to which the regu- lators synchronize their switching frequency. The default phase-interleaving angle between the channels is 180 °. A pin-strapping resistor on FSWPH_nn_CFG configures the frequency of the SYNC_nn clock (switching frequency) and the channel phase relationship of the channels to each other and with respect to the falling edge of the SYNC_nn sig- nal. (Most possible combinations of switching frequency and phase-angle assignments are settleable by resistor pin programming; see Table 3. Configure the LTM4681’s NVM to implement settings not available by resistor-pin strapping.) When a FSWPH_nn_CFG pin-strap resistor sets the channel phase relationship of the LTM4681’s channels, the SYNC_nn clock is not driven by the module; instead, SYNC_nn becomes strictly a high impedance input and channel switching frequency is then synchronized to SYNC_nn provided by an externally-generated clock or sib- ling LTM4681 with pull-up resistor to VDD33_nn. Switching frequency and phase relationship can be altered via the I2C interface, but only when switching action is off, i.e., when the module is not regulating the outputs. See the Applications Information section for details. Programmable analog feedback loop compensation for channel 0 to channel 3 is accomplished with a capaci - tor connection from COMPna to SGND, and a capacitor from COMPnb to SGND.) The COMP nb pin is for the high frequency gain roll off and is the g m amplifier out- put that has a programmable range, and the COMP na pin has the programmable resistor range along with a capacitor to SGND that sets the frequency compensa - tion. See Programmable Loop Compensation section. The LTM4681 module has sufficient stability margins and good transient performance with a wide range of output capacitors—even all-ceramic MLCCs. Table 13 provides guidance on input and output capacitors recommended for many common operating conditions along with the programmable compensation settings. The Analog Devices L TpowerCAD tool is available for transient and stability analysis, and experienced users who prefer to adjust the module’s feedback loop compensation param- eters can use this tool. POWER-UP AND INITIALIZATION The LTM4681 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 16V) while three on-chip linear regulators generate internal 2.5V, 3.3V and 5.5V per controller . If VINnn does not exceed 6V, and the VBIAS pin is turned off, the INTVCC, VINnn and SVIN_nn pins must be tied together . The controller configuration is initialized by an internal threshold based UVLO where V INnn must be approximately 4V and the 5.5V, 3.3V and 2.5V linear regulators must be within approximately 20% of the regulated values. In addition to the power supply, a PMBus RESTORE_USER_ALL or MFR_RESET command can initialize the part too. The VBIAS pin is the output of an internal 5.5V buck regu- lator to improve efficiency of the circuit and minimize power loss on the LTM4681. The VBIAS pin must exceed approximately 4.8V, and VIN must exceed 7V before the INTVCC LDO operates from the VBIAS pin. The VBIAS regu- lator is powered from VIN_VBIAS and enabled with RUNP . During initialization, the external configuration resistors are identified and/or contents of the NVM are read into the controller’s commands and the power train is held off. The RUNn and FAUL Tn and PGOODn are held low. The LTM4681 will use the contents of Table 1 thru Table 5 to determine the resistor defined parameters. See the Resistor Configuration section for more details. The resistor configuration pins only control some of the preset values of the controller .

Rev. AFor more information www.analog.com OPERATION The remaining values are programmed in NVM either at the factory or by the user . If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_ CONFIG_ALL configuration command), the LTM4681 will use only the contents of NVM to determine the DC/ DC characteristics. The ASEL_nn value read at power-up or reset is always respected unless the pin is open. The ASEL_nn will set the bottom 4LSBs and the MSBs are set by NVM. See the Applications Information section for more details. After the part has initialized, an additional comparator monitors V IN through the SVIN_nn pins. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After V IN is initially applied, the part will typically require 30ms to initialize and begin the TON_DELAY timer . The readback of voltages and currents may require an additional 0ms to 90ms. SOFT-START The method of start-up sequencing described below is time-based. The part must enter the run state prior to soft- start. The run pins are released by the LTM4681 after the part is initialized and SVIN_nn is greater than the VIN_ON threshold. If multiple LTM4681s are used in an application, they all hold their respective run pins low until all devices are initialized and SV IN_nn exceeds the VIN_ON threshold for every device. The SHARE_CLK_nn pin assures all the devices connected to the signal use the same time base. The SHARE_CLK_nn pin is held low until the part has been initialized after VIN is applied. The LTM4681 can be set to turn-off (or remain off) if SHARE_CLK_nn is low (set bit 2 of MFR_CHAN_CONFIG to 1). This allows the user to assure synchronization across numerous L TC® devices even if the RUNn pins cannot be connected together due to board constraints. In general, if the user cares about synchronization between chips it is best not only to con- nect all the respective RUNn pins together but also to connect all the respective SHARE_CLK_nn pins together and pulled up to VDD33_nn with a 10k resistor . This assures all chips begin sequencing at the same time and use the same time base. After the RUNn pins release and prior to entering a constant output voltage regulation state, the LTM4681 performs a monotonic initial ramp or “ soft-start”. Soft-start is per- formed by actively regulating the load voltage while digi- tally ramping the target voltage from 0V to the commanded voltage set-point. Once the LTM4681 is commanded to turn on (after power up and initialization), the controller waits for the user specified turn-on delay (TON_DELAY) prior to ini- tiating this output voltage ramp. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The LTM4681 PWM always uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bot- tom MOSFET is turned off as soon as reverse current is detected in the inductor . This will allow the regulator to start up into a pre-biased load. When the TON_MAX_FAULT_ LIMIT is reached, the part transitions to continuous mode, if so programmed. If TON_MAX_FAULT_LIMIT is set to zero, there is no time limit and the part transitions to the desired conduction mode after TON_RISE completes and V OUTn has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. However , setting TON_MAX_FAULT_LIMIT to a value of 0 is not recommended. TIME-BASED SEQUENCING The default mode for sequencing the outputs on and off is time-based. Each output is enabled after waiting TON_ DELAY amount of time following either a RUN pin going high, a PMBus command to turn on or the VIN rising above a preprogrammed voltage. Off sequencing is handled in a similar way. To assure proper sequencing, make sure all ICs connect the SHARE_CLK_nn pin together and RUNn pins together . If the RUNn pins cannot be connected together for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1. This bit requires the SHARE_CLK_nn pin to be clocking before the power supply output can start. When the RUNn pin is pulled low, the LTM4681 will hold the pin low for the MFR_ RESTART_DELAY. The minimum MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures proper sequencing of all rails. The LTM4681 calculates this delay internally and will not process a shorter delay. However , a longer commanded

mum allowed value is 65.52 seconds. this problem, set the TON_RISE time under 100ms. tion states or through user intervention. output to decay below 12.5% of the programmed value. RUNn or commanding the part OFF then ON. it from reversing and going negative. Figure 4. Event (Voltage) Based Sequencing

4681 F04

capacitance and load current, instead of TOFF_FALL.

Rev. AFor more information www.analog.com OPERATION the efficiency at light loads is lower than in discontinuous mode operation. However, continuous mode exhibits lower output ripple and less interference with audio circuitry, but may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this and turn off the offending channel. However, this fault is based on an ADC read and can take up to tCON- VERT to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction mode. If the part is set to discontinuous mode operation, as the inductor average current increases, the controller will automatically modify the operation from discontinuous mode to continuous mode. SWITCHING FREQUENCY AND PHASE The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes the PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other devices through PMBus command, NVM setting, or external configuration resistors as outlined in Table 3. As clock master , the LTM4681 will drive its open-drain SYNC_nn pin at the selected rate with a pulse width of 500ns. An external pull-up resistor between SYNC_nn and VDD33_nn is required in this case. Only one device connected to SYNC_nn should be designated to drive the pin. The LTM4681 will automatically revert to an external SYNC_nn input, disabling its own SYNC_ nn, as long as the external SYNC_nn frequency is greater than 80% of the programmed SYNC_nn frequency. The external SYNC input shall have a duty cycle between 20% and 80%. Whether configured to drive SYNC_nn or not, the LTM4681 can continue PWM operation using its own internal oscil- lator if an external clock signal is subsequently lost. The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS. The MFR_PWM_CONFIG command can be used to con- figure the phase of each channel. Desired phase can also be set from EEPROM or external configuration resistors as outlined in T able 3. Designated phase is the relation - ship between the falling edge of SYNC and the internal clock edge that sets the PWM latch to turn on the top power switch. Additional small propagation delays to the PWM control pins will also apply. Both channels must be off before the FREQUENCY_SWITCH and MFR_PWM_ CONFIG commands can be written to the LTM4681. The phase relationships and frequency options provide for numerous application options. Multiple LTM4681 mod - ules can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. PWM LOOP COMPENSATION The internal PWM loop compensation resistors RCOMPna of the LTM4681 can be adjusted using bit[4:0] of the MFR_PWM_COMP command for each controller . The transconductance (gm) of the LTM4681 PWM error amplifier can be adjusted using bit [7:5] of the MFR_ PWM_COMP command. These two loop compensation parameters can be programmed when device is in opera- tion. Refer to the Programmable Loop Compensation sub- section in the Applications Information section for further details. OUTPUT VOL TAGE SENSING All four channels in LTM4681 have differential amplifi - ers, which allow the remote sensing of the load voltage between V+ and V– pins. The telemetry ADC is also fully differential and makes measurements between V OSNSn+ and VOSNSn-voltages for both channels at the V + and V– pins, respectively. The maximum allowed 3.6V, but the LTM4681 design is limited to 3.3V. INTVCC/VBIAS POWER Power for the internal top and bottom MOSFET drivers and most other internal circuitry is derived from the INTV CC pin. When the RUNP pin is shorted to GND and the VBIAS is off, an internal 5.5V linear regulator supplies INTV CC

Rev. A For more information www.analog.com OPERATION power from SVIN_nn. If VBIAS is on at 5.5V output and VIN is higher than 7.0V, the 5.5V regulator is turned off and an internal switch is turned on, connecting V BIAS. Using the VBIAS allows the INTVCC power to be derived from a high efficiency internal source. VBIAS can provide power to the internal 3.3V linear regulators when VIN is present, which allows the LTM4681 controllers to be initialized and programmed even with channels off. The INTVCC_nn regulator is powered from the SVIN_nn pin, the power through the IC is equal to SVIN_nn • IINTVCCnn. The gate charge current is dependent on operating fre - quency. The INTVCC_nn regulator can supply up to 100mA, and the typical INTV CC_nn current for the LTM4681 is ~50mA. A 12V input voltage would equate to a difference of 7V per controller drop across the internal controller , when multiplied by 50mA equals a 350mW power loss. This loss can be eliminated by ultilizing the VBIAS regulator . Do not tie INTVCC_nn on the LTM4681 to an external sup- ply because INTV CC_nn will attempt to pull the external supply high and hit current limit, significantly increasing the die temperature. For applications where V IN is 5V, tie the SV IN_nn and INTVCC_nn pins together to the 5V input through a 1Ω resistor as shown in Test Circuit 2. OUTPUT CURRENT SENSING AND SUB MILLIOHM DCR CURRENT SENSING The LTM4681 use a unique sub-milliohm inductor cur - rent sensing technique that provides a high level signal to noise ratio while sensing very low signals in current mode operation. This enables higher conversion efficien- cies with the use of the internal sub-milliohm inductors in heavy load applications. The current limit threshold can be accurately set with the MFR_PWM_MODE[7] for High and Low range (see page 98). The internal DCR sensing network, thus current limit are calculated based on the DCR of the inductor at room tem- perature. The DCR of the inductor has a large temperature co efficient, approximately 3900ppm/°C. The temperature coefficient of the inductor is written to the MFR_IOUT_ CAL_GAIN_TC register. The external temperature is sensed near the inductor and used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. The current sensed is then digitized by the LTM4681’s telemetry ADC with an input range of ±128mV, a noise floor of 7µVRMS, and a peak-peak noise of approximately 46.5µV. The LTM4681 computes the induc- tor current using the DCR value stored in the IOUT_CAL_ GA IN command and the temperature coefficient stored in command MFR_IOUT_CAL_GAIN_TC. The resulting cur- rent value is returned by the READ_IOUT command. INPUT CURRENT SENSING To sense the total input current consumed by the LTM4681’s power stages , a sense resistor is placed between the supply voltage and the drain of the top N-channel MOSFET . The IIN_nn+ and IIN_nn– pins are con- nected to the sense resistor . The filtered voltage is ampli- fied by the internal high side current sense amplifier and digitized by the LTM4681’s telemetry ADC. The input cur- rent sense amplifier has three gain settings of 2x, 4x, and 8x set by the bit[6:5] of the MFR_PWM_CONFIG com- mand. The maximum input sense voltage for the three gain settings is 50mV, 25mV, and 10mV respectively. The LTM4681 computes the input current using the internal RSENSE value stored in the IIN_CAL_GAIN command. The resulting measured power stage current is returned by the READ_IIN command. I IN_01+, IIN_01– for controller 1 (channel 0 and 1), and I IN_23+, IIN_23– for controller 2 (channel 2 and 3). The LTM4681 uses a 1Ω resistor to measure the SVIN_nn pin supply current being consumed by each LTM4681 internal controller . This value is returned by the MFR_ READ_ICHIP command. The chip current is calculated by using the 1Ω value stored in the MFR_ICHIP_CAL_GAIN command. Refer to the subsection titled Input Current Sense Amplifier in the Applications Information section for further details. PolyPhase LOAD SHARING Multiple LTM4681s can be arrayed in order to provide a balanced load-share solution by bussing the necessary pins. Figure 50 illustrates a 8-Phase design sharing con- nections required for load sharing.

Rev. AFor more information www.analog.com OPERATION If an external oscillator is not provided, the SYNC_nn pins should only be enabled on one of the LTM4681s con - trollers. The other(s) should be programmed to disable SYNC_nn controllers using bit 4 of MFR_CONFIG_ALL. If an external oscillator is present, the chip with the SYNC_ nn pin enabled will detect the presence of the external clock and disable its output. Multiple channels need to tie all the VOSNSn+ pins together , and all the V OSNSn – pins together , COMPna and C OMPnb pins together as well. Do not assert bit[4] of MFR_ CONFIG_ALL except in a PolyPhase® application. The user must share the SYNC_nn, SHARE_CLK_ nn, FAUL Tn, and ALERTn pins of these parts. Be sure to use pull-up resistors on SYNC_nn, FAUL Tn, SHARE_CLK_nn and ALERTn. See Application figures. INTERNAL TEMPERATURE SENSE Temperature is measured using the internal diode-con - nected PNP transistors, and the outputs are connected to TSNS0 to TSNS3 pins corresponding to channel 0 to 3. These outputs are used for testing. T wo different currents are applied to the diode (nominally 2µA and 32µA) and the temperature is calculated from a ∆VBE measurement made with the internal 16-bit monitor ADC (see Figure 2 Block Diagram). The LTM4681 will only implement ∆V BE temperature sensing, therefore MFR_PWM_MODE bit[5] is reserved. RCONFIG (RESISTOR CONFIGURATION) PINS There are twelve input pins utilizing 1% resistors between these pins to select key operating parameters. The pins are ASEL_01, ASEL_23, FSWPH_01_CFG, FSWPH_23_CFG, VOUT0_CFG, VOUT1_CFG, VOUT2_CFG, VOUT3_CFG, VTRIM0_CFG, VTRIM1_CFG, VTRIM2_CFG, VTRIM3_CFG. If pins are floated, the value stored in the corresponding NVM command is used. If bit 6 of the MFR_CONFIG_ALL configuration command is asserted in NVM, the resistor input is ignored upon power-up except for ASEL which is always respected. The resistor configuration pins are only measured during a power-up reset or after a MFR_RESET or after a RESTORE_USER_ALL command is executed. The VOUTn_CFG pin settings are described in Table 1. These pins set the LTM4681 VOUT0 to VOUT3 output voltage coarse settings. If the pin is open, the VOUT_COMMAND command is loaded from NVM to determine the output voltage. The default setting is to have the switcher off unless the voltage configuration pins are installed. The VTRIMn_CFG pins in Table 2 are used to set the output voltage fine adjustment setting. Both combine to offer several distinct output voltages. The following parameters are set as a percentage of the output voltage if the RCONFIG pins are used to determine the output voltage: The FSWPH_CFG_nn pin settings are described in Table 3. This pin selects the switching frequency and phase of each channel. The phase relationships between the two channels and SYNC_nn pin are determined in Table 3. To synchronize to an external clock, the part should be put into external clock mode (SYNC_nn output disabled but frequency set to the nominal value). If no external clock is supplied, the part will clock at the programmed frequency. If the application is multiphase and the SYNC_nn signal between chips is lost, the parts will not operate at the designed phase even if they are programmed and trimmed to the same frequency. This may increase the ripple voltage on the output, possi- bly produce undesirable operation. If the external SYNC_nn signal is being generated internally and external SYNC_nn is not selected, bit 10 of MFR_PADS will be asserted. If no frequency is selected and the external SYNC_nn frequency is not present, a PLL_FAULT will occur. If the user does not wish to see the ALERT from a PLL_FAULT even if there is not a valid synchronization signal at power-up, the ALERT mask for PLL_FAULT must be written. See the description on SMBALERT_MASK for more details. If the SYNC_nn pin is connected between multiple ICs only one of the ICs should have the SYNC_nn pin enabled using the MFR_CONFIG_ ALL[4] = 0, and all other ICs should be configured to have the SYNC pin disabled with MFR_CONFIG_ALL[4] = 1.

ler . For more detail, refer to Table 5. Table 1. VOUTn _CFG Pin Strapping Look-Up Table for the

32.4 NVM NVM

VOUTn_CFG’s value over time. MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one’s product. Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the

Table 3. FSWPH_nn_CFG Pin Strapping Look-Up Table to Set the LTM4681’s Switching Frequency and Channel Phase-Interleaving Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b), nn = 0,1 or 2,3 Channels, set top resistor to 14.3k.

5.23 External** 0° 240° 010b 1b

4.22 External** 0° 120° 011b 1b

3.24 External** 60° 240° 101b 1b

2.43 External** 120° 300° 110b 1b

1.65 External** 90° 270° 001b 1b

0.787 External** 0° 180° 000b 1b

0 External** 120° 240° 100b 1b

every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product. the clock provided on the SYNC_nn pin, provided MFR_CONFIG_ALL[4] = 1b. RTOP = 14.3k is external to the part.

Rev. A For more information www.analog.com Table 4. ASEL_nn Pin Strapping Look-Up Table to Set the regardless of the NVM or ASEL resistor configuration values. such that its value is always within 3% of the value indicated in the table. Table 5. LTM4681 MFR_ADDRESS Command Examples 7-BIT 8-BIT 7 6 5 4 3 2 1 0 R/W Rail4 0x5A 0xB4 0 1 0 1 1 0 1 0 0 Global4 0x5B 0xB6 0 1 0 1 1 0 1 1 0 Default 0x4F 0x9E 0 1 0 0 1 1 1 1 0 Example 1 0x40 0x80 0 1 0 0 0 0 0 0 0 Example 2 0x41 0x82 0 1 0 0 0 0 0 1 0 Disabled2,3 1 0 0 0 0 0 0 0 0 Note 1: This table can be applied to the MFR_RAIL_ADDRESSn commands, but not the MFR_ADDRESS command. Note 2: A disabled value in one command does not disable the device, nor does it disable the global address. Note 3: A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. Note 4: It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A (7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or the MFR_RAIL_ADDRESSn commands. FAUL T DETECTION AND HANDLING A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include: n Input OV F AUL T Protection and UV Warning n Average Input OC Warn n Output OV/UV Fault and W arn Protection n Output OC Fault and Warn Protection n Internal control Die and Internal Module Overtemperature Fault and Warn Protection n Internal Undertemperature Fault and Warn Protection n CML Fault (Communication, Memory or Logic) n External Fault Detection via the Bidirectional F AUL Tn Pins In addition, the LTM4681 can map any combination of fault indicators to their respective FAUL Tn pin using the propagate FAUL Tn response commands, MFR_FAULT_ PROPAGATE. Typical usage of a FAUL Tn pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a OPERATION

Rev. AFor more information www.analog.com microcontroller to poll the fault commands. Alternatively, the FAUL Tn pins can be used as inputs to detect external faults downstream of the controller that require an imme- diate response. Any fault or warning event will always cause the ALERT_nn pin to assert low unless the fault or warning is masked by the SMBALERT_MASK. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1 or bias power is cycled or a MFR_RESET command is issued, or the RUNn pins are toggled OFF/ ON or the part is commanded OFF/ON via PMBus or an ARA command operation is performed. The MFR_FAULT_ PROPAGATE command determines if the FAUL Tn pins are pulled low when a fault is detected. Output and input fault event handling is controlled by the corresponding fault response byte as specified in Table 17 thru Table 21. Shutdown recovery from these types of faults can either be autonomous or latched. For autono- mous recovery, the faults are not latched, so if the fault conditions not present after the retry interval has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator com- ponents by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_ RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds. Status Registers and ALERT Masking Figure 5 summarizes the internal LTM4681 status regis- ters accessible by PMBus command. These contain indi- cation of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information. NONE OF THE ABOVE in the STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set. OPERATION In general, any asserted bit in a STATUS_x register also pulls the ALERT_ nn pin low. Once set, ALERT_ nn will remain low until one of the following occurs. n A CLEAR_FAULTS or MFR_RESET Command Is Issued n The Related Status Bit Is Written to a One n The Faulted Channel Is Properly Commanded Off and Back On n The LTM4681 Successfully T ransmits Its Address During a PMBus ARA n Bias Power Is Cycled With some exceptions, the SMBALERT_MASK command can be used to prevent the LTM4681 from asserting ALERT_nn for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT_nn is masked for all bits in channel n STATUS_VOUT, then ALERT_nn is effec- tively masked for the VOUT bit in STATUS_WORD for PAGE n. The BUSY bit in STATUS_BYTE also asserts ALERT_nn low and cannot be masked. This bit can be set as a result of various internal interactions with PMBus communi - cation. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in the Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. If masked faults occur immediately after power up, ALERT_nn may still be pulled low because there has not been time to retrieve all of the programmed masking information from EEPROM. Status information contained in MFR_COMMON and MFR_PADS can be used to further debug or clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALERT_nn pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD.

Figure 5. LTM4681 Status Register Summary per Controller

4681 F05

Rev. AFor more information www.analog.com OPERATION Mapping Faults to FAUL Tn Pins Channel-to-channel fault (including channels from mul - tiple LTM4681s) dependencies can be created by con - necting FAUL Tn pins together . In the event of an internal fault, one or more of the channels is configured to pull the bussed FAUL Tn pins low. The other channels are then configured to shut down when the FAUL Tn pins are pulled low. For autonomous group retry, the faulted channel is configured to let go of the FAUL Tn pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the FAUL Tn pin remains asserted low until either the RUNn pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUNn either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all faults cleared when either RUNn pin is toggled or , set bit 0 of MFR_CONFIG_ALL to a 1. The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands. Additional fault detection and handling capabilities are: Power Good Pins The PGOODn pins of the LTM4681 are connected to the open drains of internal MOSFETs. The MOSFETs turn on and pull the PGOODn pins low when the channel output voltage is not within the channel’ s UV and OV voltage thresholds. During TON_DELAY and TON_RISE sequenc- ing, the PGOODn pin is held low. The PGOODn pin is also pulled low when the respective RUNn pin is low. The PGOODn pin response is deglitched by an internal 100µs digital filter . The PGOODn pin and PGOOD status may be different at times due to communication latency of up to 10µs. CRC Protection The integrity of the NVM memory is checked after a power on reset. A CRC error will prevent the controller from leav- ing the inactive state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT_nn pin will be pulled low. NVM repair can be attempted by writing the desired configura- tion to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. The LTM4681 manufacturing section of the NVM is mir- rored. If both copies are corrupted, the “NVM CRC Fault” in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after being cleared by issuing a CLEAR_ FAULTS or writing a 1 to this bit, an irrecoverable internal fault has occurred. The user is cautioned to disable both output power supply rails associated with this specific part. There are no provisions for field repair of NVM faults in the manufacturing section. SERIAL INTERFACE The LTM4681 serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the NVM or an external resistor . In addition the LTM4681 always responds to the global broadcast address of 0x5A (7-bit) or 0x5B (7-bit). The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block. 8) write block. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTM4681. Communication Protection PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low. DEVICE ADDRESSING The LTM4681 offers five different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA).

Rev. A For more information www.analog.com OPERATION Global addressing provides a means of the PMBus master to address all LTM4681 devices on the bus. The LTM4681 global address is fixed 0x5A (7-bit) or 0xB4 (8-bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF . Commands sent are written to both channels simultaneously. Global command 0x5B (7-bit) or 0xB6 (8-bit) is paged and allows channel specific command of all LTM4681 devices on the bus. Other ADI device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged. Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTM4681. The value of the device address is set by a combination of the ASEL_nn configuration pin and the MFR_ ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Reading from rail addresses is also strongly discouraged. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTM4681 devices at global and rail addresses should be limited to command write operations. RESPONSES TO VOUT AND IIN/IOUT FAUL TS VOUT OV and UV conditions are monitored by compara- tors. The OV and UV limits are set in three ways: n As a Percentage of the V OUT if Using the Resistor Configuration Pins n In NVM if Either Programmed at the Factory or Through the GUI n By PMBus Command The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are based on average currents and can have a time latency of up to t CONVERT. The IOUT calculation accounts for the DCR and their temperature coefficient. The input current is equal to the voltage measured across the RSENSEn resis- tor divided by the resistors value as set with the MFR_ IIN_CAL_GAIN command. If this calculated input current exceeds the IN_OC_WARN_LIMIT the ALERT_nn pin is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT command. The digital processor within the LTM4681 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_ DELAY and can be from 120ms to 83.88 seconds in 10µs increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time. Output Overvoltage Fault Response A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term over - voltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on. However , the reverse output current is monitored while device is in OV fault. When it reaches the limit, both top and bottom MOSFETs are turned off. The top and bot - tom MOSFETs will keep their state until the overvoltage condition is cleared regardless of the PMBus VOUT_OV_ FAULT_RESPONSE command byte value. This hardware level fault response delay is typically 2µs from the over - voltage condition to BG asserted high. Using the VOUT_ OV_FAULT_RESPONSE command, the user can select any of the following behaviors: n OV Pull-Down Only (OV Cannot Be Ignored) n Shut Down (Stop Switching) Immediately—L atch Off n Shut Down Immediately —R etry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY Either the Latch Off or Retry fault responses can be de- glitched in increments of (0-7) • 10µs. See Table 17.

Rev. AFor more information www.analog.com OPERATION Output Undervoltage Response The response to an undervoltage comparator output can be the following: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately —R etry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. The UV responses can be deglitched. See Table 18. Peak Output Overcurrent Fault Response Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle- by-cycle basis. The value of the peak current limit is speci- fied in Electrical Characteristics table. The current limit circuit operates by limiting the COMPn maximum voltage. Since internal DCR sensing is used, the COMPn maximum voltage has a temperature dependency directly propor - tional to the TC of the DCR of the inductor . The LTM4681 automatically monitors the external temperature sensors and modifies the maximum allowed COMPn to compen- sate for this term. The IOUT_OC_FAULT_LIMIT section provides data points for I OUT Limiting on page 98. The overcurrent fault processing circuitry can execute the following behaviors: n Current Limit Indefinitely n Shut Down Immediately—Latch Off n Shut Down Immediately —R etry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. The overcurrent responses can be deglitched in incre - ments of (0-7) • 16ms. See Table 19. RESPONSES TO TIMING FAUL TS TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT condition is predicated upon detection of the VOUT_UV_ FAULT_LIMIT as the output is undergoing a SOFT_START sequence. The TON_MAX_ FAULT_LIMIT time is started after TON_DELAY has been reached and a SOFT_START sequence is started. The resolution of the TON_MAX _ FAULT_LIMIT is 10µs . If the VOUT_UV_FAULT _LIMIT is not reached within the TON_MAX_FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE command value. This response may be one of the following: n Ignore n Shut Down (Stop Switching) Immediately—L atch Off n Shut Down Immediately —R etry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. It is recommended TON_MAX_FAULT_ LIMIT always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user . See Table 21. RESPONSES TO V IN OV FAUL TS VIN overvoltage is measured with the ADC. The response is naturally deglitched by the 100ms typical response time of the ADC. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately —R etry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 21. RESPONSES TO OT/UT FAUL TS Internal Overtemperature Fault Response An internal temperature sensor protects against NVM damage. Above 85°C , no writes to NVM are recom - mended. Above 130°C, the internal overtemperature warn threshold is exceeded and the part disables the NVM and does not re-enable until the temperature has dropped to 125°C. When the die temperature exceed 160°C the inter- nal temperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal tempera- ture faults cannot be ignored. Internal temperature limits cannot be adjusted by the user . See T able 20.

Rev. A For more information www.analog.com OPERATION Overtemperature and Undertemperature Fault Response Four internal temperature sensors are used to sense the temperature of critical circuit elements like inductors and power MOSFETs on each channel. The OT_FAULT_ RESPONSE and UT_FAULT_ RESPONSE commands are used to determine the appropriate response to an overtem- perature and under temperature condition, respectively. If no external sense elements are used (not recommended) set the UT_FAULT_ RESPONSE to ignore— and set the UT_FAULT_LIMIT to 275°C. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately—Retr y Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 21. RESPONSES TO INPUT OVERCURRENT AND OUTPUT UNDERCURRENT FAUL TS Input overcurrent and output undercurrent are measured with the ADC. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately —R etry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. RESPONSES TO EXTERNAL FAUL TS When either FAUL Tn pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT_nn pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its FAUL Tn pin going low by modifying the MFR_FAULT_RESPONSE command. To avoid the ALERT_nn pin asserting low when FAUL Tn is pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask the ALERT using the SMBALERT_MASK command. FAUL T LOGGING The LTM4681 has fault logging capability. Data is logged into memory in the order shown in Table 23. The data is stored in a continuously updated buffer in RAM. When a fault event occurs, the fault log buffer is copied from the RAM buffer into NVM. Fault logging is allowed at tem - peratures above 85°C; however , retention of 10 years is not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 125°C. The fault log data remains in NVM until a MFR_FAULT _LOG_CLEAR command is issued. Issuing this command re-enables the fault log feature. Before re- enabling fault log, be sure no faults are present and a CLEAR_FAULTS command has been issued. When the LTM4681 powers-up or exits its reset state, it checks the NVM for a valid fault log. If a valid fault log exists in NVM, the “Valid Fault Log” bit in the STATUS_ MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTM4681 has received a MFR_FAULT_LOG_CLEAR command before fault logging will be re-enabled. The information is stored in EEPROM in the event of any fault that disables the controller on either channel. A FAUL Tn being externally pulled low will not trigger a fault logging event. BUS TIMEOUT PROTECTION The LTM4681 implements a timeout feature to avoid persistent faults on the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 30ms or the LTM4681 will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable. The LTM4681 allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout

Refer to Figure 7 for a legend. and Command Processing subsection of the Applications Information section for further details. Figure 6. PMBus Timing Diagram Table 6. Abbreviations of Supported Data Formats

Figure 7. PMBus Packet Protocol Diagram Element Key

4681 F07

4681 F08

4681 F09

4681 F10

4681 F11

4681 F12

4681 F13

4681 F14

Figure 8. Quick Command Protocol Figure 9. Send Byte Protocol Figure 10. Send Byte Protocol with PEC Figure 11. Write Byte Protocol Figure 12. Write Byte Protocol with PEC Figure 13. Write Word Protocol Figure 14. Write Word Protocol with PEC

Figure 15. Read Byte Protocol

4681 F15

4681 F16

4681 F17

4681 F18

4681 F19

4681 F20

Figure 16. Read Byte Protocol with PEC Figure 17. Read Word Protocol Figure 18. Read Word Protocol with PEC Figure 19. Block Read Protocol Figure 20. Block Read Protocol with PEC

Figure 21. Block Write – Block Read Process Call

4681 F21

4681 F22

4681 F23

4681 F24

Figure 22. Block Write – Block Read Process Call with PEC Figure 23. Alert Response Address Protocol Figure 24. Alert Response Address Protocol with PEC

Part II, Section 10.8.7, to communicate that it is busy. section for further details. protocols supported by this device. voltage including VOUT_MARGIN_HI. Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations Are Detailed in Table 8)

Rev. AFor more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be greater than VOUT_COMMAND. R/W Word Y L16 V Y 1.05 0x10CD VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be less than VOUT_COMMAND. R/W Word Y L16 V Y 0.95 0x0F33 VOUT_TRANSITION_ RATE 0X27 Rate the output changes when V OUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 0xD010 102 FREQUENCY_SWITCH 0x33 Switching frequency of the controller . R/W Word N L11 kHz Y 350kHz 0x2016 VIN_ON (SVIN_XX) 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 4.75 0xD130 VIN_OFF (SVIN_XX) 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 4.5 0xD120 VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1 0x119A VOUT_OV_FAULT_ RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 104 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075 0x1133 VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925 0x0ECD VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9 0x0E66 VOUT_UV_FAULT_ RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 105 IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 40.00 0xE280 IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00 107 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 34.0 0xE230 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 128.0 0xF200 100 OT_FAULT_RESPONSE 0x 50 Action to be taken by the device when an external overtemperature fault is detected, R/W Byte Y Reg Y 0xB8 109 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 125.0 0xEBE8 100 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –45.0 0xE530 101 UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an external undertemperature fault is detected. R/W Byte Y Reg Y 0xB8 109 VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5 0xD3E0 VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an input overvoltage fault is detected. R/W Byte Y Reg Y 0x80 104 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 4.65 0xD12A IIN_OC_WARN_LIMIT 0x5D Input supply overcurrent warning limit. R/W Word N L11 A Y 10.0 0xD280

Rev. A For more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 101 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 3.0 0xC300 101 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y L11 ms Y 5.0 0xCA80 102 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_ MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 107 TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y L11 ms Y 0.0 0x8000 102 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 3.0 0xC300 102 TOFF_MAX_WARN_ LIMIT 0x66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 0 0x8000 103 STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA 115 STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg NA 116 STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA 116 STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA 117 STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA 117 STATUS_TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA 118 STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA 118 STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA 119 READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA 121 READ_IIN 0x89 Measured input supply current. R Word N L11 A NA 121 READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA 121 READ_IOUT 0x8C Measured output current. R Word Y L11 A NA 121 READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA 121 READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not affect any other commands. R Word N L11 C NA 121 READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word Y L11 Hz NA 121 READ_POUT 0x96 Measured output power R Word Y L11 W N/A 121 READ_PIN 0x97 Calculated input power R Word Y L11 W N/A 122 PMBus_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg 0x22 113 MFR_ID 0x99 The manufacturer ID of the LTM4681 in ASCII. R String N ASC LT C 113 MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC 113

Rev. AFor more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including VOUT_OV_FAULT_LIMIT. R Word Y L16 V 3.6 0x0399 MFR_PIN_ACCURACY 0xAC Returns the accuracy of the READ_PIN command R Byte N % 5.0% 122 USER_DATA_00 0xB0 OEM RESERVED. Typically used for part serialization. R/W Word N Reg Y NA 113 USER_DATA_01 0xB1 Manufacturer reserved for L TpowerPlay. R/W Word Y Reg Y NA 113 USER_DATA_02 0xB2 OEM RESERVED. Typically used for part serialization R/W Word N Reg Y NA 113 USER_DATA_03 0xB3 An NVM word available for the user . R/W Word Y Reg Y 0x0000 113 USER_DATA_04 0xB4 An NVM word available for the user . R/W Word N Reg Y 0x0000 113 MFR_EE_UNLOCK 0xBD Contact factory. 129 MFR_EE_ERASE 0xBE Contact factory. 129 MFR_EE_DATA 0xBF Contact factory. 129 MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D 87 MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 88 MFR_FAULT_ PROPAGATE 0xD2 Configuration that determines which faults are propagated to the FAUL T pin. R/W Word Y Reg Y 0x6993 110 MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0x28 91 MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC7 90 MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAUL T pin is externally asserted low. R/W Byte Y Reg Y 0xC0 112 MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. R Byte N Reg 0xC0 108 MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_ IOUT since last MFR_CLEAR_PEAKS. R Word Y L11 A NA 122 MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back R/W Byte N Reg 0x00 123 MFR_RETRY_DELAY 0xDB Retry interval during FAUL T retry mode. R/W Word Y L11 ms Y 250.0 0xF3E8 103 MFR_RESTART_DELAY 0xDC Minimum time the RUN pin is held low by the LTM4681. R/W Word Y L11 ms Y 150.0 0xF258 103 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA 122 MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA 122 MFR_TEMPERATURE_1_ PEAK0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA 122 MFR_READ_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS R Word N L11 A NA 122 MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte N NA 115 MFR_READ_ICHIP 0xE4 Measured supply current of the SV IN pin R Word N L11 A NA 123 MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA 119

Rev. A For more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE MFR_ADDRESS 0xE6 Sets the 7-bit I 2C address byte, Ch 0 and 1 R/W Byte N Reg Y 0x4F 87 MFR_ADDRESS 0xE6 Sets the 7-bit I 2C address byte, Ch 2 and 3 R/W Byte N Reg Y 0x4E 87 MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTM4681 and revision R Word N Reg 0x414X 113 MFR_IIN_CAL_GAIN 0xE8 The resistance value of the input current sense element in mΩ. R/W Word N L11 mΩ Y 2.0 0xC200 MFR_FAULT_LOG_ STORE 0xEA Command a transfer of the fault log from RAM to EEPROM. Send Byte N NA 125 MFR_INFO 0x Contact factory. 129 MFR_IOUT_CAL_GAIN 0xDA SET AT FACTORY. Typical 0.4mΩ R Word Y L11 mΩ 0.4 typical 0xD01A MFR_FAULT_LOG_ CLEAR 0xEC Initialize the EEPROM block reserved for fault logging. Send Byte N NA 129 MFR_FAULT_LOG 0xEE Fault log data bytes. R Block N Reg Y NA 125 MFR_COMMON 0xEF Manufacturer status bits that are common across multiple ADI chips. R Byte N Reg NA 120 MFR_COMPARE_USER_ ALL 0xF0 Compares current command contents with NVM. Send Byte N NA 124 MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last MFR_ CLEAR_PEAKS. R Word N L11 C NA 123 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 92 MFR_IOUT_CAL_GAIN_ TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF ppm/ Y 3900 0x0F3C MFR_ICHIP_CAL_GAIN 0xF7 The resistance value of the V IN pin filter element in mΩ. R/W Word N L11 mΩ Y 1000 0x03E8 MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor . R/W Word Y CF Y 0.995 0x3FAE 100 MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor with respect to –273.1°C R/W Word Y L11 C Y 0.0 0x8000 100 MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to adjust common parameters. R/W Byte Y Reg Y 0x80 87 MFR_REAL_TIME 0xFB 48-bit share-clock counter value. R Block N CF NA 126 MFR_RESET 0xFD Commanded reset without requiring a power down. Send Byte N NA 89 Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. Note 2: Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”. Note 3: The LTM4681 contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however , the contents and meaning of these commands can change without notice. Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written. Note 5: Writing to commands not published in Table 7 is not permitted. Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s data sheet for each part for a complete definition of a command’s function. ADI strives to keep command functionality compatible between all ADI devices. Differences may occur to address specific product requirements.

Table 8. Data Format Abbreviations Reg Register PMBus data field b[15:0] or b[7:0]. Bit field meaning is defined in detailed PMBus Command Description. CF Custom Format V alue is defined in detailed PMBus Command Description. This is often an unsigned or two’s complement integer scaled by an MFR specific constant. ASCII Format A variable length string of text characters conforming to ISO/IEC 8859-1 standard.

Rev. A For more information www.analog.com APPLICATIONS INFORMATION VIN TO VOUT STEP-DOWN RATIOS There are restrictions in the maximum VIN and VOUT step- down ratio that can be achieved for a given input voltage. Each output of the LTM4681 is capable of 95% duty cycle at 500kHz, but the VIN to VOUT minimum dropout is still a function of its load current and will limit output current capability related to high duty cycle on the topside switch. Minimum on-time t ON(MIN) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t ON(MIN) < D/f SW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 60ns. See Note 6 in the Electrical Characteristics section for output current guideline. INPUT CAPACITORS The LTM4681 module should be connected to a low AC impedance DC source. For the regulator input, four 22µF input ceramic capacitors are used to handle the RMS ripple current. A 47µF to 150µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter , the switching duty-cycle can be estimated as: Dn = VOUTn VINn Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICINn(RMS) = IOUTn(MAX) η% • Dn • 1−Dn( ) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher- rated electrolytic aluminum capacitor , or a polymer capac- itor . Application Note 77 can be utilized to help calculate ripple current cancellation for multiphase applications. OUTPUT CAPACITORS The LTM4681 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor , a low ESR polymer capacitor or ceramic capacitor . The typical output capacitance range for each output is from 400µF to 1000µF. Additional out- put filtering may be required by the system designer , if further reduction of output ripple or dynamic transient spikes is required. Table 13 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 10A to 20A step, 10A/µs transient each channel. Table 13 optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 13 matrix, and the L TPowerCAD Design Tool will be provided for stability analysis. Multiphase operation reduces effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduc- tion versus output ripple current cancellation, but the out- put capacitance should be considered carefully as a func- tion of stability and transient response. The L TPowerCAD Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω resistor can be placed in series from V OUTn to the VOSNS0+ pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The LTM4681’s stability compensation can be adjusted using two external capacitors (COMPna , COMPnb), and the MFR_PWM_COMP commands. LIGHT LOAD CURRENT OPERATION The LTM4681 has two modes of operation including high efficiency, discontinuous conduction mode or forced continuous conduction mode. The mode of operation is configured by bit 0 of the MFR_PWM_MODEn command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode). If a channel is enabled for discontinuous mode opera - tion, the inductor current is not allowed to reverse. The reverse current comparator , IREV, turns off the bottom

Rev. AFor more information www.analog.com APPLICATIONS INFORMATION MOSFET (MBn) just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller can operate in discontinuous (pulse- skipping) operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor cur - rent is determined solely by the voltage on the COMPn pin. In this mode, the efficiency at light loads is lower than in discontinuous mode operation. However , continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this (if SV IN_nn is connected to V IN01 and/or VIN23) and turn off the offending channel. However , this fault is based on an ADC read and can nominally take up to 100ms to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduc- tion operation. SWITCHING FREQUENCY AND PHASE The switching frequency of the LTM4681’ s channels is established by its analog phase-locked-loop (PLL) locking on to the clock present at the module’s SYNC_nn pin. The clock waveform on the SYNC_nn pin can be generated by the LTM4681’s internal circuitry when an external pull-up resistor to 3.3V (e.g., VDD33) is provided, in combination with the LTM4681 control IC’s FREQUENCY_SWITCH command being set to one of the following supported val- ues: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz, 750kHz. In this configuration, the module is called a “sync master”: (using the factory-default setting of MFR_ CONFIG_ALL[4] = 0b), SYNC_nn becomes a bidirectional open-drain pin, and the LTM4681 pulls SYNC logic low for nominally 500ns at a time, at the prescribed clock rate. The SYNC signal can be bused to other LTM4681 modules (configured as “sync slaves”), for purposes of synchronizing switching frequencies of multiple modules within a system—but only one LTM4681 internal control- lers should be configured as a “sync master”; the other LTM4681(s) should be configured as “sync slaves”. The most straightforward way is to set its FREQUENCY_ SWITCH command to 0x 0000 and MFR_CONFIG _ ALL[4] = 1b. This can be easily implemented with resis - tor pin-strap settings on the FSWPH_nn_CFG pin (see Table 3). Using MFR_CONFIG_ALL[4] = 1b, the LTM4681s SYNC pin becomes a high impedance input, only—i.e., it does not drive SYNC low. The module synchronizes its frequency to that of the clock applied to its SYNC pin. The only shortcoming of this approach is: in the absence of an externally applied clock, the switching frequency of the module will default to the low end of its frequency- synchronization capture range (~225kHz). If fault-tolerance to the loss of an externally applied SYNC clock is desired, the FREQUENCY_SWITCH command of a “sync slave” can be left at the nominal target switching frequency of the application, and not 0x0000 However , it is then still necessary to configure MFR_CONFIG_ ALL[4] = 1b. With this combination of configurations, the LTM4681’s SYNC_nn pins becomes a high imped - ance input and the module synchronizes its frequency to that of the externally applied clock, provided that the frequency of the externally applied clock exceeds ~½. of the target frequency ( FREQUENCY_SWITCH). If the SYNC clock is absent, the module responds by operating at its target frequency, indefinitely. If and when the SYNC clock is restored, the module automatically phase-locks to the SYNC clock as normal. The only shortcoming of this approach is: the EEPROM must be configured per above guidance; resistor pin-strapping options on the FSWPH_nn_CFG pin alone cannot provide fault-tolerance to the absence of the SYNC clock. The FREQUENCY_SWITCH register can be altered via I2C commands, but only when switching action is disengaged, i.e., the module’s outputs are turned off. The FREQUENCY_ SWITCH command takes on the value stored in NVM at SV IN power-up, but is overridden according to a resistor pin-strap applied between the FSWPH_nn_CFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3 highlights available resistor pin-strap and corresponding FREQUENCY_SWITCH settings. The relative phasing of all active channels in a PolyPhase rail should be optimally phased. The relative phasing of each rail is 360°/n, where n is the number of phases in the rail. MFR_PWM_CONFIG[2:0] configures channel relative

corresponding MFR_PWM_CONFIG[2:0] settings. disengaged, i.e., the module’s outputs are turned off. ance until NVM contents have been downloaded to RAM. Table 9. Recommended Switching Frequency for Various VIN- range of current limiting is a part of loop design. loop stability changes if current limit range is adjusted. a warning if too much average output current is detected. readback calculated output power .

Rev. AFor more information www.analog.com APPLICATIONS INFORMATION MINIMUM ON-TIME CONSIDERATIONS Minimum on-time, t ON(MIN), is the smallest time dura - tion that the LTM4681 is capable of turning on the top MOSFET . It is determined by internal timing delays and the gate charge required to turn on the top MOSFET . Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUTn VINn • fOSC If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTM4681 is 60ns. VARIABLE DELAY TIME, SOFT-START AND OUTPUT VOL TAGE RAMPING The LTM4681 must enter its run state prior to soft-start. The RUNn pins are released after the part initializes and SV IN_nn is greater than the VIN_ON threshold. If multiple LTM4681s are used in an application, they should be con- figured to share the same RUNn pins. They all hold their respective RUNn pins low until all devices initialize and SV IN exceeds the VIN_ON threshold for all devices. The SHARE_CLK_nn pin assures all the devices connected to the signal use the same time base. After the RUNn pin releases, the controller waits for the user-specified turn-on delay (TON_DELAYn) prior to ini- tiating an output voltage ramp. Multiple LTM4681s and other ADI parts can be configured to start with variable delay times. T o work correctly, all devices use the same timing clock (SHARE_CLK) and all devices must share the RUNn pin. This allows the relative delay of all parts to be synchro - nized. The actual variation in the delay will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Analog Devices ICs are configured to allow the fastest SHARE_CLK signal to control the tim- ing of all devices). The SHARE_CLK signal can be ±10% in frequency, thus the actual time delays will have some variance. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_RISEn command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISEn to any value less than 0.250ms. The LTM4681 performs the necessary math internally to assure the voltage ramp is controlled to the desired slope. However , the voltage slope can not be any faster than the VOUTn fundamental limits of the power stage. The number of tON(MIN) steps in the ramp is equal to TON_RISE/0.1ms. Therefore, the shorter the TON_RISEn time setting, the more discrete steps in the soft-start ramp appear . The LTM4681 PWM always operates in discontinuous mode during the TON_RISEn operation. In discontinuous mode, the bottom MOSFET (MBn) is turned off as soon as reverse current is detected in the inductor . This allows the regulator to start up into a pre-biased load. There is no analog tracking feature in the LTM4681; how- ever , two outputs can be given the same TON_RISEn and TON_DELAYn times to achieve ratiometric rail tracking. Because the RUNn pins are released at the same time and both units use the same time base (SHARE_CLK), the outputs track very closely. If the circuit is in a PolyPhase configuration, all timing parameters must be the same. DIGITAL SERVO MODE For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE command. In digital servo mode, the LTM4681 will adjust the regulated output voltage based on the ADC voltage reading. Every 90ms the digital servo loop will step the LSB of the DAC (nominally 1.375mV or 0.6875mV depending on the voltage range bit) until the output is at the correct ADC reading. At power-up this mode engages after TON_MAX_FAULT_LIMIT unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to 0 (infinite), the servo begins after TON_RISE is com- plete and V OUT has exceeded the VOUT_UV_FAULT_LIMIT.

1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT
3. After the VOUT_UV_FAULT_LIMIT

or the IOUT_OC_FAULT_LIMIT is no longer active.

1. After the TON_MAX_FAULT_LIMIT

The maximum rise time is limited to 1.3 seconds. of the control loops have the digital servo mode enabled. other due to slight differences in the reference circuits.

4681 F25

Figure 25. Timing Controlled VOUT Rise Figure 26. TOFF_DELAY and TOFF_FALL

Rev. AFor more information www.analog.com APPLICATIONS INFORMATION UNDERVOL TAGE LOCKOUT The LTM4681 is initialized by an internal threshold-based UVLO where VIN must be approximately 4V and INTVCC_ nn, VDD33_nn, and VDD25_nn must be within approximately 20% of their regulated values. In addition, VDD33_nn must be within approximately 7% of the targeted value before the RUNn pin is released. After the part has initialized, an additional comparator monitors V IN. The VIN_ON thresh- old must be exceeded before the power sequencing can begin. When V IN drops below the VIN_OFF threshold, the SHARE_CLK_nn pin will be pulled low and V IN must increase above the VIN_ON threshold before the con - troller will restart. The normal start-up sequence will be allowed after the VIN_ON threshold is crossed. If FAUL Tn is held low when V IN is applied, ALERTnn will be asserted low even if the part is programmed to not assert ALERTnn when FAUL Tn is held low. If I2C communication occurs before the LTM4681 is out of reset and only a portion of the command is seen by the part, this can be interpreted as a CML fault. If a CML fault is detected, ALERTnn is asserted low. It is possible to program the contents of the NVM in the application if the V DD33_nn supply is externally driven directly to VDD33_nn or through VBIAS. This will activate the digital portion of the LTM4681 without engaging the high voltage sections. PMBus communications are valid in this supply configuration. If V IN has not been applied to the LTM4681, bit 3 (NVM Not Initialized) in MFR_COMMON will be asserted low. If this condition is detected, the part will only respond to addresses 5A and 5B. To initialize the part issue the following set of commands: global address 0x5B command 0xBD data 0x2B followed by global address 5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ALL. When VIN is applied a MFR_RESET command must be issued to allow the PWM to be enabled and valid ADC conversions to be read. FAUL T DETECTION AND HANDLING The LTM4681 FAUL Tn pins are configurable to indicate a variety of faults including OV , UV , OC, OT , timing faults, and peak over current faults. In addition, the FAUL Tn pins can be pulled low by external sources indicating a fault in some other portion of the system. The fault response is configurable and allows the following options: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately —R etry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY Refer to the PMBus section of the data sheet and the PMBus specification for more details. The OV response is automatic. If an OV condition is detected, TGn goes low and BGn is asserted. Fault logging is available on the LTM4681. The fault log- ging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault. If the LTM4681 internal temperature is in excess of 85°C, writes into the NVM (other than fault logging) are not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all NVM communication is disabled until the die temperature drops below 120°C. OPEN-DRAIN PINS The LTM4681 has the following open-drain pins: 3.3V Pins 1. F AUL Tn 2. SYNC_ nn 3. SHARE_CLK_ nn 4. PGOODn 5V Pins ( 5V pins operate correctly when pulled to 3.3V.) 1. RUNn 2. ALERT _nn 3. SCL_ nn 4. SDA_ nn

Rev. A For more information www.analog.com APPLICATIONS INFORMATION All the above pins have on-chip pull-down transistors that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, there is plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor . Unless there are transient speed issues associated with the RC time constant of the resistor pull- up and parasitic capacitance to ground, a 10k resistor or larger is generally recommended. For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time con- stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA_nn and SCL_ nn pins with the time constant set to 1/3 the rise time is: RPULLUP = tRISE 3•100pF = 1k The closest 1% resistor value is 1k. Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capaci- tance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is a one time constant. The SYNC_nn pin has an on-chip pull-down transistor with the output held low for nominally 500ns. If the internal oscil- lator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows: RPULLUP = 2µs – 500ns 3•100pF = 5k The closest 1% resistor is 4.99k. If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and deter - mine if the RC time constant is too long for the applica - tion. If possible reduce the parasitic capacitance. If not, reduce the pull-up resistor sufficiently to assure proper timing. The SHARE_CLK_nn pull-up resistor has a similar equation with a period of 10µs and a pull-down time of 1µs. The RC time constant should be approximately 3µs or faster . PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION The LTM4681 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector . The PLL is locked to the falling edge of the SYNC_nn pin. The phase relationship between the PWM controller and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_ CONFIG command. For PolyPhase applications, it is recommended that all the phases be spaced evenly. Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°. The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complemen- tary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 250kHz and 1MHz. Nominal parts will have a range beyond this; however , operation to a wider frequency range is not guaranteed. The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_ SPECIFIC command is asserted and the ALERT_ nn pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the ALERT_nn pin assert if a PLL_FAULT occurs, the SMBALERT_MASK command can be used to prevent the alert. If the SYNC signal is not clocking in the application, the nominal programmed frequency will control the PWM circuitry. However , if multiple parts share the SYNC_nn pins and the signal is not clocking, the parts will not be synchronized and excess voltage ripple on the output may be present. Bit 10 of MFR_PADS will be asserted low if this condition exists. If the PWM signal appears to be running at too high a frequency, monitor the SYNC_nn pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise versus the intended signal. Review routing of digital control signals and minimize crosstalk to the SYNC signal

to share one SYNC_nn pin in PolyPhase configurations. programmed to the nominal desired value. the input current sense resistor . mand is used to measure the internal controller current. mize the loop over a wide range of output capacitors. and zero location, as shown in Figure 28. RCOMPn using the L TPowerCAD tool. Figure 27. Programmable Loop Compensation Figure 28. Error Amp gm Adjust

4681 F28

4681 F27

lish these settings prior to compensation calculation. filter sets the dominant pole-zero loop compensation. Figure 29. RCOMP Adjust

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the load rise time is limited to approximately 25 • CLOAD. limiting the charging current to about 200mA. should be set to the same value. application example Figure 50. to be enabled and valid ADCs to be read.

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Figure 30. Controller Connection

Rev. A For more information www.analog.com APPLICATIONS INFORMATION Because of the adapter’s limited current sourcing capabil- ity, only the LTM4681s, their associated pull-up resistors and the I 2C pull-up resistors should be powered from the VDD33 3.3V supply. In addition any device sharing the I2C bus connections with the LTM4681 should not have body diodes between the SDA/SCL pins and their respective VDD node because this will interfere with bus communication in the absence of system power . If VIN is applied, the DC1613A will not supply the power to the LTM4681s on the board. It is recommended the RUNn pins be held low or no voltage configuration resistors inserted to avoid providing power to the load until the part is fully configured. The LTM4681 is fully isolated from the host PC’s ground by the DC1613A.The 3.3V from the adapter and the LTM4681 VDD33_nn pin must be driven to each LTM4681 internal controllers with a separate PFET . If both VIN and VBIAS are not on, the V DD33_nn pins can be in parallel because the on-chip LDO is off. The controller’ s 3.3V current limit is 100mA but typical V DD33_nn currents are under 15mA. The VDD33_nn does back drive the INTV CC/ VBIAS pin. Normally this is not an issue if VIN is open. LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL POWER L TpowerPlay (Figure 31) is a powerful Windows-based development environment that supports Analog Devices digital power system management ICs including the LTM4681. The software supports a variety of differ - ent tasks. L TpowerPlay can be used to evaluate Analog Devices ICs by connecting to a demo board or the user application. L TpowerPlay can also be used in an offline mode (with no hardware present) in order to build mul - tiple IC configuration files that can be saved and reloaded at a later time. L TpowerPlay provides unprecedented diag- nostic and debug features. It becomes a valuable diagnos- tic tool during board bring-up to program or tweak the power system or to diagnose power issues when bring up rails. L TpowerPlay utilizes Analog Devices’s USB-to-I2C/ SMBus/PMBus adapter to communication with one of the many potential targets including the DC2924A, DC3082A demo boards, or a customer target system. The software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. A great deal of context sensitive help is available with LTpowerPlay along with several tutorial demos. : PMBus COMMUNICATION AND COMMAND PROCESSING The LTM4681 internal controllers have one deep buffer to hold the last data written for each supported com - mand prior to processing as shown in Figure 32, Write Command Data Processing. When the part receives a new command from the bus, it copies the data into the Write Command Data Buffer , indicates to the internal processor that this command data needs to be fetched, and con - verts the command to its internal format so that it can be executed. T wo distinct parallel blocks manage command buffering and command processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. Command data buffering handles incoming PMBus writes by storing the command data to the Write Command Data Buffer and marking these commands for future processing. The internal processor runs in parallel and handles the sometimes slower task of fetching, con- verting and executing commands marked for processing. Some computationally intensive commands (e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long rela- tive to PMBus timing. If the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. The part indicates when internal calculations are in pro - cess via bit 5 of MFR_COMMON (“calculations not pend- ing”). When the part is busy calculating, bit 5 is cleared. When this bit is set, the part is ready for another com - mand. An example polling loop is provided in Figure 33 which ensures that commands are processed in order while simplifying error handling routines.

Figure 31. L TpowerPlay Screen Shot

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Figure 32. Write Command Data Processing

correlate thermal performance to one’s own application.

1. θJA, the thermal resistance from junction to ambient,
2. θJCbottom, the thermal resistance from junction to the
3. θJCtop, the thermal resistance from junction to top of

tions don’t generally match the user’s application. board is described in JESD51-9. resistances are external to the µModule package.

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Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients

Rev. A For more information www.analog.com APPLICATIONS INFORMATION As a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal oper- ating conditions of a µModule regulator . For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the µModule package— as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4681, be aware there are multiple power devices and components dissipating power , with a con- sequence that the thermal resistances relative to differ - ent junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity— but also, not ignoring practical realities— an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA soft - ware is used to accurately build the mechanical geometry of the LTM4681 and the specified PCB with all of the cor- rect material coefficients along with accurate power loss source definitions ; (2) this model simulates a software- defined JEDEC environment consistent with JESD51-9 and JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4681 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a con- trolled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JE SD51-12-defined θ values provided in the Pin Configuration section of this data sheet. The 5V, 8V, and 12V power loss curves in Figure 35, Figure 36 and Figure 37, respectively, can be used in coor- dination with the load current derating curves in Figure 41 to Figure 46 for calculating an approximate θ JA thermal resistance for the LTM4681 with various airflow condi - tions and without heat sinks. These thermal resistances represent demonstrated performance of the LTM4681 on hardware; a 8-layer FR4 PCB measuring 215mm × 160mm × 1.6mm using 2oz copper on all layers. The power loss curves are taken at room temperature, and are increased with multiplicative factors of 1.35 when the junction temperature reaches 125°C. The derating curves are plotted with the LTM4681’s paralleled outputs initially sourcing up to 120A and the ambient temperature at 25°C. The output voltages are 0.9V, 1.5V and 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measure - ments in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 125°C maximum while lowering output cur- rent or power while increasing ambient temperature. The decreased output current decreases the internal module loss as ambient temperature is increased. The monitored junction temperature of 125°C minus the ambient operat- ing temperature specifies how much module temperature rise can be allowed. As an example in Figure 43, the load current is derated to ~90A at ~65°C ambient with no air or heat sink and the room temperature (25°C) power loss for this 12VIN to 1.5VOUT at 90AOUT condition is ~9.5W. A 12.8W loss is calculated by multiplying the ~9.5W room temperature loss from the 12V IN to 1.5VOUT power loss curve at 90A (Figure 37), with the 1.35 multiplying factor .

Table 13. Single Channel Output Voltage vs Capacitor Selection, 10A to 20A Load Step with 10A/µs Slew Rate

Table 14. Single Channel Output Voltage vs Capacitor Selection, All Ceramic Configuration, 10A to 20A Load Step with 10A/µs Slew Rate

Table 15. Dual Connected Channels Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 10A to 30A Load Step with 20A/µs Slew Rate

Table 16. Quad Connected Channels Output Voltage vs Capacitor Selection, Bulk and Ceramic Cap Configuration, 10A to 40A Load Step with 15A/µs Slew Rate

Figure 35. 5VIN Power Loss Curve Figure 38. 5VIN to 0.9VOUT Figure 36. 8VIN Power Loss Curve Figure 39. 8VIN to 0.9VOUT Derating Figure 37. 12VIN Power Loss Curve Figure 40. 12VIN to 0.9VOUT Derating

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Figure 41. 5VIN to 1.5VOUT Figure 42. 8VIN to 1.5VOUT Derating Figure 43. 12VIN to 1.5VOUT

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Figure 44. 5VIN to 3.3VOUT

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Figure 45. 8VIN to 3.3VOUT Figure 46. 12VIN to 3.3VOUT

Rev. A For more information www.analog.com APPLICATIONS INFORMATION EMI PERFORMANCE The SWn pin provides access to the midpoint of the power MOSFETs in LTM4681’s power stages. Connecting an optional series RC network from SWn to GND can dampen high frequency (~30MHz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. The RC network is called a snubber circuit because it dampens (or “snubs”) the reso- nance of the parasitics, at the expense of higher power loss. To use a snubber , choose first how much power to allocate to the task and how much PCB real estate is avail- able to implement the snubber . For example, if PCB space allows a low inductance 0.5W resistor to be used then the capacitor in the snubber network (CSW) is computed by: CSW = PSNUB VINn(MAX) 2 • fSW where VINn(MAX) is the maximum input voltage that the input to the power stage (VINn) will see in the application, and fSW is the DC/DC converter’ s switching frequency of operation. CSW should be NPO, C0G or X7R-type (or better) material. The snubber resistor (RSW) value is then given by: RSW = 5nH CSW The snubber resistor should be low ESL and capable of withstanding the pulsed currents present in snubber cir- cuits. A value between 0.7Ω and 4.2Ω is normal. A 2.2nF snubber capacitor is a good value to start with in series with the snubber resistor to ground. The no load input quiescent current can be monitored while selecting different RC series snubber components to get a increased power loss versus switch node ringing attenuation. SAFETY CONSIDERATIONS The LTM4681 modules do not provide galvanic isolation from V IN to V OUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET . This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The device does support over current and overtemperature protection. LAYOUT CHECKLIST/EXAMPLE The high integration of LTM4681 makes the PCB board layout very simple and easy. However , to optimize its electrical and thermal performance, some layout consid- erations are still necessary. n Use large PCB copper areas for high current paths, including VINn, GND and VOUTn. It helps to minimize the PCB conduction loss and thermal stress. n Place high frequency ceramic input and output capac- itors next to the VINn, GND and VOUTn pins to minimize high frequency noise. n Place a dedicated power ground layer underneath the module. n To minimize the via conduction loss and reduce mod- ule thermal stress, use multiple vias for interconnec- tion between top layer and other power layers.

resistor if input current monitoring is used. Figure 47. Recommended PCB Layout Package Top View n Bring out test points on the signal pins for monitoring.

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Figure 48. Quad 31.25A DC/DC µModule Regulator with I2C/SMBus/PMBus Serial Interface

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Figure 49. 0.75V and 1V Outputs at 60A with Providing I2C/SMBus/PMBus Serial Interface

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Figure 50. T wo Paralleled LTM4681 Producing 0.9VOUT at 250A. Integrated Power System Management Features Accessible

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Figure 51. 1V/60A and 0.75V/60A Outputs Generated from 5V Power Input and Providing I2C/SMBus/PMBus Serial Interface

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Figure 52. 6-Phase Operation Producing 0.9V at 187A, 2 Phase for 1V at 30A, and 1.2V at 30A. Power System Management

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Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device. will have a different programmed address. will respond to read commands as if PAGE were set to 0x00 (Channel 0 results). This command has one data byte. may be sent with PAGE_PLUS_WRITE. a non-paged command, the Page Number byte is ignored. mand that has two data bytes is shown in Figure 53.

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Figure 53. Example of PAGE_PLUS_WRITE the data returned by the command, all in one communication packet .

4681 F54

Figure 54. Example of PAGE_PLUS_READ data from a non-paged command, the Page Number byte is ignored. fault for Invalid/Unsupported Data. EE_UNLOCK, and STORE_USER_ALL commands. respective bits in the STATUS commands. Enable writes to all commands when WRITE_PROTECT is set to 0x00.

Rev. AFor more information www.analog.com PMBus COMMAND DETAILS MFR_ADDRESS The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device. Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore, the ASEL_nn pins are still used to determine the LSB of the chan- nel address. If the ASEL_01 and ASEL_23 pins are both open, the LTM4681 will use the address value stored in NVM. If the ASEL_nn pins are open, the LTM4681 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail. The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTL Y the same value, the LTM4681 will detect bus contention and may set a CML communications fault. Setting this command to a value of 0x80 disables rail device addressing for the channel. This command has one data byte. GENERAL CONFIGURATION COMMANDS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 MFR_CHAN_CONFIG General purpose configuration command common to multiple ADI products. BIT MEANING

7 Reserved

6 Reserved

5 Reserved

4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF . 3 Enable Short Cycle recognition if this bit is set to a 1. 2 SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled. 1 No FAUL T ALERT, ALERT is not pulled low if FAUL T is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated on FAUL T.

0 Disables the V

OUT decay value requirement for MFR_RETRY_TIME and tOFF(MIN) processing. When this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high. This command has one data byte.

Rev. A For more information www.analog.com PMBus COMMAND DETAILS A ShortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned ON and OFF through either the RUN pin and or the PMBus OPERATION command. If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following: 1. Immediately tri-state the PWM channel output; 2. Start the retry delay timer as specified by the tOFF(MIN). 3. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPECIFIC bit #1 will assert. If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following: 1. Stop ramping down the PWM channel output; 2. Immediately tri-state the PWM channel output; 3. Start the retry delay timer as specified by the tOFF(MIN). 4. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPEFIFIC bit #1 will assert. If the ShortCycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user . MFR_CONFIG_ALL General purpose configuration command common to multiple ADI products. BIT MEANING

7 Enable Fault Logging

6 Ignore Resistor Configuration Pins

5 Mask PMBus, Part II, Section 10.9.1 Violations

4 Disable SYNC output

3 Enable 255ms PMBus timeout

2 A valid PEC required for PMBus writes to be accepted. If this bit is not set, the part will accept commands with invalid PEC.

1 Enable the use of PMBus clock stretching

0 Execute CLEAR_FAULTS on rising edge of either RUN pin. This command has one data byte. ON/OFF/MARGIN COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg Y 0x1E OPERATION 0x01 Operating mode control. On/off, margin high and margin low. R/W Byte Y Reg Y 0x80 MFR_RESET 0xFD Commanded reset without requiring a power-down. Send Byte N NA

Rev. AFor more information www.analog.com ON_OFF_CONFIG The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off. Supported Values: VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte. OPERATION The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOL TAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is sequence off. If V IN is applied to a part with factory default programming and the VOUT_CONFIG resistor configuration pins are not installed, the outputs will be commanded off. The part defaults to the Sequence Off state. This command has one data byte. Supported Values: VALUE MEANING 0xA8 Margin high. 0x98 Margin low. 0x80 On (V OUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). 0x40* Soft off (with sequencing). 0x00* Immediate off (no sequencing). *Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set. Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte. MFR_RESET This command provides a means to reset the LTM4681 from the serial bus. This forces the LTM4681 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled. This write-only command has no data bytes. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS PWM CONFIGURATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0x28 MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC3 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 FREQUENCY_SWITCH 0x33 Switching frequency of the controller . R/W Word N L11 kHz Y 250 0xF3E8 MFR_PWM_MODE The MFR_PWM_MODE command sets important PWM controls for each channel. The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode. BIT MEANING Use High Range of ILIMIT Low Current Range High Current Range

6 Enable Servo Mode

5 External temperature sense:

∆VBE measurement. Now reserved, ∆VBE only supported.

4 Page 0 Only: Use of TSNS 1a-Sensed Temperature Telemetry

0 - Temperature sensed via TSNS1a is used to temperature-correct the current-sense information digitized by Channel 1’s current sense input, ISNS1a+/ISNS1a–. 1 - Temperature sensed via TSNS0a is used to temperature-correct the current-sense information digitized by Channel 1’s current sense input, ISNS1a+/ISNS1a–. Telemetry obtained from the thermal sensor connected to TSNS1a can be external to the module, if desired.

3 Reserved

2 Reserved

The maximum output voltage is 2.75V The maximum output voltage is 3.6V Bit[0] Mode Discontinuous Forced Continuous Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit [6] The LTM4681 will not servo while the part is OFF , ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value). The LTM4681 computes temperature in °C from ∆V BE measured by the ADC at the TSNSn pin as T = (G •

Rev. AFor more information www.analog.com For both equations, G = MFR_TEMP_1_GAIN • 2–14, and O = MFR_TEMP_1_OFFSET Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous con - duction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this bit. This command has one data byte. MFR_PWM_COMP The MFR_PWM_COMP command sets the g m of the PWM channel error amplifiers and the value of the internal RITHn compensation resistors. This command affects the loop gain of the PWM output which may require modifications to the external compensation network. BIT MEANING BIT [7:5] Error Amplifier GM Adjust (mS) 000b 1.00 001b 1.68 010b 2.35 011b 3.02 100b 3.69 101b 4.36 110b 5.04 111b 5.76 BIT [4:0] RCOMP (kΩ) 00000b 0 00001b 0.25 00010b 0.5 00011b 0.75 00100b 1 00101b 1.25 00110b 1.5 00111b 1.75 01000b 2 01001b 2.5 01010b 3 01011b 3.5 01100b 4 01101b 4.5 01110b 5 01111b 5.5 PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS 10000b 6 10001b 7 10010b 8 10011b 9 10100b 11 10101b 13 10110b 15 10111b 17 11000b 20 11001b 24 11010b 28 11011b 32 11100b 38 11101b 46 11110b 54 11111b 62 This command has one data byte. MFR_PWM_CONFIG The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the channels must be commanded off. If either channel is in the RUN state and this command is written, the command will be NACK’d and a BUSY fault will be asserted. BIT MEANING [6:5] 00b 01b 10b 11b Input current sense gain. 2x gain. 0mV to 50mV range. 4x gain. 0mV to 25mV range. 8x gain. 0mV to 10mV range. Reserved

4 Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until V IN > VIN_ON. The SHARE_CLK pin will be pulled low when VIN < VIN_OFF. If this bit is 0, the SHARE_ CLK pin will not be pulled low when VIN < VIN_OFF except for the initial application of VIN. BIT [2:0] CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300

Rev. AFor more information www.analog.com FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTM4681. Supported Frequencies: VALUE [15:0] RESUL TING FREQUENCY (TYP) 0x0000 External Oscillator 0xF3E8 250kHz 0xFABC 350kHz 0xFB52 425kHz 0xFBE8 500kHz 0x023F 575kHz 0x028A 650kHz 0x02EE 750kHz 0x03E8 1000kHz The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency. This command has two data bytes and is formatted in Linear_5s_11s format. VOL TAGE Input Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5 0xD3E0 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 4.65 0xD12A VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 4.75 0xD130 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 4.5 0xD120 MFR_ICHIP_CAL_GAIN 0xF7 The resistance value of the V IN pin filter element in milliohms onboard R/W Word N L11 mΩ Y 1000 0x03E8 VIN_OV_FAULT_LIMIT The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under- voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN Voltage drops below the VIN_UV_WARN_LIMIT the device:

• Sets the INPUT Bit Is the STATUS_WORD
• Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command
• Notifies the Host by Asserting ALER T, unless Masked VIN_ON The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. VIN_OFF The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_ICHIP_CAL_GAIN The MFR_ICHIP_CAL_GAIN command is used to set the resistance value of the V IN pin filter element in milliohms. (See also READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used. This command has two data bytes and is formatted in Linear_5s_11s format. Output Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VOUT_MODE 0x20 Output voltage format and exponent (2–12). R Byte Y Reg 2–12 0x14 VOUT_MAX 0x24 Upper limit on the output voltage the unit can command regardless of any other commands. R/W Word Y L16 V Y 3.6 0xC399 VOUT_OV_FAULT_ LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1 0x119A VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075 0x1133 VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be greater than VOUT_COMMAND. R/W Word Y L16 V Y 1.05 0x10CD VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y L16 V Y 1.0 0x1000 VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be less than VOUT_COMMAND. R/W Word Y L16 V Y 0.95 0x0F33 VOUT_UV_WARN_ LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925 0x0ECD VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9 0x0E66 MFR_VOUT_MAX 0xA5 Maximum allowed output voltage. R Word Y L16 V 3.6 0xC399

Rev. AFor more information www.analog.com VOUT_MODE The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands. This read-only command has one data byte. VOUT_MAX The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com - mand regardless of any other commands or combinations. The maximum allowed value of this command is 3.6V. The maximum output voltage the LTM4681 can produce is 3.3V including VOUT_MARGIN_HIGH. However , the VOUT_OV_FAULT_LIMIT can be commanded as high as 3.6V. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara- tor at the sense pins, in volts, which causes an output overvoltage fault. If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modi - fied to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON . Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher . If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAUL T pin will not assert if VOUT_OV_FAULT is propagated. The LTM4681 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this limit has been exceeded. In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked This condition is detected by the ADC so the response time may be up to t CONVERT. This command has two data bytes and is formatted in Linear_16u format. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts, when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 3.6V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_COMMAND The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 3.6V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_ RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage low warning. In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com - parator at the sense pins, in volts, which causes an output undervoltage fault. This command has two data bytes and is formatted in Linear_16u format.

Rev. AFor more information www.analog.com MFR_VOUT_MAX The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX is 3.6V. If the output voltage is set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX is 2.75V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set. This read only command has 2 data bytes and is formatted in Linear_16u format. OUTPUT CURRENT AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_IOUT_CAL_GAIN 0xDA The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor , it is the resistance value in mΩ. R Word Y L11 mΩ Factory Only NVM 0.4 0xD01A MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF Y 3900 0x0F3C IOUT_OC_FAULT_LIMIT 0x 46 Output overcurrent fault limit. R/W Word Y L11 A Y 40.0 0xE940 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 35.0 0xE231 MFR_IOUT_CAL_GAIN The MFR_IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see also MFR_IOUT_CAL_GAIN_TC). This command has two data bytes and is formatted in Linear_5s_11s format. MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_ GAIN sense resistor or inductor DCR in ppm/°C. This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • 10–6. Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by: [1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)]. DCR sensing will have a typical value of 3900. The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including : READ_IOUT, MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS IOUT_OC_FAULT_LIMIT The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the control- ler is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the progammable peak output current limit value in mV between I SENSE+ and ISENSE–. The actual value of current limit is (ISENSE+ – ISENSE–)/IOUT_CAL_GAIN in Amperes. BASED ON PEAK-TO-PEAK INDUCTOR CURRENT = 50% OF 30A FOR WORSE CASE, THESE ARE APPROXIMATES, SO USE GUARDBAND AND CHECK MFR_PWM_MODE[7] = 1 High Current Range (mV) ~ILPeak (A) ~IOUT (A) MFR_PWM_MODE[7] = 0 Low Current Range (mV) ~ ILPeak (A) ~ IOUT (A) Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation: Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)). The LTM4681 automatically convert currents to the appropriate internal bit value. The IOUT range is set with bit 7 of the MFR_PWM_MODE command. The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. If the IOUT_OC_FAULT_LIMIT is exceeded, the device:

• Sets the IOUT bit in the STATUS word
• Sets the IOUT Overcurrent fault bit in the STATUS_IOUT
• Notifies the host by asserting ALERT, unless masked This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. AFor more information www.analog.com IOUT_OC_WARN_LIMIT This command sets the value of the output current measured by the ADC that causes an output overcurrent warning in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded. In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. This command has two data bytes and is formatted in Linear_5s_11s format Input Current and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_IIN_CAL_GAIN 0xE8 The resistance value of the input current sense element in mΩ. R/W Word L11 mΩ Y 1.000 0xE010 MFR_IIN_CAL_GAIN The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms. (see also READ_IIN). This command has two data bytes and is formatted in Linear_5s_11s format. COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IIN_OC_WARN_LIMIT 0x5D Input overcurrent warning limit. R/W Word N L11 A Y 10.0 0xD280 IIN_OC_WARN_LIMIT The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin This command has two data bytes and is formatted in Linear_5s_11s format. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS TEMPERATURE Power Stage DCR Temperature Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor . R/W Word Y CF Y 0.995 0x3FAE MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor . R/W Word Y L11 C Y 0.0 0x8000 MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command will modify the slope of the power stage sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in 16-bit 2’s complement integer . The effective gain adjustment is N • 2–14. The nominal value is 1. N = 8192 to 32767 MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calibration with a –273.15 so the default adjustment is zero. Power Stage Temperature Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE OT_FAULT_LIMIT 0x4F Power stage overtemperature fault limit. R/W Word Y L11 C Y 128.0 0xF200 OT_WARN_LIMIT 0x51 Power stage overtemperature warning limit. R/W Word Y L11 C Y 125.0 0xEBE8 UT_FAULT_LIMIT 0x53 Power stage undertemperature fault limit. R/W Word Y L11 C Y –45.0 0xE530 OT_FAULT_LIMIT The OT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. This command has two data bytes and is formatted in Linear_5s_11s format. OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.

Rev. AFor more information www.analog.com In response to the OT_WARN_LIMIT being exceeded, the device:

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_5s_11s format. UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response set to ignore to avoid ALERT being asserted. This command has two data bytes and is formatted in Linear_5s_11s format. TIMING Timing—On Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 3.0 0xC300 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y L11 ms Y 5.0 0xCA80 VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.001 0x8042 TON_DELAY The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of 270µs for TON_DELAY = 0 and an uncertainty of ±50µs for all values of TON_DELAY. This command has two data bytes and is formatted in Linear_5s_11s format. TON_RISE The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4681 digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the PWM switcher . The number of steps in TON_RISE is equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms. This command has two data bytes and is formatted in Linear_5s_11s format. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS TON_MAX_FAULT_LIMIT The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds. This command has two data bytes and is formatted in Linear_5s_11s format. VOUT_TRANSITION_RATE When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms. This command has two data bytes and is formatted in Linear_5s_11s format. Timing—Off Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y L11 ms Y 0.0 0x8000 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 3.0 0xC300 TOFF_MAX_WARN_LIMIT 0x 66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 0 0x8000 TOFF_DELAY The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of 270µs for TOFF_DELAY = 0 and an uncertainty of ±50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied when a fault event occurs This command has two data bytes and is formatted in Linear_5s_11s format. TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt- age is commanded to zero. It is the ramp time of the V OUT DAC. When the VOUT DAC is zero, the PWM output will be set to high impedance state. The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty of ±0.1ms. In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. AFor more information www.analog.com TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds 12.5% of the programmed voltage before a warning is asserted. The output is considered off when the V OUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid. This command has two data bytes and is formatted in Linear_5s_11s format. Precondition for Restart COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_RESTART_ DELAY 0xDC Minimum time the RUN pin is held low by the LTM4681. R/W Word Y L11 ms Y 150 0xF258 MFR_RESTART_DELAY This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms. Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_ FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value. This command has two data bytes and is formatted in Linear_5s_11s format. FAUL T RESPONSE Fault Responses All Faults COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_RETRY_ DELAY 0xDB Retry interval during FAUL T retry mode. R/W Word Y L11 ms Y 250 0xF3E8 MFR_RETRY_DELAY This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments. Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. This command has two data bytes and is formatted in Linear_5s_11s format. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS Fault Responses Input Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an input supply overvoltage fault is detected. R/W Byte Y Reg Y 0x80 VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over - voltage fault. The data byte is in the format given in Table 21. The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
• Sets the VIN Over voltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked This command has one data byte. Fault Responses Output Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 17. The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked The only values recognized for this command are: 0x00 Part performs OV pull down only , or OV_PULLDOWN. 0x80 The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).

another fault condition causes the unit to shut down. removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. Any other value will result in a CML fault and the write will be ignored. This command has one data byte. Table 17. VOUT_OV_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4681.

00 Part performs OV pull down only or OV_PULLDOWN

01 The PMBus device continues operation for the delay time

10 The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault.

111 The PMBus device attempts to restart continuously, without

retry interval is set by the MFR_RETRY_DELAY command. detected. Only valid for deglitched off state. undervoltage fault. The data byte is in the format given in Table 18.

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked PMBus COMMAND DETAILS

The UV fault and warn are masked whenever the channel is not active. The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing. This command has one data byte. Table 18. VOUT_UV_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled. 00 The PMBus device continues operation without interruption. (Ignores the fault functionally)

10 The device shuts down (disables the output) and responds

according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. detected. Only valid for deglitched off state.

Rev. AFor more information www.analog.com TON_MAX_FAULT_RESPONSE The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX fault. The data byte is in the format given in Table 21. The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0. Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded. This command has one data byte. Fault Responses Output Current COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00 IOUT_OC_FAULT_RESPONSE The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The data byte is in the format given in Table 19. The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked This command has one data byte. PMBus COMMAND DETAILS

Table 19. IOUT_OC_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.

00 The LTM4681 continues to operate indefinitely while

voltage (known as constant-current or brick-wall limiting).

10 The LTM4681 continues to operate, maintaining the output

regard to the output voltage, for the delay time set by bits [2:0].

11 The LTM4681 shuts down immediately and responds as

programmed by the Retry Setting in bits [5:3].

111 The device attempts to restart continuously, without limitation,

is set by the MFR_RETRY_DELAY command. down. Only valid for deglitched off response. internal overtemperature fault is detected. overtemperature fault. The data byte is in the format given in Table 20.

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

Table 20. Data Byte Contents MFR_OT_FAULT_RESPONSE

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4681. 00 Not supported. Writing this value will generate a CML fault. 01 Not supported. Writing this value will generate a CML fault

responds according to the retry setting in bits [5:3]. 11 The device’s output is disabled while the fault is present. disabled until the fault is cleared. 001-111 Not supported. Writing this value will generate CML fault. external undertemperature fault is detected. perature fault on the external temp sensors. The data byte is in the format given in Table 21.

• Sets the TEMPERA TURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked This command has one data byte. UT_FAULT_RESPONSE The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under - temperature fault on the external temp sensors. The data byte is in the format given in Table 15. The device also:
• Sets the TEMPERA TURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked PMBus COMMAND DETAILS

This condition is detected by the ADC so the response time may be up to tCONVERT. This command has one data byte. Table 21. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,

• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled. 00 The PMBus device continues operation without interruption. 01 Not supported. Writing this value will generate a CML fault.

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. are propagated to the FAUL T pins. This command has two data bytes.

Table 22. FAUL Tn Propagate Fault Configuration channels. Others are specific to an output channel. They can also be used to share faults between channels. OFF(MIN) after sequence off.

Rev. A For more information www.analog.com PMBus COMMAND DETAILS Fault Sharing Response COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAUL T pin is asserted low. R/W Byte Y Reg Y 0xC0 MFR_FAULT_RESPONSE The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAUL Tn pin being pulled low by an external source. Supported Values: VALUE MEANING 0xC0 FAULT_INHIBIT The LTM4681 will three-state the output in response to the FAUL T pin pulled low. 0x00 FAULT_IGNORE The LTM4681 continues operation without interruption. The device also: Sets the MFR Bit in the STATUS_WORD.

• Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAUL Tn Is Being Pulled Low
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte. SCRATCHPAD COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE USER_DATA_00 0xB0 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_01 0xB1 Manufacturer reserved for L TpowerPlay. R/W Word Y Reg Y NA USER_DATA_02 0xB2 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_03 0xB3 A NVM word available for the user . R/W Word Y Reg Y 0x0000 USER_DATA_04 0xB4 A NVM word available for the user . R/W Word N Reg Y 0x0000

Rev. AFor more information www.analog.com USER_DATA_00 through USER_DATA_04 These commands are non-volatile memor y locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However , the L TpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products. These commands have 2 data bytes and are in register format. IDENTIFICATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PMBus_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg FS 0x22 CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R Byte N Reg 0xB0 MFR_ID 0x99 The manufacturer ID of the LTM4681 in ASCII. R String N ASC LT C MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTM4681 MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTM4681. R Word N Reg 0x500X PMBus_REVISION The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4681 is PMBus Version 1.2 compliant in both Part I and Part II. This read-only command has one data byte. CAPABILITY This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTM4681 supports packet error checking, 400kHz bus speeds, and ALERT pin. This read-only command has one data byte. MFR_ID The MFR_ID command indicates the manufacturer ID of the LTM4681 using ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command indicates the manufacturer’s part number of the LTM4681 using ASCII characters. This read-only command is in block format. MFR_SPECIAL_ID The 16-bit word representing the part name and revision. 0x414 denotes the part is an LTM4681, X is adjustable by the manufacturer . This read-only command has two data bytes. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS FAUL T WARNING AND STATUS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N NA SMBALERT_MASK 0x1B Mask activity. Block R/W Y Reg Y See CMD Details MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte Y NA STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg NA STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA STATUS_ TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA STATUS_MFR_ SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA MFR_COMMON 0xEF Manufacturer status bits that are common across multiple ADI chips. R Byte N Reg NA CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set. This write-only command has no data bytes. The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when: The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERA TION command, to turn off and then to turn back on, or

• MFR_RESET command is issued.
• Bias power is removed and reapplied to the integrated circuit SMBALERT_MASK The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they are asserted. Figure 33 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in the mask byte align with bits in the specified status register . For example, if the STATUS_TEMPERATURE command code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning

bits would continue to assert ALERT if set. present state of any supported status register , again without PEC. SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTM4681. SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.

4681 F56

4681 F55

Figure 55. Example of Writing SMBALERT_MASK Figure 56. Example of Reading SMBALERT_MASK This write-only command has no data bytes. lower byte of the status word.

Rev. A For more information www.analog.com PMBus COMMAND DETAILS STATUS_BYTE Message Contents: BIT STATUS BIT NAME MEANING 7* BUSY A fault was declared because the LTM4681 was unable to respond. 6 OFF This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 VOUT_OV An output overvoltage fault has occurred. 4 IOUT_OC An output overcurrent fault has occurred. 3 VIN_UV Not supported (LTM4681 returns 0). 2 TEMPERATURE A temperature fault or warning has occurred. 1 CML A communications, memory or logic fault has occurred. 0* NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred. *ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_ FAULTS command. This command has one data byte. STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME MEANING 15 VOUT An output voltage fault or warning has occurred. 14 IOUT An output current fault or warning has occurred. 13 INPUT An input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the LTM4681 has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (LTM4681 returns 0). 9 OTHER Not supported (LTM4681 returns 0). 8 UNKNOWN Not supported (LTM4681 returns 0). If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted. This command has two data bytes. STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT MEANING 7 V OUT overvoltage fault. 6 V OUT overvoltage warning. 5 V OUT undervoltage warning. 4 V OUT undervoltage fault. 3 V OUT max warning. 2 TON max fault. 1 TOFF max fault. 0 Not supported (LTM4681 returns 0).

Rev. AFor more information www.analog.com The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_IOUT The STATUS_IOUT command returns one byte of IOUT status information. STATUS_IOUT Message Contents: BIT MEANING 7 I OUT overcurrent fault. 6 Not supported (LTM4681 returns 0). 5 I OUT overcurrent warning. 4:0 Not supported (LTM4681 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (VINSNS) status information. STATUS_INPUT Message Contents: BIT MEANING 7 V IN overvoltage fault. 6 Not supported (LTM4681 returns 0). 5 V IN undervoltage warning. 4 Not supported (LTM4681 returns 0).

3 Unit off for insufficient V

IN. 2 Not supported (LTM4681 returns 0). 1 I IN overcurrent warning. 0 Not supported (LTM4681 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not generate an ALERT even if it is set. This command has one data byte. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS STATUS_TEMPERATURE The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged command and is related to the respective READ_TEMPERATURE_1 value. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (LTM4681 returns 0). 4 External undertemperature fault. 3:0 Not supported (LTM4681 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. This command has one data byte. STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (LTM4681 returns 0). 1 Other communication fault. 0 Other memory or logic fault. If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued operation of the part is not recommended if these bits are continuously set. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

Rev. AFor more information www.analog.com STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. The format for this byte is: BIT MEANING 7 Internal Temperature Fault Limit Exceeded. 6 Internal Temperature Warn Limit Exceeded. 5 Factory T rim Area NVM CRC Fault.

4 PLL is Unlocked

3 Fault Log Present

1 ShortCycle Event Detected

0 FAUL T Pin Asserted Low by External Device

If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. However , the fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. MFR_PADS This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows: BIT ASSIGNED DIGITAL PIN

15 V DD33 OV Fault

14 V DD33 UV Fault

13 Reserved

12 Reserved

11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation

10 SYNC clocked by external device (when LTM4681 configured to drive SYNC pin)

9 Channel 1 Power Good

8 Channel 0 Power Good

7 LTM4681 Driving RUN1 Low

6 LTM4681 Driving RUN0 Low

5 RUN1 Pin State

4 RUN0 Pin State

3 LTM4681 Driving FAUL T1 Low

2 LTM4681 Driving FAUL T0 Low

1 FAUL T1 Pin State

0 FAUL T0 Pin State

A 1 indicates the condition is true. This read-only command has two data bytes. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS MFR_COMMON The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products. BIT MEANING

7 Module Not Driving ALERT Low

6 LTM4681 Not Busy

5 Calculations Not Pending

4 LTM4681 Outputs Not in T ransition

3 NVM Initialized

1 SHARE_CLK Timeout

0 WP Pin Status

This read-only command has one data byte. TELEMETRY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA READ_IIN 0x89 Measured input supply current. R Word N L11 A NA READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA READ_IOUT 0x8C Measured output current. R Word Y L11 A NA READ_TEMPERATURE_1 0x8D Power stage temperature sensor . This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA READ_TEMPERATURE_2 0x8E Internal junction temperature. Does not affect any other controller commands. R Word N L11 C NA READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word Y L11 Hz NA READ_POUT 0x96 Calculated output power . R Word Y L11 W NA READ_PIN 0x97 Calculated input power . R Word N L11 W NA MFR_PIN_ACCURACY 0xAC Returns the accuracy of the READ_PIN command R Byte N % 5.0% MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_IOUT since last MFR_CLEAR_PEAKS. R Word Y L11 A NA MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA MFR_READ_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS. R Word N L11 A NA MFR_READ_ICHIP 0xE4 Measured current used by the LTM4681. R Word N L11 A NA MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last MFR_CLEAR_PEAKS. R Word N L11 C NA MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back. R/W Byte N N Reg NA

Rev. AFor more information www.analog.com READ_VIN The READ_VIN command returns the measured V IN pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This compensates for the IR voltage drop across the VIN filter element due to the supply current of the LTM4681. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the measured output voltage by the VOUT_MODE command. This read-only command has two data bytes and is formatted in Linear_16u format. READ_IIN The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor (see also MFR_IIN_CAL_GAIN). This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_IOUT The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of: a) the differential voltage measured across the I SENSE pins b) the IOUT_CAL_GAIN value c) the MFR_IOUT_CAL_GAIN_TC value, and d) READ_TEMPERATURE_1 value e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the power stage sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the LTM4681’s die temperature, in degrees Celsius, of the internal sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_FREQUENCY The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. READ_POUT The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on the most recent correlated output voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS READ_PIN The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the most recent input voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. MFR_PIN_ACCURACY The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command. This read-only command has one data byte and is formatted as an unsigned integer . MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_16u format. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_IIN_PEAK The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. AFor more information www.analog.com MFR_READ_ICHIP The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTM4681. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_ADC_CONTROL The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t CONVERT. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled. COMMANDED VALUE TELEMETRY COMMAND NAME DESCRIPTION 0x0F Reserved 0x0E Reserved 0x0D Reserved 0x0C READ_TEMPERATURE_1 Channel 1 external temperature 0x0B Reserved 0x0A READ_IOUT Channel 1 measured output current 0x09 READ_VOUT Channel 1 measured output voltage 0x08 READ_TEMPERATURE_1 Channel 0 external temperature 0x07 Reserved 0x06 READ_IOUT Channel 0 measured output current 0x05 READ_VOUT Channel 0 measured output voltage 0x04 READ_TEMPERATURE_2 Internal junction temperature 0x03 READ_IIN Measured input supply current 0x02 MFR_READ_ICHIP Measured supply current of the LTM4681 0x01 READ_VIN Measured input supply voltage 0x00 Standard ADC Round Robin Telemetry If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML faults will continue to be issued by the LTM4681 until a valid command value is entered. The accuracy of the measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry. This write-only command has 1 data byte and is formatted in register format. PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS NVM MEMORY COMMANDS Store/Restore COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N NA RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Send Byte N NA MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with NVM. Send Byte N NA STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User NVM memory. Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten- tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C. Communication with the LTM4681 and programming of the NVM can be initiated when EXTVCC or VDD33 is available and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by 0xC4. The LTM4681 will now communicate normally, and the project file can be updated. To write the updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read. This write-only command has no data bytes. RESTORE_USER_ALL The RESTORE_USER_ALL command instructs the LTM4681 to copy the contents of the non-volatile User memory to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value retrieved from the User commands. The LTM4681 ensures both channels are off, loads the operating memory from the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels if applicable. STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C. This write-only command has no data bytes. MFR_COMPARE_USER_ALL The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated. This write-only command has no data bytes.

Rev. AFor more information www.analog.com Fault Logging COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_FAULT_LOG 0xEE Fault log data bytes. R Block N CF Y NA MFR_FAULT_LOG_ STORE 0xEA Command a transfer of the fault log from RAM to EEPROM. Send Byte N NA MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault logging. Send Byte N NA MFR_FAULT_LOG The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur - rence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed in Table 15. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147 bytes long. If a fault occurs within the first second of applying power , some of the earlier pages in the fault log may not contain valid data. NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock. This read-only command is in block format. MFR_FAULT_LOG_STORE The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in the MFR_CONFIG_ALL command. If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature drops below 125°C. This write-only command has no data bytes. PMBus COMMAND DETAILS

Table 23. Fault Logging This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command. Fault Log Preface [7:0] ASC 0 Returns L Txx beginning at byte 0 if a partial or complete fault log exists. Fault Source [7:0] Reg 4 Refer to Table 19. MFR_REAL_TIME [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution). MFR_VIN_PEAK [15:8] L11 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command. READ_TEMPERATURE1 (PAGE 0) [15:8] L11 21 Power stage temperature sensor 0 during last event. READ_TEMPERATURE1 (PAGE 1) [15:8] L11 23 Power stage temperature sensor 1 during last event. READ_TEMPERATURE2 [15:8] L11 25 LTM4681 die temperature sensor during last event.

Rev. AFor more information www.analog.com CYCLICAL DATA EVENT n (Data at Which Fault Occurred; Most Recent Data) Event “n” represents one complete cycle of ADC reads through the MUX at time of fault. Example: If the fault occurs when the ADC is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to EEPROM READ_VOUT (PAGE 0) [15:8] LIN 16 27 [7:0] LIN 16 28 READ_VOUT (PAGE 1) [15:8] LIN 16 29 [7:0] LIN 16 30 READ_IOUT (PAGE 0) [15:8] LIN 11 31 [7:0] LIN 11 32 READ_IOUT (PAGE 1) [15:8] LIN 11 33 [7:0] LIN 11 34 READ_VIN [15:8] LIN 11 35 [7:0] LIN 11 36 READ_IIN [15:8] LIN 11 37 [7:0] LIN 11 38 STATUS_VOUT (PAGE 0) BYTE 39 STATUS_VOUT (PAGE 1) BYTE 40 STATUS_WORD (PAGE 0) [15:8] WORD 41 [7:0] WORD 42 STATUS_WORD (PAGE 1) [15:8] WORD 43 [7:0] WORD 44 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 45 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 46 PMBus COMMAND DETAILS

Rev. A For more information www.analog.com PMBus COMMAND DETAILS EVENT n-1 (data measured before fault was detected) READ_VOUT (P AGE 0) [15:8] LIN 16 47 [7:0] LIN 16 48 READ_VOUT (PAGE 1) [15:8] LIN 16 49 [7:0] LIN 16 50 READ_IOUT (PAGE 0) [15:8] LIN 11 51 [7:0] LIN 11 52 READ_IOUT (PAGE 1) [15:8] LIN 11 53 [7:0] LIN 11 54 READ_VIN [15:8] LIN 11 55 [7:0] LIN 11 56 READ_IIN [15:8] LIN 11 57 [7:0] LIN 11 58 STATUS_VOUT (PAGE 0) BYTE 59 STATUS_VOUT (PAGE 1) BYTE 60 STATUS_WORD (PAGE 0) [15:8] WORD 61 [7:0] WORD 62 STATUS_WORD (PAGE 1) [15:8] WORD 63 [7:0] WORD 64 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 65 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 66 EVENT n-5 (Oldest Recorded Data) READ_VOUT (PAGE 0) [15:8] LIN 16 127 [7:0] LIN 16 128 READ_VOUT (PAGE 1) [15:8] LIN 16 129 [7:0] LIN 16 130 READ_IOUT (PAGE 0) [15:8] LIN 11 131 [7:0] LIN 11 132 READ_IOUT (PAGE 1) [15:8] LIN 11 133 [7:0] LIN 11 134 READ_VIN [15:8] LIN 11 135 [7:0] LIN 11 136 READ_IIN [15:8] LIN 11 137 [7:0] LIN 11 138 STATUS_VOUT (PAGE 0) BYTE 139 STATUS_VOUT (PAGE 1) BYTE 140 STATUS_WORD (PAGE 0) [15:8] WORD 141 [7:0] WORD 142 STATUS_WORD (PAGE 1) [15:8] WORD 143 [7:0] WORD 144 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 145 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 146

Table 24. Explanation of Position_Fault Values Contact the factory for details. Contact the factory for details. STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear . This write-only command is send bytes. die temperature drops below 125°C.

Table 25. LTM4681 BGA Pinout

Rev. AFor more information www.analog.com PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION N1 GND P1 SW2 R1 SW2 T1 SW2 U1 GND V1 SW3 N2 GND P2 SW2 R2 SW2 T2 SW2 U2 GND V2 SW3 N3 GND P3 GND R3 GND T3 GND U3 GND V3 GND N4 GND P4 GND R4 GND T4 GND U4 GND V4 GND N5 V IN23 P5 V IN23 R5 V IN23 T5 V IN23 U5 V IN23 V5 V IN23 N6 V IN23 P6 V IN23 R6 V IN23 T6 V IN23 U6 V IN23 V6 V IN23 N7 GND P7 GND R7 GND T7 GND U7 GND V7 GND N8 GND P8 V OSNS2+ R8 V OSNS2– T8 COMP2a U8 TSNS2 V8 SDA_23 N9 V IN_VBIAS P9 I IN_23– R9 I IN_23+ T9 COMP2b U9 TSNS3 V9 SYNC_23 N10 V BIAS P10 INTV CC_23 R10 PGOOD2 T10 PGOOD3 U10 SGND23 V10 FAUL T2 N11 RUNP P11 SV IN_23 R11 V OSNS3+ T11 V OSNS3– U11 SGND23 V11 COMP3a N12 GND P12 GND R12 GND T12 GND U12 GND V12 GND N13 V OUT2 P13 V OUT2 R13 V OUT2 T13 V OUT2 U13 V OUT2 V13 V OUT3 N14 V OUT2 P14 V OUT2 R14 V OUT2 T14 V OUT2 U14 V OUT2 V14 V OUT3 N15 V OUT2 P15 V OUT2 R15 V OUT2 T15 V OUT2 U15 V OUT2 V15 V OUT3 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION W1 SW3 Y1 SW3 AA1 GND AB1 GND W2 SW3 Y2 SW3 AA2 GND AB2 GND W3 GND Y3 GND AA3 GND AB3 GND W4 GND Y4 GND AA4 GND AB4 GND W5 V IN23 Y5 V IN23 AA5 V IN23 AB5 V IN23 W6 V IN23 Y6 V IN23 AA6 V IN23 AB6 V IN23 W7 GND Y7 GND AA7 GND AB7 GND W8 ALERT_23 Y8 RUN3 AA8 VOUT2_CFG AB8 VOUT3_CFG W9 SCL_23 Y9 RUN2 AA9 FSWPH_23_CFG AB9 VTRIM3_CFG W10 FAUL T3 Y10 V DD33_23 AA10 ASEL_23 AB10 VTRIM2_CFG W11 COMP3b Y11 WP_23 AA11 SHARE_CLK_23 AB11 V DD25_23 W12 GND Y12 GND AA12 GND AB12 GND W13 V OUT3 Y13 V OUT3 AA13 V OUT3 AB13 V OUT3 W14 V OUT3 Y14 V OUT3 AA14 V OUT3 AB14 V OUT3 W15 V OUT3 Y15 V OUT3 AA15 V OUT3 AB15 V OUT3 PACKAGE DESCRIPTION

Rev. A For more information www.analog.com PACKAGE DESCRIPTION A DETAIL B PACKAGE SIDE VIEW 330-Lead (22mm × 15mm × 8.17mm) (Reference LTC DWG # 05-08-1654 Rev Ø) DETAIL B SYMBOL A b D E e F G aaa bbb ccc ddd eee fff MIN 7.77 0.40 1.72 0.50 0.47 0.27 1.45 5.65 NOM 8.17 0.50 1.82 0.60 0.50 15.00 22.00 1.00 21.00 14.00 0.32 1.50 5.85 MAX 8.57 0.60 1.92 0.70 0.53 0.37 1.55 6.05 0.15 0.10 0.20 0.25 0.10 0.35 TOTAL NUMBER OF BALLS: 330 PACKAGE BOTTOM VIEW SEE NOTES b e e b F G BGA 330 0618 REV Ø DETAIL A PIN 1 SUGGESTED PCB LAYOUT TOP VIEW 0.00 0.00 0.500 ±0.025 Ø 330x 1.50 4.50 3.50 2.50 5.50 0.50 0.50 6.50 2.50 7.50 4.50 10.50 9.50 8.50 7.00 6.00 5.00 4.00 5.00 3.00 4.00 2.00 3.00 1.00 2.00 1.00 6.00 7.00 10.50 8.50 6.50 1.50 3.50 5.50 9.50 7.50 DETAIL A Øb (330 PLACES) M X Y Z ddd M Z eee NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SEE NOTES PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z D E 21.40 5. PRIMARY DATUM -Z- IS SEATING PLANE

6 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT INDUCTOR HT 11 10 9 8 7 6 5 4 3 215 12 13 14 1 A B C D E F G H K J L T R P N M U AB AA Y W V Z SUBSTRATE INDUCTOR ccc Z // bbb Z // fff Z MOLD CAP Z 14.30 TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXX µModule

Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. REV DATE DESCRIPTION PAGE NUMBER A 04/22 Corrected V VSNS – VSNG to VVOSNSn+ – VVOSNSn– in the Electrical Characteristics table. Fixed errors: changed onboard to offboard. Added Note 15 in the Electrical Characteristics table. Corrected Quad Channel Single Output Efficiency curve Y axis. Corrected SV IN pin description. Changed note Figure 1 to Figure 2 in the Decoupling Requirements section. Changed 1ms to 10μs in the Responses to V OUT and IIN/IOUT Faults section. Added (SVIN_XX) to VIN_ON and VIN_OFF. Fixed schematic error . Fixed typo. Added ink marking statement to package photos. 134

REVISION HISTORY

Rev. A For more information www.analog.com  ANALOG DEVICES, INC. 2021-2022 www.analog.com DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
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• Free Simulation Tools Manufacturing:
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• Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4675 Dual 9A or Single 18A Step-Down μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 17V, 0.5V ≤ VOUT ≤ 5.5V, 11.9mm × 16mm × 3.51mm BGA LTM4686/ LTM4686-1 Ultrathin Dual 10A or Single 20A μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 17V, 0.5V ≤ VOUT ≤ 3.6V (LTM4686), 2.375V ≤ VIN ≤ 17V (LTM4686-1) 11.9mm × 16mm × 1.82mm LGA LTM4676A Dual 13A or Single 26A Step-Down μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 26.5V, 0.5V ≤ VOUT ≤ 5.5V, 16mm × 16mm × 5.01mm BGA LTM4677 Dual 18A or Single 36A Step-Down μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm BGA LTM4678 Dual 25A or Single 50A μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 16V, 0.5V ≤ VOUT ≤ 3.4V, 16mm × 16mm × 5.86mm BGA LTM4664 54 VIN, Dual 25A or Single 50A μModule Regulator with Digital Power System Management 30V ≤ V IN ≤ 58V, 0.5V ≤ VOUT ≤ 1.5V, 16mm × 16mm × 7.72mm BGA LTM4680 Dual 30A or Single 60A μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 16V, 0.5V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.82mm BGA LTM4700 Dual 50A or Single 100A μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V, 15mm × 22mm × 7.87mm BGA PACKAGE PHOTOS Part marking is either ink mark or laser mark