SLG88103

SLG88103 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 22

Technical content

Features

• Low Quiescent Current: 375 nA per Amplifier (typ)
• Low Offset Voltage: ±200 µV (typ)
• Zero-Crossover
• Low Offset Drift: 1 µV/˚C (typ)
• DC Precision:
• PSRR: 115 dB
• CMRR: 100 dB
• A OL : 120 dB
• Gain-Bandwidth Product: 10 kHz (typ)
• Rail to Rail Input/Output
• Supply Voltage: 1.71 V to 5.5 V
• Tiny Package:
• 10-pin 2 x 2 mm STDFN
• 20-pin 2 x 3.5 mm STQFN
• Industrial Temperature Range: -40 ˚C to 85 ˚C Typical Applications
• Battery-Powered Devices
• Portable Devices
• Wearable Products
• Gas Sensors
• Pressure Sensors
• Medical Monitors
• Smoke Detectors
• Active RFID Reader
• Energy Harvester Pin Configurations IN+2 IN-2 OUT2 IN+1 IN-1 4 7 OUT1 PD1 1 10-pin STDFN (Top View) PD2 6 VDD VSS 5 PD4 IN+4 IN-4 VSS IN+1 4 15 IN-1 OUT1 1 20-pin STQFN (Top View) VDD 14 OUT4 PD2 5 7 12 9 10 20 19 IN-2 OUT2 IN+2 IN-3 OUT3 IN+3 VDD PD1 PD3 VSS SLG88103 SLG88104 SLG88103/4

000-0088103/4-103 Page 2 of 21 SLG88103/4 Pin Description

Ordering Information

Pin # Pin Name Type Pin Description 20L STQFN 10L STDFN 1 2 OUT1 O Analog Output (Op Amp 1) 2 3 IN-1 I Inverting Input (Op Amp 1) 3 4 IN+1 I Non-inverting Input (Op Amp 1) 4 5 VSS GND Negative Power Supply 5 6 PD2 I Power Down Input (Op Amp 2) When PD pin is high, the respective amplifier is powered down. 6 9 OUT2 O Analog Output (Op Amp 2) 7 8 IN-2 I Inverting Input (Op Amp 2) 8 7 IN+2 I Non-inverting Input (Op Amp 2) 9 -- VSS GND Negative Power Supply 10 -- PD3 I Power Down Input (Op Amp 3) When PD pin is high, the respective amplifier is powered down. 11 -- IN+3 I Non-inverting Input (Op Amp 3) 12 -- IN-3 I Inverting Input (Op Amp 3) 13 -- OUT3 O Analog Output (Op Amp 3) 14 10 VDD PWR Power Supply 15 -- PD4 I Power Down Input (Op Amp 4) When PD pin is high, the respective amplifier is powered down. 16 -- IN+4 I Non-inverting Input (Op Amp 4) 17 -- IN-4 I Inverting Input (Op Amp 4) 18 -- OUT4 O Analog Output (Op Amp 4) 19 -- VDD PWR Power Supply 20 1 PD1 I Power Down Input (Op Amp 1) When PD pin is high, the respective amplifier is powered down. Part Number Type Production Flow SLG88103V 10-pin STDFN Industrial, -40 °C to 85 °C SLG88103VTR 10-pin STDFN (Tape and Reel) Industrial, -40 °C to 85 °C SLG88104V 20-pin STQFN Industrial, -40 °C to 85 °C SLG88104VTR 20-pin STQFN (Tape and Reel) Industrial, -40 °C to 85 °C

000-0088103/4-103 Page 3 of 21 SLG88103/4 Absolute Maximum Ratings Parameter Description Min. Typ. Max. Unit VDD Voltage on VDD pin relative to GND -0.3 -- 6.0 V TA Operating Range -40 -- 85 ˚C θJA Thermal Resistance -- 80 -- ˚C/W TS Storage Temperature -65 -- 150 ˚C TJ Junction Temperature -- -- 150 ˚C ESD HBM ESD Protection (Human Body Model) 2000 -- -- V ESD CDM ESD Protection (Charged Device Model) 500 -- -- V MSL Moisture Sensitivity Level 1 Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at thes e or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Electrical Characteristics

TA = 25 °C, V DD = 1.71 V to 5.5 V, V SS = GND, V CM = V DD /2, V OUT = V DD /2, V L = V DD /2, R L = 1 MΩ to V L, unless otherwise stated. Symbol Description Conditions Min Typ Max Unit Input Offset VOS Input Offset Voltage VCM = V DD /2 -1000 ±200 1000 µV VCM = V DD /2; TA = -40 ˚C to 85 ˚C -1100 ±250 1100 µV VCM = V SS ; TA = -40 ˚C to 85 ˚C -2400 ±350 2400 µV dV OS /dT Offset Drift with Temperature VCM = V DD /2; TA = -40 ˚C to 85 ˚C -4 ±1 4 µV/˚C VCM = V SS ; TA = -40 ˚C to 85 ˚C -10 ±2 10 µV/˚C dV OS /Time 10 Year Offset Drift TA = 85˚C; V DD = 3.3 V -30 -- +30 µV TA = 85˚C; V DD = 5.0 V -40 -- +40 µV PSRR Power Supply Rejection Ratio VCM = V DD /2 TA = -40 ˚C to 85 ˚C 95 115 -- dB VCM = V SS TA = -40 ˚C to 85 ˚C 85 100 -- dB CS Channel Separation VDD = 5 V, f = 10 Hz -- 120 -- dB VDD = 5 V, f = 1 kHz -- 95 -- dB Input Voltage Range VCMR Input Common-Mode Voltage Range TA = -40 ˚C to 85 ˚C V SS -- V DD V CMRR Common-Mode Rejection Ratio VSS + 0.8 V < V CM < VDD - 0.8 V, TA = -40 ˚C to 85 ˚C 65 100 -- dB VSS < V CM < V SS + 0.8 V, VDD - 0.8 V < V CM < V DD , TA = -40 ˚C to 85 ˚C 50 75 -- dB Input Bias Current and Impedance IB Input Bias Current 1 -- 2 -- pA TA = 85 ˚C -- 320 500 pA

000-0088103/4-103 Page 4 of 21 SLG88103/4 IOS Input Offset Current 2 -- ±0.3 -- pA RCM Common Mode Input Resistance -- 10 13 -- Ω RDIFF Differential Input Resistance -- 10 13 -- Ω CCM Input Capacitance Common-Mode -- 4.3 -- pF CDIFF Input Capacitance Differential -- 6 -- pF Open-Loop Gain AOL DC Open Loop Voltage Gain RL = 1 MΩ; VSS + 0.1 V ≤ V OUT ≤ V DD - 0.1 V 100 120 -- dB RL = 50 kΩ; VSS + 0.5 V ≤ V OUT ≤ V DD - 0.5 V 100 120 -- dB RL = 50 kΩ; T A = 85 ˚C; VSS + 0.1 V ≤ V OUT ≤ V DD - 0.1 V 80 100 -- dB Output VOH , V OL Maximum Voltage Swing R L= 50 kΩ V SS + 5 -- V DD - 5 mV VOSR Linear Output Swing Range V OVR from Rail V SS + 100 -- V DD - 100 mV ISC Short-circuit Current VDD = 1.71 V 3.8 4.5 -- mA VDD = 3.0 V to 5.5 V 8.5 10 -- mA CLOAD Capacitive Load Drive See Typical Performance Charts Power Supply VDD Supply Voltage Guaranteed by PSRR Test 1.71 -- 5.5 V IQ Quiescent Current (Per Amplifier) -- 0.38 0.55 µA TA = -40 ˚C to 85 ˚C -- 0.4 0.8 µA PDx = V DD -- 1 -- nA Frequency Response GBW Gain Bandwidth Product G = +1 V/V -- 10 -- kHz PM Phase Margin G = +1 V/V -- 54 -- ˚ SR Slew Rate R L= 50 kΩ 2.4 5.0 -- V/ms tOR Overload Recovery Time T A = -40 ˚C to 85 ˚C; R L= 50 kΩ -- 350 -- µs Noise en Input Voltage Noise f = 0.1 to 10 Hz -- 6.5 -- µVP-P Vn Input Voltage Noise Density f =1 kHz -- 195 -- nV/√Hz In Input Current Noise Density f =1 kHz -- < 10 -- fA/√Hz Note: 1. Part is measured to be less than 1 µA during production test. 2. Guaranteed by design, not tested in production. Electrical Characteristics (continued) TA = 25 °C, V DD = 1.71 V to 5.5 V, V SS = GND, V CM = V DD /2, V OUT = V DD /2, V L = V DD /2, R L = 1 MΩ to V L, unless otherwise stated. Symbol Description Conditions Min Typ Max Unit

000-0088103/4-103 Page 5 of 21 SLG88103/4 Typical Performance Charts TA = 25 °C, V DD = 5.0 V, V SS = GND, V CM = V DD /2, V OUT = V DD /2, V L = V DD /2, R L = 1 MΩ to V L , C L = 80 pF, unless otherwise stated. Fig 1. Input Offset Voltage Drift Distribution VCM = V SS ; V DD = 1.71 V and 5.5 V; T A = 25˚C. Fig 2. Input Offset Voltage vs. Common Mode Input Voltage VDD = 5.5 V. Fig 3. Quiescent Current vs. Power Supply Voltage 10% 12% 14% 16% 18% -800 -700 -600 -500 -400 -300 -200 -100 100 200 300 400 500 600 700 800 Percentage of Occurrences Input Offset Voltage ( ȝV)

164 Samples

V DD = 1.71 and 5.5V VCM = V SS 100 150 200 250 300 0 1 2 3 4 5 6 Input Ofset voltage ( ȝV) Common Mode Input Voltage (V) TA = +85°C TA = +25°C TA = -40°C 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Quiescent Current ( ȝA/Amplifier) Power Supply Voltage (V) TA = +85°C TA = +25°C TA = -40°C Fig 4. Input Offset Voltage Temperature Drift Distribution VCM = V SS ; V DD = 3.3 V; T A = -40˚C to 85˚C. Fig 5. Input Offset Voltage vs. Common Mode Input Voltage VDD = 1.71 V. Fig 6. DC Open Loop Gain vs. Common Mode Input Voltage VDD = 3.3 V. 10% 12% 14% 16% 18% 20% 22% 24% -3 -2 -1 0 1 2 3 4 5 6 7 Percentage of Occurrences Input Offset Voltage Temperature Drift ( ȝV/°C)

124 Samples

T VDD = 3.3V ; V CM = V SS 100 150 200 250 300 0.0 0.5 1.0 1.5 Input offset voltage ( ȝV) Common mode input voltage (V) TA = +85°C TA = +25°C TA = -40°C 100 110 120 130 DC Open Loop Gain (dB) Common mode input voltage (V) TA = +85°C TA = +25°C TA = -40°C

000-0088103/4-103 Page 6 of 21 SLG88103/4 TA = 25 °C, V DD = 5.0 V, V SS = GND, V CM = V DD /2, V OUT = V DD /2, V L = V DD /2, R L = 1 MΩ to V L , C L = 80 pF, unless otherwise stated. Fig 7. Open Loop Gain and Phase vs. Frequency VDD = 3.3 V. Fig 8. CMRR, PSRR vs. Frequency VDD = 3.3 V. Fig 9. Channel Separation vs. Frequency -10 100 1000 10000 Gain (dB) Frequency (Hz) Phase (°) GAIN PHASE 100 10 100 1,000 10,000 CMRR, PSRR (dB) Frequency (Hz) PSRR+ PSRR- CMRR 100 120 140 10 100 1000 10000 100000 1000000 Channel Separation (dB) Frequency (Hz) Fig 10. Input Noise Voltage Density vs. Frequency Fig 11. 0.1 Hz to 10 Hz Noise Fig 12. Output Short Circuit Current vs. V DD 200 400 600 800 1000 1200 0 1 10 100 1,000 Input Voltage Noise Density (nV/ ¥Hz) Frequency (Hz) 1ȝV/div Time (1s/div) Output Short Circuit Current (mA) Power supply voltage (V) Sink Source

000-0088103/4-103 Page 7 of 21 SLG88103/4 TA = 25 °C, V DD = 5.0 V, V SS = GND, V CM = V DD /2, V OUT = V DD /2, V L = V DD /2, R L = 1 MΩ to V L , C L = 80 pF, unless otherwise stated. Fig 13. Input Bias, Offset Currents vs. T A VDD = 3.3 V. Fig 14. Input Bias, Offset Currents vs. V CM VDD = 5.5 V. Fig 15. Input Current vs. V CM (below V SS ) VDD = 5.5 V. 0.01 0.1 100 1000 -40 -20 0 20 40 60 80 100 Input Bias and Offset Currents (pA) Ambient Temperature (°C) |Ios| Ib 0.01 0.1 100 1000 Input Bias and Offset Currents (pA) Input Common Mode Voltage (V) Ib |Ios| TA = +85°C TA = +25°C VDD = 5.5 V 100 200 300 400 500 600 700 Input Current (pA) Input Common Mode Voltage (V) TA = -40°C TA = +85°C TA = +55°C TA = +25°C Fig 16. Gain Bandwidth Product vs. Power Supply Voltage Fig 17. Gain Bandwidth Product vs. Ambient Temperature Fig 18. Slew Rate vs. Ambient Temperature G = 1 V/V; R L = 50 kΩ Gain Bandwidth Product (kHz) Power supply voltage (V) TA = +85°C TA = +25°C TA = -40°C -40 -20 0 20 40 60 80 100 Gain Bandwidth Product (kHz) Ambient temperature (°C) VDD = 1.71V Vdd=5.5V -40 -20 0 20 40 60 80 100 Slew Rate (V/ms) Ambient temperature (°C) High-to-Low Low-to-High

000-0088103/4-103 Page 8 of 21 SLG88103/4 TA = 25 °C, V DD = 5.0 V, V SS = GND, V CM = V DD /2, V OUT = V DD /2, V L = V DD /2, R L = 1 MΩ to V L , C L = 80 pF, unless otherwise stated. Fig 19. Small Signal Inverting Step Response G = -1 V/V; R L = 50 kΩ; C L = 60 pF. Fig 20. Large Signal Inverting Step Response G = -1 V/V; R L = 50 kΩ; C L = 80 pF. Fig 21. Inverting Overload Recovery G = -1 V/V; R L = 50 kΩ; C L = 60 pF. 10mV/div Time (250 ȝs/div) 500mV/div Time (1ms/div) 1V/div Time (1ms/div) Fig 22. Small Signal Non-inverting Step Response G = 1 V/V; R L = 50 kΩ; C L = 60 pF. Fig 23. Large Signal Non-inverting Step Response G = 1 V/V; R L = 50 kΩ; C L = 60 pF. Fig 24. Non-Inverting Overload Recovery G = 1 V/V; R L = 50 kΩ; C L = 60 pF. 10mV/div Time (250 ȝs/div) 500mV/div Time (1ms/div) 1V/div Time (1ms/div)

000-0088103/4-103 Page 9 of 21 SLG88103/4 TA = 25 °C, V DD = 5.0 V, V SS = GND, V CM = V DD /2, V OUT = V DD /2, V L = V DD /2, R L = 1 MΩ to V L , C L = 80 pF, unless otherwise stated. Fig 25. Small Signal Non-inverting Step Response G = 1 V/V; R L = 50 kΩ; C L = 10 nF. Fig 26. Small Signal Overshoot vs. Capacitive Load VDD = 3.3 V; V IN = 40 and 100 mV p-p; G = 1 V/V. Fig 27. Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V. 10mV/div Time (250 ȝs/div) 100 1,000 10,000 Overshoot (%) Capacitive load (pF) Overshoot Undershoot VIN = 40 mV p-p VIN = 100 mV p-p VIN = 100 mV p-p 100 200 300 400 500 600 Overload Recovery Time ( ȝs) Power Supply Voltage (V) High-to-Low Low-to-High Fig 28. DC Open Loop Gain vs. Power Supply Voltage RL = 50 kΩ Fig 29. Output Voltage Swing from Rail vs. I OUT VDD = 1.71 V and 5.5 V. Fig 30. Output Response to Power Down Signal G = 1 V/V; R L = 50 kΩ; C L = 20 pF; V IN = V S/2. 100 110 120 130 140 150 DC Open Loop Gain (dB) Power supply voltage (V) TA = +25°C TA = +85°C 100 1,000 0.1 1 10 Output Voltage Swing from Rail (mV) Output Load Current (mA) VDD = 1.71V — VDD - V OH - - VOL - V SS VDD = 5.5V 0 5 10 15 20 25 30 35 40 Voltage(V) Time ( ȝs) — VPDx — VOUT

000-0088103/4-103 Page 10 of 21 SLG88103/4 Applications Information The SLG88103/4 operates on a 1.71 V to 5.5 V power supply over a wide industrial temperature range from -40 °C to 85 °C. This dual/quad op amp chip has two/four active low enabl e pins used to individually power-up / power-down e ach op amp. Its com - mon-mode range extends from 0 to V DD and its output swings from rail-to-rail. Input Protection Voltage spikes need to be controlled at the inputs of each operational amplifier in order to avoid damaging the device. Electrical events like electrostatic discharge can produce large voltages at these nodes. The SLG88103/4 has inte rnal circuitry to protect the device from these events. If V IN exceeds V DD or drops below V SS , additional currents will flow through the inter nal ESD diodes and can damage the device even if the supplies are turned off. In this case we recommend placing a resistor in ser ies to the input to limit current through the inter nal ESD diodes to 5 mA (or preferably less). Driving Capacitive Loads Capacitive loads degrade circuit stability by decreasing the phase margin and bandwidth of the operational amplifier circuit. The SLG88103/4 can drive capacitive loads up to 10 nF at low loads. The amplifier’s output impedance and the capacitive load add phase lag to the system. This phase lag creates gai n peaking in the frequency response and peaking/rin ging in the output’s transient response. When large capacitive loads nee d to be driven, isolation resistors need to be used to increase the phase margin. This is done by increasing the output load impedance at higher frequencies. After selecting an isolation resistor value, verify that the frequency peaking and transient overshoot and ringing have been reduced. Fig 31. ESD Protection . Fig 32. Capacitive Load Test Circuit.

000-0088103/4-103 Page 11 of 21 SLG88103/4 Low Power Considerations The SLG88103/4 features low quiescent current at 375 nA per amplifier, as well as extremely high-impedance CMOS inputs. To take most advantage of such low power features, high impedance external components should be used. We recommend using low-leakage capacitors (such as ceramic). Other typ es of capacitors (such as aluminum dielectric) can leak at uA levels and consume more quiescent power than the op-amp itself! High value resistors are needed to keep power consumption low, as well as to avoid gain loss and non-linearities due to lo ading effects on the ultra-low power-stage of the o p amp. On the other hand, higher resistances increase thermal noise and sensitivity to external interference. We recommend impedances between 100 kΩ and 500 kΩ in gain/feedback networks to achieve balanced performance given the ultra-low power characteristics of SLG88103/4. PCB Layout For proper PCB layout, place a 100 nF decoupling capacitor close to the VDD pin of the SLG88103/4. To improve sensitive system performance, keep trace lengths similar on the positive and negative inputs of the op amp. Keep feedback resistors as close to the op amp and as short as possible. In addition, remove the PCB ground plane from under the inputs and outputs of the op amp. For low current applications, board leakage currents on sensitive, high impedance inputs can degrade signal integrity. To maximize system performance, use guard rings / shields aroun d these high impedance op amp inputs. For non-inver ting op amps, IN+ should have a guard ring driven to the voltage of IN- by a low impedance source. Similarly, the guard ring around IN- should be driven to IN+ for an inverting amplifier. The IN- and IN+ nodes for non-inverting and inverting amplifiers respectively can be used as low impedance voltage sources. This is because these nodes are effectively low impedance nodes due to op amp feedback properties. For a non-inverting amplifier, leakage current on IN+ will produce a voltage on the input that will be amplified to the op amp’s output. On the other hand, the op amp will fight changes in voltage on IN- to match the voltage potential at IN+. These guard rings should be used on both sides of the PCB to help sink stray currents on the PCB before the currents can reach the input pins of the op amp and to minimize stray capacitance. Proper Setup for Unused Op Amps For an unused op amp on the SLG88103/4, connect the op amp as a voltage follower with the input tied to ground and it’s enable pin tied to VDD. An example circuit using one of the op amps is shown below. Application Examples The SLG88103/4 excels in low-power applications that operate at low frequencies. Please see the “Application Notes” section of this datasheet for application examples which use the SLG88103/4. Fig 33. Unused Op Amp Setup.

000-0088103/4-103 Page 12 of 21 SLG88103/4 Design Resources 1. Spice Macro Model The most recent SPICE model is available on the Renesas website. This model is intended for simulation purposes only and shouldn’t be used in place of hardware testing to verify proper functionality in a full system. 2. Application Notes For more information on the topics discussed in this datasheet and applications of this device, please see the following applications notes available online at our Application Notes page. New Application Notes are added regularly. AN-1106 Custom Instrumentation Amplifier Design 3. Design Support Please contact a Renesas Representative at our Contact page for more information on the SLG88103/4. They will be happy to assist you by answering additional questions and by offering design support for projects relating to the SLG88103/4 and Renesas’s GreenPAK devices. 4. Op Amp + GreenPAK EVB The OP AMP+GreenPAK EVB provides convenient breakout access for various IC’s in Renesas’s Op Amp and GreenPAK product families. Please see the OP AMP+EVB Layout Guide for more information on which GreenPAK devices and op amps can be placed on this PCB. Fig 34. Op Amp + GreenPAK EVB.

000-0088103/4-103 Page 13 of 21 SLG88103/4 PPA Part Code + Assembly Code Pin 1 Identifier WWN Date Code + S/N Code R Revision Code PP - Part ID Field WW - Date Code Field N - Lot Traceability Code Field 1 A - Assembly Site Code Field 2 R - Part Revision Code Field 2 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z

000-0088103/4-103 Page 14 of 21 SLG88103/4 PPPPP Part Code Pin 1 Identifier WWNNN Date Code + LOT Code ARR Assembly + Rev. Code PPPPP - Part ID Field WW - Date Code Field NNN - Lot Traceability Code Field 1 A - Assembly Site Code Field 2 RR - Part Revision Code Field 2 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z

000-0088103/4-103 Page 15 of 21 SLG88103/4

10 Lead STDFN Package

000-0088103/4-103 Page 16 of 21 SLG88103/4

20 Lead STQFN Package

000-0088103/4-103 Page 17 of 21 SLG88103/4 Recommended Land Pattern - SLG88103 Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.2 mm 3 (nominal). More information can be found at www.jedec.org.

000-0088103/4-103 Page 18 of 21 SLG88103/4 Recommended Land Pattern - SLG88104 Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.85 mm 3 (nominal). More information can be found at www.jedec.org.

000-0088103/4-103 Page 19 of 21 SLG88103/4 Tape and Reel Specifications Carrier Tape Drawing and Dimensions - SLG88103 Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STDFN 10L 2x2mm 0.4P COL Green 10 2 x 2 x 0.55 3000 3000 178 / 60 100 400 100 400 8 4 STQFN 20L 2x3.5mm 0.4P Green 20 2 x 3.5 x 0.55 5000 10000 330 /100 42 336 42 336 12 8 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STDFN 10L 2x2mm 0.4P COL Green Refer to EIA-481 specification

000-0088103/4-103 Page 20 of 21 SLG88103/4 Carrier Tape Drawing and Dimensions Dimensions - SLG88104 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 20L 2x3.5mm 0.4P Green Refer to EIA-481 specification

000-0088103/4-103 Page 21 of 21 SLG88103/4

Revision History

2/17/2022 1.03 Renesas rebranding Fixed typos 4/25/2017 1.02 Replaced Input Current vs.V CM Chart 3/13/2017 1.01 Replaced Slew Rate vs. Ambient Temperature Chart Fixed Chart formatting for some charts. Fixed typos 3/1/2017 1.00 Production Release

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