SLG84901

SLG84901 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Paul Cheng
• PDF pages: 22

Technical content

Features

• CK420BQ Clock Specification Revision 1.0
• PCIe Gen2: 3.1ps rms phase jitter compliant
• PCIe Gen3: 1.0ps rms phase jitter compliant
• Intel QPI: 0.3ps rms phase jitter compliant
• 64 pin TSSOP Package (6/6 RoHS Compliant) Output Summary
• 4- differential CPU clock outputs
• 5 - single-ended PCI clock outputs
• 2 - non-spread differential SAS clock outputs
• 3 - differential Serial Reference Clock (SRC) clock outputs
• 2 - non-spread differential NTB SRC clock outputs
• 1 - single-ended 48MHz clock output
• 1 - differential DOT96 clock output
• 1 - single-ended REF 14.318MHz clock output Other brands and names may be claimed as the property of others Pin Configuration PWRGD#/PD TEST_MODE VDDA_96 DOT_96# DOT_96 GND_96 GND *USB_48/100M_133M# VDD_48 VDD_PCI GND_PCI PCI_0 PCI_1 PCI_2 PCI_3 PCI_4 VDD_PCI GND_PCI VDD_XTAL X2_25 X1_25 GND_XTAL GND_14 **REF/TEST_SEL VDD_14 VDDA_14 GNDA_14 SCL SRC_1# SRC_1 SRC_2# SRC_2 VDD_SRC VDDA_SRC GNDA IREF NS_SRC_0# NS_SRC_0 NS_SRC_1# NS_SRC_1 VDD GND NS_SAS_0# NS_SAS_0 NS_SAS_1# NS_SAS_1 VDDA_SAS GNDA CPU_0# CPU_0 CPU_1# CPU_1 SLG84901 64-pin TSSOP * Default power up frequency

Table 1. Frequency Select Table (FS_C, FS_B, FS_A)

Pin # Name Type

Description

I Serial Interface bus clock input. GNDA_14 GND Ground for outputs. VDDA_14 PWR 3.3V power supply for outputs. VDD_14 PWR 3.3V power supply for outputs. REF/TEST_SEL I/O, SE 14.318MHz reference clock output. When TEST_SEL input is pulled to 3.3V during CKPWRGD# assertion, the device will configure into TEST MODE. Refer to DC Paramete rs section for FS input voltage threshold. After CKPWRGD assertion, this pin will be configured as REF output. GND_14 GND Ground for outputs. GND_XTAL GND Ground for outputs. X1_25 I 25MHz crystal input. X2_25 O, SE 25MHz crystal output. VDD_XTAL PWR 3.3V power supply for outputs. GND_PCI GND Ground for outputs. VDD_PCI PWR 3.3V power supply for outputs. PCI_4 O, DIF PCI clock output. PCI_3 O, DIF PCI clock output. PCI_2 O, DIF PCI clock output. PCI_1 O, DIF PCI clock output. PCI_0 O, DIF PCI clock output. GND_PCI GND Ground for outputs. VDD_PCI PWR 3.3V power supply for outputs. VDD_48 PWR 3.3V power supply for outputs. USB_48/100M_133M# I/O, SE USB clock output. CPU Frequency Select, latched input. GND GND Ground for outputs. GND_96 GND Ground for outputs. DOT_96 O, DIF 96 MHz DOT clock output. DOT_96# O, DIF 96 MHz DOT clock output. VDDA_96 PWR 3.3V power supply for outputs. TEST_MODE I When in test mode, TEST_MODE will configure outputs to run at REF or Hi-Z. 0 = Hi-Z, 1 = REF PWRGD#/PD I CKPWRGD is a 3.3V LVTTL iput. It ac ts as a level sensitive strobe to latch the FS pins and other multiplexed inputs. After CKPWRGD assertion, it becomes a real time input for asserting power down (active high). VDD_SRC PWR 3.3V power supply for outputs. SRC_0 O, DIF Differential Serial Reference Clock output. SRC_0# O, DIF Differential Serial Reference Clock output.

*Note: Do not leave unused hardware str ap pin floating, please add external pull-up and pull-down resistors on the schematic. GND GND Ground for outputs. SRC_1# O, DIF Differential Serial Reference Clock output. SRC_1 O, DIF Differential Serial Reference Clock output. SRC_2# O, DIF Differential Serial Reference Clock output. SRC_2 O, DIF Differential Serial Reference Clock output. VDD_SRC PWR 3.3V power supply for outputs. VDDA_SRC PWR Low voltage I/O power supply for outputs. GNDA GND Ground for outputs. IREF I A precision resistor is attached to this pin, which is connected to the internal current reference. No Spread. NS_SRC_0# O, DIF Differential Serial Reference Clock output. No Spread. NS_SRC_0 O, DIF Differential Serial Reference Clock output. No Spread. NS_SRC_1# O, DIF Differential Serial Reference Clock output. No Spread. NS_SRC_1 O, DIF Differential Serial Reference Clock output. No Spread. VDD PWR 3.3V power supply for outputs. GND GND Ground for outputs. NS_SAS_0# O, DIF Differentia l SAS Clock output. No Spread. NS_SAS_0 O, DIF Differential SAS Clock output. No Spread. NS_SAS_1# O, DIF Differentia l SAS Clock output. No Spread. NS_SAS_1 O, DIF Differential SAS Clock output. No Spread. VDDA_SAS PWR 3.3V power supply for outputs. GNDA GND Ground for outputs. CPU_0# O, DIF Differential CPU Clock output. CPU_0 O, DIF Differential CPU Clock output. CPU_1# O, DIF Differential CPU Clock output. CPU_1 O, DIF Differential CPU Clock output. VDD_CPU PWR 3.3V power supply for outputs. GND GND Ground for outputs. CPU_2# O, DIF Differential CPU Clock output. CPU_2 O, DIF Differential CPU Clock output. CPU_3# O, DIF Differential CPU Clock output. CPU_3 O, DIF Differential CPU Clock output. VDD_CPU PWR 3.3V power supply for outputs. SDA I/O, SE Serial Interface bus data input and output. Pin Description (continued) Pin # Name Type

Figure 1. Simplified Block Diagram

A two-wire serial interface is provided as the programming inte rface for the clock synthesizer. The serial interface is fully c ompli- ance to the SMBus 2.0 specification. The registers associated with the two-wire inte rface initializes to their default setting upon power-up, and theref ore use of this interface is optional. The serial interface supports block write and block read operatio n from any SMBus master devices. For block write and block read operations, the bytes must be accessed in sequential order from lowest to highest by te (most significant bit first) with t he ability to stop after any complete byte has been transferre d. The block write and block read protocol is outlined in Table 2 . The slave receiver address is 11010010 (D2h). Table 2. Block Read and Block Write protocol 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits Write Write Acknowledge from slave Acknowledge from slave 11:18 Command Code - 8 Bit '00000000' stands for block operation 11:18 Command Code - 8 Bit '00000000' stands for block operation Acknowledge from slave Acknowledge from slave 20:27 Byte Count - 8 bits Repeat start Acknowledge from slave 21:27 Slave address - 7 bits 29:36 Data byte 0 - 8 bits Read Acknowledge from slave Acknowledge from slave 38:45 Data byte 1 - 8 bits 30:37 Byte count from slave - 8 bits Acknowledge from slave Acknowledge .... Data Byte N/Slave Acknowledge... 39:46 Data byte from slave - 8 bits .... Data Byte N - 8 bits Acknowledge .... Acknowledge from slave 48:55 Data byte from slave - 8 bits .... Stop Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave - 8 bits .... Not Acknowledge .... Stop

Table 3. Byte Read and Byte Write protocol 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits Write Write Acknowledge from slave Acknowledge from slave 11:18 Command Code - 8 bits '1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code - 8 bits '1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Acknowledge from slave 20:27 Data byte - 8 bits Repeat start Acknowledge from slave 21:27 Slave address - 7 bits Stop Read Acknowledge from slave 30:37 Data byte from slave - 8 bits Not Acknowledge Stop

DOT_96 Output Enabled 0 = Disabled 1 = Enabled RW NS_SAS_1 Output Enabled 0 = Disabled 1 = Enabled RW NS_SAS_0 Output Enabled 0 = Disabled 1 = Enabled RW NS_SRC_1 Output Enabled 0 = Disabled 1 = Enabled RW NS_SRC_0 Output Enabled 0 = Disabled 1 = Enabled RW SRC_2 Output Enabled 0 = Disabled 1 = Enabled RW SRC_1 Output Enabled 0 = Disabled 1 = Enabled RW SRC_0 Output Enabled 0 = Disabled 1 = Enabled Control Register 1 Bit Type Description/Function Power up condition RW REF Output Enabled 0 = Disabled 1 = Enabled RW Reserved RW Reserved RW CPU_3 Output Enabled 0 = Disabled 1 = Enabled RW CPU_2 Output Enabled 0 = Disabled 1 = Enabled RW CPU_1Output Enabled 0 = Disabled 1 = Enabled RW CPU_0 Output Enabled 0 = Disabled 1 = Enabled RW Spread Spectrum Mode 0 = Spread off 1 = Spread on

PCI_4 Output Enabled 0 = Disabled 1 = Enabled RW PCI_3 Output Enabled 0 = Disabled 1 = Enabled RW PCI_2 Output Enabled 0 = Disabled 1 = Enabled RW PCI_1 Output Enabled 0 = Disabled 1 = Enabled RW PCI_0 Output Enabled 0 = Disabled 1 = Enabled RW USB_48 Output Enabled 0 = Disabled 1 = Enabled Control Register 3 Bit Type Description/Function Power up condition RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved Control Register 4 Bit Type Description/Function Power up condition RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved

Note: All values not listed in the table above are not supported. Control Register 5 Bit Type Description/Function Power up condition RW Reserved RW Reserved RW Reserved RW NS_SAS/NS_SRC Frequency Select FS_4 RW NS_SAS/NS_SRC Frequency Select FS_3 RW NS_SAS/NS_SRC Frequency Select FS_2 RW NS_SAS/NS_SRC Frequency Select FS_1 RW NS_SAS/NS_SRC Frequency Select FS_0 NS_SAS Frequency Margining Table Byte 5 NS_SAS/NS_SRC (MHz) B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 9 8 . 5 0 100M (Default) 101.50 Control Register 6 Bit Type Description/Function Power up condition RW Test Mode 0 = Hi-Z or tristate 1 = REF/N R W T e s t S e l e c t 0 = Normal operation 1 = Test Mode enabled RW Reserved R 100M_133MHz# Frequency Select RW CPU Frequency Margining bit 3 RW CPU Frequency Margining bit 2 RW CPU Frequency Margining bit 1 RW CPU Frequency Margining bit 0

Note: Frequency values not listed in the table above are not supported. CPU Frequency Margining Table Byte 6 CPU (MHz) SRC (MHz) PCI (MHz) Bit 4 (HW Latch) Bit 3 Bit 2 Bit 1 Bit 0 1 = 1 0

0 M H

z 100.00 (Default) 100.00 33.33 1 = 1 0 z 9 5 . 0 0 9 5 . 0 0 3 1 . 6 6 1 = 1 0 z 1 0 5 . 0 0 1 0 5 . 0 0 3 5 . 0 0 0 = 1 3

3 M H

z 133.33 (Default) 100.00 33.33 0 = 1 3 z 1 2 6 . 6 6 9 5 . 0 0 3 1 . 6 6 0 = 1 3 z 1 4 0 . 0 0 1 0 5 . 0 0 3 5 . 0 0 Control Register 7 Bit Type Description/Function Power up condition R Revision ID bit 3 R Revision ID bit 2 R Revision ID bit 1 R Revision ID bit 0 R Vendor ID bit 3 R Vendor ID bit 2 R Vendor ID bit 1 R Vendor ID bit 0 Control Register 8 Bit Type Description/Function Power up condition 7:0 RW Byte count register for block read operation Note: The default value is 10. To read more than 10 bytes, system BIOS needs to change this register to the number of bytes it intends to read. 00001010 Control Register 9 Bit Type Description/Function Power up condition R Device ID bit 7 R Device ID bit 6 R Device ID bit 5 R Device ID bit 4 R Device ID bit 3 R Device ID bit 2 R Device ID bit 1 R Device ID bit 0

7:6 RW REF Drive Strength 00 = 1X 01 = 2X 10 = 3X 11 = Reserved RW PCI Drive Strength 0 = 1X 1 = 2X RW USB Drive Strength 0 = 1X 1 = 2X RW CPU PLL SS 0 = Center Spread 1 = Down Spread RW Reserved 1:0 RW Table SS Ratio 00 = 0.2% 01 = 0.3% 10 = 0.5% 11 = 1.0%

Parallel Resonance Crystal. Substituting a series resonance crystal will cause the SLG84901 to operate at the wrong frequency and violate the ppm specification. Fo r most applications there is a 300ppm frequency shift between series and parallel crystals due to incorrect loading. Absolute Maximum Ratings Max VDD Supply Voltage (VDD_3.3) C to + 150 C Operating Temperature (Ambient, no airflow): . 0 C to +70 C ESD Protection (Min): Table 4. Crystal Recommendations. 3.3V Core Supply Voltage ±5% 3.135 3.465 V VDD_3.3 3.3V Supply Voltage ±5% 3.135 3.465 V Vih Input High Voltage 2.0 VDD+0.3 V Vil Input Low Voltage VSS-0.3 0.8 V Iil Input Leakage Current 0 < Vin < VDD uA Vih_FS Input High Voltage (FS) 0.7 1.5 V Vil_FS Input Low Voltage (FS) VSS-0.3 0.35 V Voh Output High Voltage (SE) Ioh = -1mA 2.4 V Vol Output Low Voltage (SE) Iol = 1mA 0.4 V Cin Input Pin Capacitance 2.5 4.5 pF Cxtal Xtall Pin Capacitance pF Cout Output Pin Capacitance 2.5 4.5 pF Lpin Pin Inductance n H Ta Ambient Temerature No Airflow C V_max Diff Max Output Include Overshoot 1.15 V V_min Diff Min Output Include Undershoot -0.3 V Idd Full Active 350 mA Idd_pd Power Down Mode Outputs = tristate mA

Differential Outputs (CPU, SRC, DOT_96) Timing Characteristics Symbol Min. Max. Unit Conditions Laccurracy Long term accuracy 100 ppm Using frequency counter with the measure- ment interval equal or greater than 0.15 sec- ond Tperiod Average CPU Period (100MHz, SSC enabled) 9.99906 10.05107 ns Average period over 1 us Tperiod Average CPU Period (133MHz, SSC enabled) 7.44930 7.53830 ns Average period over 1 us Tperiod Average SRC Period (100MHz, SSC enabled) 9.99906 10.05107 ns Average period over 1 us Tperiod Average DOT_96 Period (96MHz) 10.41354 10.41979 ns Average period over 1 us Tabs Absolute Min/Max CPU Period (100, SSC disabled) 9.94900 10.05100 ns Tabs Absolute Min/Max CPU Period (133, SSC disabled) 7.44925 7.55075 ns Tabs Absolute Min/Max CPU Period (100, SSC enabled) 9.94906 10.10107 ns Tabs Absolute Min/Max CPU Period (133, SSC enabled) 7.44930 7.58830 ns Tabs Absolute Min/Max SRC Period (100, SSC disabled) 9.94900 10.05100 ns Tabs Absolute Min/Max SRC Period (100, SSC enabled) 9.94906 10.10107 ns Tabs Absolute Min/Max NS_SRC Period (SSC enabled) 9.94900 10.05100 ns Tabs Absolute Min/Max NS_SAS Period (SSC disabled) 9.94900 10.05100 ns Tabs Absolute Min/Max DOT_96 Period (96MHz) 10.16563 10.66771 ns Slew_rise Rising slew rate 1.0 4.0 V/ns 1. Use ‘average’ acquisition mode of the scope 2. Measurement taken from differential wave- form 3. Slew rate measured through V_swing volt- age range centered about differential zero Slew_fall Falling slew rate 1.0 4.0 V/ns 1. Use ‘average’ acquisition mode of the scope 2. Measurement taken from differential wave- form 3. Slew rate measured through V_swing volt- age range centered about differential zero Slew_var Slew rate matching 1. Use ‘average’ acquisition mode of the scope 2. Measurement taken from single ended waveform 3. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcu- lation V_swing Differential output swing 300 mV Measurement taken from differential wave- form V_cr Crossing point voltage 250 550 mV 1. Measurement taken from single ended waveform 2. V_cross is defined as the voltage where Clock = Clock# 3. Only applies to the differential rising edge (i.e. Clock rising and Clock# falling) V_cr_dlt Variation of V_cr 140 mV 1. Measurement taken from single ended waveform 2. V_cross is defined as the voltage where Clock = Clock# 3. V_cross delta is defined as the total varia- tion of all crossing voltages of rising Clock and falling Clock# Tskew CPU[0:3] skew ps Tccjitter Cycle to Cycle Jitter (CPU) ps Tccjitter Cycle to Cycle Jitter (SRC) ps Tccjitter Cycle to Cycle Jitter (NS_SAS) ps

Cycle to Cycle Jitter (NS_SRC) ps Tccjitter Cycle to Cycle Jitter (DOT_96) 250 ps Tpj_src SRC Phase Jitter PCIe Gen 2 3.1 ps RMS Jitter. PCI-SI G Gen 2 Condition Tpj_src SRC Phase Jitter PCIe Gen 3 1.0 ps RMS Jitter. PCI-SI G Gen 3 Condition Tpj_cpu QPI Phase Jitter (QPI 4.8Gb/s or 6.4Gb/s, 100MHz or 133Mhz) 0.5 ps RMS Jitter. QPI Tpj_cpu QPI Phase Jitter (QPI 8Gb/s, 100MHz) 0.3 ps RMS Jitter. QPI Duty Cycle Duty Cycle Differential Outputs (CPU, SRC, DOT_96) Timing Characteristics Symbol Min. Max. Unit Conditions PCI Timing Characteristics Symbol

1. Measured with respect to 1.5V 2. Using frequency counter with the measure- ment interval equal or greater than 0.15s, tar- get frequency is 33.333333MHz Tperiod Average Period (SSC disabled) 29.99700 30.00300 ns 1. Measured with respect to 1.5V 2. Average period over any 1us period of time Tperiod Average Period (SSC enabled, -0.5%) 29.99718 30.15320 ns 1. Measured with respect to 1.5V 2. Average period over any 1us period of time Tabs Absolute Min/Max Period (SSC disabled) 29.49700 30.50300 ns Tabs Absolute Min/Max Period (SSC enabled, -0.5%) 29.49718 30.65320 ns Thigh CLK high time ns Tlow CLK low time ns Edge Rate Rising edge rate 1.0 4.0 V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Edge Rate Falling edge rate 1.0 4.0 V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Tccjitter Cycle to cycle jitter 500 ps Measured with respect to 1.5V Duty Cycle Duty Cycle Measured with respect to 1.5V USB_48 Timing Characteristics Symbol
2. Measured with respect to 1.5V 2. Using frequency counter with the measure- ment interval equal or greater than 0.15s, tar- get frequency is 48.000000MHz Tperiod Average Period 20.83125 20.83542 ns 1. Measured with respect to 1.5V 2. Average period over any 1us period of time Tabs Absolute Min/Max Period 20.48125 21.18542 ns Thigh CLK high time 8.094 10.036 ns Tlow CLK low time 7.694 9.836 ns Edge Rate Rising edge rate 1.0 2.0 V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Edge Rate Falling edge rate 1.0 2.0 V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system

Measured with respect to 1.5V Duty Cycle Duty Cycle Measured with respect to 1.5V USB_48 Timing Characteristics Symbol REF Timing Characteristics Symbol

1. Measured with respect to 1.5V 2. Using frequency counter with the measure- ment interval equal or greater than 0.15s, tar- get frequency is 25MHz Tperiod Average Period 69.83429 69.84826 ns 1. Measured with respect to 1.5V 2. Average period over any 1us period of time Tabs Absolute Min/Max Period 68.78429 69.89826 ns Edge Rate Rising edge rate 1.0 4.0 V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Edge Rate Falling edge rate 1.0 4.0 V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Tccjitter Cycle to cycle jitter 1000 ps Measured with respect to 1.5V Duty Cycle Duty Cycle Measured with respect to 1.5V

PWRDN# Assertion PWRGD Assertion (PWRDN# De-assertion) Single-ended Measurement Points for Trise, Tfall

Single-ended Measurement Points for Vovs, Vuds, Vrb Differential (Clock - Clock#)Measurement Points for Tperiod, Duty Cycle, Jitter

Vcross Range Clarification Test and Measurement - Differential Impedance Transmission Line Rs Z = 10” (typ) Output Rs Rp Z = 10” (typ) R p Clock Board Trace Impedance Rs Rp RIref Units DIFF Clocks 50 Ω Configuration 100 33 (5%) 49.9 (1%) 475 (1%) Ω DIFF Clocks 43 Ω Configuration 27 (5%) 42.2 (1%) 412 (1%) Ω

64 Lead Green Package TSSOP

Commercial, 0 to 70 C SLG84901TTR

64 Lead Green Package TSSOP - Tape and Reel

Commercial, 0 to 70 C

Package Drawing and Dimensions

64 Lead TSSOP Package

Tape and Reel Specifications Carrier Tape Drawing and Dimensions Package Type # of Pins Nominal Package Size (mm) Max Units Hub & Reel Size (mm) Trailer A Leader B Pocket Tape (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch TSSOP 64L 240 mil Green 17x8.1 2,000 2,000 504 504 Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) E F W TSSOP 64L 240 mil Green 8.4 17.3 1.6 1.5 1.75 11.5 W E Y Y Section Y-Y C L F

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