SLG7SQ47664 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 16

Technical content

Datasheet SLG7SQ47664 Low Power Compact Sequencer R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 1 © 2025 Renesas Electronics Features ■ Low power consumption ■ Programmable time delays between enable signals, no need for external capacitor adjustable time delays ■ Power supply monitoring from 0.05 V to VDD, no need for an external resistor to adjust voltage monitoring threshold ■ Output stages: inverting or non-inverting open-drain output ■ Pb-free/RoHS compliant ■ Halogen-free ■ STQFN-12 package Applications ■ Desktop/notebook computers, servers ■ Low power portable equipment ■ Routers base stations ■ Line cards ■ Graphics cards Output Summary ■ Two outputs – open-drain NMOS 1x

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 2

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 3

  1. Pin Information 2.1 Pin Assignments

Figure 3. Pin Assignments – Top View 2.2 Pin Descriptions Pin # Pin Name Type Description Internal Resistor 1 VDD PWR Supply Voltage -- 2 EN Digital Input Digital Input without Schmitt Trigger 1 MΩ Pull-Down 3 SCL Digital Input Digital Input with Schmitt Trigger Floating 4 SDA Digital Input Digital Input with Schmitt Trigger Floating 5 NC -- Keep Floating or Connect to GND -- 6 NC -- Keep Floating or Connect to GND -- 7 GND GND Ground -- 8 VIN Analog Input/Output Analog Input/Output Floating 9 ENOUT Digital Output Open-Drain NMOS 1x Floating 10 nENOUT Digital Output Open-Drain NMOS 1x Floating 11 NC -- Keep Floating or Connect to GND -- 12 NC -- Keep Floating or Connect to GND --

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 6 3. Specifications 3.1 Absolute Maximum Ratings Quiescent Current IQ Static inputs and floating outputs. PIN3 and PIN4 are HIGH, PIN2 and PIN8 are LOW -- 25 -- µA

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 7 Parameter Symbol Condition/Note Min Typ Max Unit LOW-Level Output Voltage VOL Open-Drain NMOS 1x, IOL = 1 mA, VDD = 2.5 V -- -- 0.036 V Open-Drain NMOS 1x, IOL = 3 mA, VDD = 3.3 V -- -- 0.089 V Open-Drain NMOS 1x, IOL = 5 mA, VDD = 5.0 V -- -- 0.112 V LOW-Level Output Current [2] IOL Open-Drain NMOS 1x, VOL = 0.15 V, VDD = 2.5 V 3.676 -- -- mA Open-Drain NMOS 1x, VOL = 0.4 V, VDD = 3.3 V 11.438 -- -- mA Open-Drain NMOS 1x, VOL = 0.4 V, VDD = 5.0 V 15.397 -- -- mA Internal Pull-Down Resistance RPULL_DOWN Pull-down on PIN2 -- 1 -- MΩ MS ACMP Channel0 Threshold Voltage VACMP Low to High, TA = 25°C 597 -- 619 mV Low to High, TA = -40 °C to +85 °C [3] 593 -- 619 mV High to Low, TA = 25°C 597 -- 618 mV High to Low, TA = -40 °C to +85 °C [3] 593 -- 619 mV

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 8

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 12 7. Package Top Marking Definitions Datasheet Revision Programming Code Number Lock Status Checksum Part Code Revision Date 1.00 001 U 0x2DA14C65 7/1/2024 Lock coverage for this part is indicated by √, from one of the following options: √ Unlocked Partly lock read (mode 1) Partly lock read2 (mode 2) Partly lock read2/write (mode 3) All lock read (mode 4) All lock write (mode 5) All lock read/write (mode 6) The IC security bit is locked/set for code security for production unless otherwise specified. The Programming Code Number is not changed based on the choice of locked vs. unlocked status.

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 13 8. Package Outlines

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 14 9. Layout Guidelines

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 15 10. Ordering Information 12 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4

10.2 Carrier Tape Drawing and Dimensions Package Type

Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width

R19DS0130EU0100 Rev.1.00 Jan 29, 2025 Page 16 11. Revision History Revision Date Description 1.00 Jul 1, 2024 Initial release