SLG7NT4964VTR

SLG7NT4964V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 8

Technical content

Features

• Low Power Consumption
• Pb - Free / RoHS Compliant
• Halogen - Free
• S T QFN - 12 Package Output Summary
• 4 Outputs — Push Pull 1X Pin Configuration 4 5 6 12 11 S T Q FN - 12 TOP VIEW VDD V5S_PWRGD VDDQ VTT_EN SLP_S4_N VPP GND VDDQ_BLEED VDDQ_EN VDDQ_PWRGD SLP_S3_N VPP_EN Renesas SLG7NT4964 is a low power and small form device. The SoC is housed in a 1.6 x 1.6 mm STQFN package which is optimal for using with small devices.

DDR_RAIL SEQUENCING SLG7NT4964_DS_r10 2 Page 2 P in Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 V5S_PWRGD Digital Input Digital Input without Schmitt trigger

3 VDDQ Analog

4 VTT_EN Digital Output Push Pull 1X

5 SLP_S4_N Digital Input Digital Input without Schmitt trigger

6 VPP Analog

7 GND GND Ground

8 VDDQ_BLEED Digital Output Push Pull 1X

9 VDDQ_EN Digital Output Push Pull 1X

10 VDDQ_PWRGD Digital Input Digital Input without Schmitt trigger

11 SLP_S3_N Digital Input Digital Input without Schmitt trigger

12 VPP_EN Digital Output Push Pull 1X

Ordering Information

SLG7NT4964V V= S TQFN - 12 SLG7NT4964VTR S TQFN - 12 – Tape and Reel (3k units)

DDR_RAIL SEQUENCING SLG7NT4964_DS_r10 2 Page 3 Absolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 125 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1000 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 3 3.3 3.6 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 65 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side -- -- 90 mA V IH HIGH - Level Input Voltage Logic Input, at VDD=3.3V 1.78 -- VDD V V IL LOW - Level Input Voltage Logic Input, at VDD=3.3V -- -- 1.21 V I IH HIGH - Level Input Current Logic Input PINs; V IN = VDD - 1.0 -- 1.0 µA I IL LOW - Level Input Current Logic Input PINs; V IN = 0V - 1.0 -- 1.0 µA V OH HIGH - Level Output Voltage (note 1) Push Pull & PMOS OD, I OH = 3mA, 1X Driver, at VDD=3.3 V 2.71 3.09 -- V V OL LOW - Level Output Voltage (note 1) Push Pull, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.18 0.28 V I OH HIGH - Level Output Current (note 1) Push Pull & PMOS OD, V OH = 2.4 V, 1X Driver, at VDD=3.3 V 5.83 10.158 -- mA I OL LOW - Level Output Current (note 1) Push Pull, V OL =0.4V, 1X Driver, at VDD=3.3 V 4.06 6.44 -- mA V ACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 189 -- 212 mV ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40 +85°C (note 1) 186 -- 214 V ACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 1164 -- 1235 mV

DDR_RAIL SEQUENCING SLG7NT4964_DS_r10 2 Page 4 ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40 +85°C (note 1) 1150 -- 1246 T DLY1 Delay1 Time At temperature 25°C 116.88 140 185.5 µs At temperature - 40°C +85°C (note 1) 105.11 140 215.2 T SU Start up Time From VDD rising past 1.35V -- 0.31 -- ms 1. Guaranteed by Design.

DDR_RAIL SEQUENCING SLG7NT4964_DS_r10 2 Page 5 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.0 2 002 L SQ A 0 2 / 25 /20 22 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

DDR_RAIL SEQUENCING SLG7NT4964_DS_r10 2 Page 6 Package Drawing and Dimensions

12 Lead S TQFN Package

DDR_RAIL SEQUENCING SLG7NT4964_DS_r10 2 Page 7 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch STQFN 12L FC 0.4P Green 12 1.6 x 1.6 x0. 5 5 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W STQFN 12L FC 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 1.408 mm 3 (nominal). More information can be found at www.jedec.org .

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.