SLG7NT4779V RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: pwong
  • PDF pages: 7

Technical content

Features

  • Low Power Consumption
  • Pb - Free / RoHS Compliant
  • Halogen - Free
  • S T QFN - 12 Package Output Summary
  • 3 Outputs — Push Pull 1X
  • 1 Output — 3 - State 1X Pin Configuration 4 5 6 12 11 S T Q FN - 12 TOP VIEW VDD MISO CLK MOSI EN CS GND CS_EXT MOSI_S MISO_S NC CLK_DIV Renesas SLG7NT4779 is a low power and small form device. The SoC is housed in a 1.6 x 1.6 mm STQFN package which is optimal for using with small devices.

Clock Divider and Chip Select Extender SLG7NT4779_DS_r01 6 Preliminary Page 2 P in Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 MISO Digital Input Digital Input without Schmitt trigger

3 CLK Digital Input Digital Input without Schmitt trigger

4 MOSI Digital Input Digital Input without Schmitt trigger

5 EN Digital Input Digital Input without Schmitt trigger

6 CS Digital Input Digital Input without Schmitt trigger

7 GND GND Ground

8 CS_EXT Digital Output Push Pull 1X

9 MOSI_S Digital Output Push Pull 1X

10 MISO_S Digital Output 3 - State Output 1X

11 NC -- Keep Floating or Connect to GND

12 CLK_DIV Digital Output Push Pull 1X

Ordering Information

SLG7NT4779V V= S TQFN - 12 SLG7NT4779VTR S TQFN - 12 – Tape and Reel (3k units)

Clock Divider and Chip Select Extender SLG7NT4779_DS_r01 6 Preliminary Page 3 Absolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 125 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1000 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 3 3.3 3.6 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 1 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side -- -- 90 mA V IH HIGH - Level Input Voltage Logic Input, at VDD=3.3V 1.78 -- VDD V V IL LOW - Level Input Voltage Logic Input, at VDD=3.3V -- -- 1.21 V I IH HIGH - Level Input Current Logic Input PINs; V IN = VDD - 1.0 -- 1.0 µA I IL LOW - Level Input Current Logic Input PINs; V IN = 0V - 1.0 -- 1.0 µA V OH HIGH - Level Output Voltage (note 1) Push Pull & PMOS OD, I OH = 3mA, 1X Driver, at VDD=3.3 V 2.71 3.09 -- V V OL LOW - Level Output Voltage (note 1) Push Pull, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.18 0.28 V I OH HIGH - Level Output Current (note 1) Push Pull & PMOS OD, V OH = 2.4 V, 1X Driver, at VDD=3.3 V 5.83 10.158 -- mA I OL LOW - Level Output Current (note 1) Push Pull, V OL =0.4V, 1X Driver, at VDD=3.3 V 4.06 6.44 -- mA T PD_CLK CLK to CLK_DIV Propagation Delay Time 33 -- 63 ns T PD_CS CS to CS_N Propagation Delay Time 34 -- 62 ns T PD_MOSI MOSI to MOSI_S Propagation Delay Time 29 -- 57 ns T PD_MISO MISO to MISO_S Propagation Delay Time 28 -- 58 ns T SU Start up Time From VDD rising past 1.35 V -- 0.3 1 -- ms 1. Guaranteed by Design.

Clock Divider and Chip Select Extender SLG7NT4779_DS_r01 6 Preliminary Page 4 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 0.1 6 004 U UW A 0 2 / 2 5 /20 23 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

Clock Divider and Chip Select Extender SLG7NT4779_DS_r01 6 Preliminary Page 5 Package Drawing and Dimensions

12 Lead S TQFN Package

Clock Divider and Chip Select Extender SLG7NT4779_DS_r01 6 Preliminary Page 6 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch STQFN 12L FC 0.4P Green 12 1.6 x 1.6 x0. 5 5 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W STQFN 12L FC 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 1.408 mm 3 (nominal). More information can be found at www.jedec.org .

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