SLG7NT4774V RENESAS | Alldatasheet
Document overview
- Manufacturer or author: pwong
- PDF pages: 9
Technical content
Features
- Low Power Consumption
- Pb - Free / RoHS Compliant
- Halogen - Free
- S T QFN - 20 Package Output Summary
- 7 Outputs — Open Drain NMOS 1X Pin Configuration 11 8 9 10 20 19 18 S T Q FN - 20 TOP VIEW VDD SLG7NT4774 GND PWRGD_PC PROCID_1 VCCORE_PWRGD VCCSA_PWRGD VM_1 VR_EN DRAM_PWRGD SLP_S3_N VM_2 VCCIO_PWRGD VCCIO RSMRST_PWRGD_N SYS_PWROK VCCSA_EN VCCORE_EN VCCIO_EN ALL_SYS_PWRGD/VCCST_P WRGD PCH_PWROK Renesas SLG7NT4774 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices.
ALL_SYS_PWRGD and PCH_PWROK and SYS_PWROK Logic SLG7NT4774_DS_r10 5 SLG7NT4774 P in Configuration Pin # Pin Name Type Pin Description
1 VDD PWR Supply Voltage
2 PWRGD_PC Digital Input Digital Input without Schmitt trigger
3 PROCID_1 Digital Input Digital Input without Schmitt trigger
4 VCCORE_PWRGD Digital Input Digital Input without Schmitt trigger
5 VCCSA_PWRGD Digital Input Digital Input without Schmitt trigger
6 VM_1 Analog Input/Output Analog Input/Output
7 VR_EN Digital Output Open Drain NMOS 1X
8 DRAM_PWRGD Digital Input Digital Input without Schmitt trigger
9 SLP_S3_N Digital Input Digital Input without Schmitt trigger
10 VM_2 Analog Input/Output Analog Input/Output
11 GND GND Ground
12 VCCIO_PWRGD Digital Input Digital Input without Schmitt trigger
13 VCCIO Analog Input/Output Analog Input/Output
14 RSMRST_PWRGD_N Digital Input Digital Input without Schmitt trigger
15 SYS_PWROK Digital Output Open Drain NMOS 1X
16 ALL_SYS_PWRGD/VCCST_
PWRGD Digital Output Open Drain NMOS 1X
17 PCH_PWROK Digital Output Open Drain NMOS 1X
18 VCCSA_EN Digital Output Open Drain NMOS 1X
19 VCCORE_EN Digital Output Open Drain NMOS 1X
20 VCCIO_EN Digital Output Open Drain NMOS 1X
Ordering Information
SLG7NT4774V V= S TQFN - 20 SLG7NT4774VTR VTR= S TQFN - 20 – Tape and Reel (3k units)
ALL_SYS_PWRGD and PCH_PWROK and SYS_PWROK Logic SLG7NT4774_DS_r10 5 SLG7NT4774 Absolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 125 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 13 00 -- V Moisture Sensitivity Level 1
Electrical Characteristics
(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 3 3.3 3.6 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 80 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2 - PIN10, PIN12 - PIN20) -- -- 90 mA V IH HIGH - Level Input Voltage Logic Input, at VDD=3.3V 1.78 -- VDD V V IL LOW - Level Input Voltage Logic Input, at VDD=3.3V -- -- 1.21 V I IH HIGH - Level Input Current Logic Input PINs; V IN = VDD - 1.0 -- 1.0 µA I IL LOW - Level Input Current Logic Input PINs; V IN = 0V - 1.0 -- 1.0 µA V OL LOW - Level Output Voltage Open Drain, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.080 0.147 V I OL LOW - Level Output Current Open Drain, V OL =0.4V, 1X Driver, at VDD=3.3 V 7.313 12.37 -- mA V ACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 936 -- 964 mV V ACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 936 -- 964 mV V ACMP2 Analog Comparator Threshold Voltage ACMP2 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 640 -- 661 mV T SU Start up Time From VDD rising past 1.6V -- 1 -- ms 1. Guaranteed by Design.
ALL_SYS_PWRGD and PCH_PWROK and SYS_PWROK Logic SLG7NT4774_DS_r10 5 SLG7NT4774 Timing Diagram Case 1: PIN# 3 ( PROCID_1 ) – LOW
ALL_SYS_PWRGD and PCH_PWROK and SYS_PWROK Logic SLG7NT4774_DS_r10 5 SLG7NT4774 Case 2 : PIN# 3 ( PROCID_1 ) – HIGH
ALL_SYS_PWRGD and PCH_PWROK and SYS_PWROK Logic SLG7NT4774_DS_r10 5 SLG7NT4774 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.0 5 009 L 4774V AB 0 2 / 25 /20 2 2 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .
ALL_SYS_PWRGD and PCH_PWROK and SYS_PWROK Logic SLG7NT4774_DS_r10 5 SLG7NT4774 Package Drawing and Dimensions
20 Lead S T Q FN Package
JEDEC MO - 220, Variation WECE IC Net Weight: 0.015 g
ALL_SYS_PWRGD and PCH_PWROK and SYS_PWROK Logic SLG7NT4774_DS_r10 5 SLG7NT4774 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch S T Q FN 20L 2 x3 mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W S T Q FN 20L 2 x3 mm 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). More information can be found at www.jedec.org .
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