SLG7NT4741VTR

SLG7NT4741V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 10

Technical content

Features

• Low Power Consumption
• Pb - Free / RoHS Compliant
• Halogen - Free
• S T QFN - 20 Package Output Summary
• 1 Output — Push Pull 1X
• 7 Outputs — Open Drain NMOS 1X Pin Configuration 11 8 9 10 20 19 18 S T Q FN - 20 TOP VIEW VDD SLG7NT4741 GND PSHBTN_LTCH_IN1 PSHBTN_LTCH_IN2 PSHBTN_IN1 PSHBTN_IN2 HEARTBEAT_EN PASSTHROUGH_IN PWRFLT0_N PWRFLT1_N PWRFLT_DLY_OUT_N PASSTHROUGH_OUT BREATHING_OUT PSHBTN_OUT2 PSHBTN_OUT1 PWRFLT_OUT_N PWRFLT2_N PWRFLT3_N PSHBTN_LTCH_OUT2 PSHBTN_LTCH_OUT1 Renesas SLG7NT4741 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices.

SLG7NT4741_DS_r10 2 SLG7NT4741 Block Diagram

SLG7NT4741_DS_r10 2 SLG7NT4741 P in Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 PSHBTN_LTCH_IN1 Digital Input Low Voltage Digital input

3 PSHBTN_LTCH_IN2 Digital Input Low Voltage Digital input

4 PSHBTN_IN1 Digital Input Low Voltage Digital input

5 PSHBTN_IN2 Digital Input Low Voltage Digital input

6 HEARTBEAT_EN Digital Input Low Voltage Digital input

7 PASSTHROUGH_IN Digital Input Low Voltage Digital input

8 PWRFLT0_N Digital Input Low Voltage Digital input

9 PWRFLT1_N Digital Input Low Voltage Digital input

10 PWRFLT_DLY_OUT_N Digital Output Open Drain NMOS 1X

11 GND GND Ground

12 PASSTHROUGH_OUT Digital Output Open Drain NMOS 1X

13 BREATHING_OUT Digital Output Open Drain NMOS 1X

14 PSHBTN_OUT2 Digital Output Open Drain NMOS 1X

15 PSHBTN_OUT1 Digital Output Open Drain NMOS 1X

16 PSHBTN_LTCH_OUT2 Digital Output Open Drain NMOS 1X

17 PSHBTN_LTCH_OUT1 Digital Output Push Pull 1X

18 PWRFLT_OUT_N Digital Output Open Drain NMOS 1X

19 PWRFLT2_N Digital Input Low Voltage Digital input

20 PWRFLT3_N Digital Input Low Voltage Digital input

Ordering Information

SLG7NT4741V V= S TQFN - 20 SLG7NT4741VTR VTR= S TQFN - 20 – Tape and Reel (3k units)

SLG7NT4741_DS_r10 2 SLG7NT4741 Absolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 125 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 13 00 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 1.71 3 5.5 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 80 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2 - PIN10, PIN12 - PIN20) -- -- 90 mA V IH HIGH - Level Input Voltage Low - Level Logic Input, at VDD=1.8V 0.894 -- VDD V Low - Level Logic Input, at VDD=3.3V 1.059 -- VDD Low - Level Logic Input, at VDD=5.0V 1.157 -- VDD V IL LOW - Level Input Voltage Low - Level Logic Input, at VDD=1.8V 0 -- 0.557 V Low - Level Logic Input, at VDD=3.3V 0 -- 0.686 Low - Level Logic Input, at VDD=5.0V 0 -- 0.776 I IH HIGH - Level Input Current Logic Input PINs; V IN = VDD - 1.0 -- 1.0 µA I IL LOW - Level Input Current Logic Input PINs; V IN = 0V - 1.0 -- 1.0 µA V OH HIGH - Level Output Voltage Push Pull & PMOS OD, I OH = 100uA, 1X Driver, at VDD=1.8 V 1.680 1.788 -- V Push Pull & PMOS OD, I OH = 3mA, 1X Driver, at VDD=3.3 V 2.713 3.095 -- Push Pull & PMOS OD, I OH = 5mA, 1X Driver, at VDD=5.0 V 4.159 4.750 -- V OL LOW - Level Output Voltage Push Pull, I OL = 100uA, 1X Driver, at VDD=1.8 V -- 0.009 0.015 V Open Drain, I OL = 100uA, 1X Driver, at VDD=1.8 V -- 0.007 0.010 Push Pull, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.148 0.228 Open Drain, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.080 0.147

SLG7NT4741_DS_r10 2 SLG7NT4741 Push Pull, I OL = 5mA, 1X Driver, at VDD=5.0 V -- 0.189 0.270 Open Drain, I OL = 5mA, 1X Driver, at VDD=5.0 V -- 0.102 0.180 I OH HIGH - Level Output Current Push Pull & PMOS OD, V OH = VDD - 0.2, 1X Driver at VDD=1.8 V 1.027 1.703 -- mA Push Pull & PMOS OD, V OH = 2.4 V, 1X Driver, at VDD=3.3 V 5.608 10.774 -- Push Pull & PMOS OD, V OH = 2.4 V, 1X Driver, at VDD=5.0 V 20.337 30.010 -- I OL LOW - Level Output Current Push Pull, V OL = 0.15V, 1X Driver, at VDD=1.8 V 0.917 1.660 -- mA Open Drain, V OL = 0.15V, 1X Driver, at VDD=1.8 V 1.375 2.534 -- Push Pull, V OL = 0.4V, 1X Driver, at VDD=3.3 V 4.875 7.795 -- Open Drain, V OL = 0.4V, 1X Driver, at VDD=3.3 V 7.313 12.370 -- Push Pull, V OL = 0.4V, 1X Driver, at VDD=5.0 V 6.996 10.438 -- Open Drain, V OL = 0.4V, 1X Driver, at VDD=5.0 V 10.820 17.380 -- T DLY3 Delay3 Time At temperature 25°C 75,21 91,78 110,11 ms At temperature - 40°C +85°C (note 1) 74,3 93,31 116,97 T DLY4 Delay4 Time At temperature 25°C 974,61 1039,71 1177,65 ms At temperature - 40°C +85°C (note 1) 958,02 1047,51 1189,29 T DLY5 Delay5 Time At temperature 25°C 75,21 91,78 110,11 ms At temperature - 40°C +85°C (note 1) 74,3 93,31 116,97 T DLY7 Delay7 Time At temperature 25°C 75,21 91,78 110,11 ms At temperature - 40°C +85°C (note 1) 74,3 93,31 116,97 T DLY8 Delay8 Time At temperature 25°C 75,21 91,78 110,11 ms At temperature - 40°C +85°C (note 1) 74,3 93,31 116,97 T DLY9 Delay9 Time At temperature 25°C 3,89 4,16 4,72 ms At temperature - 40°C +85°C (note 1) 3,82 4,19 4,77 T SU Start up Time From VDD rising past PON THR 0.526 1.4 5.148 ms PON THR Power On Threshold VDD Level Required to Start Up the Chip 0.950 1.462 1.708 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.935 1.103 1.281 V 1. Guaranteed by Design.

SLG7NT4741_DS_r10 2 SLG7NT4741 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.0 2 002 L 4741V AA 0 2 / 25 /20 22 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

SLG7NT4741_DS_r10 2 SLG7NT4741 Package Drawing and Dimensions

20 Lead S T Q FN Package

JEDEC MO - 220, Variation WECE IC Net Weight: 0.015 g

SLG7NT4741_DS_r10 2 SLG7NT4741 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch S T Q FN 20L 2 x3 mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W S T Q FN 20L 2 x3 mm 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). More information can be found at www.jedec.org .

SLG7NT4741_DS_r10 2 SLG7NT4741 Datasheet Revision History Date Version Change 04 / 23 /201 5 0.10 New design for SLG46620 04/27/2015 0.11 Changed PIN13 name and PIN20 mode to “Low Voltage” 04/27/2015 0.12 Updated Device Revision Table 10/20/2015 0.13 Corrected datasheet 10/26/2015 0.14 Updated Device Revision Table 10/29/2015 0.15 Locked NVM 11/05/2015 1.00 Production Release 03/08/2016 1.01 Updated Title Description 02/25/2022 1.02 Updated Company name and logo

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