SLG7NT4618V

SLG7NT4618V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 10

Technical content

Features

• Low Power Consumption
• Pb - Free / RoHS Compliant
• Halogen - Free
• S T QFN - 20 Package Output Summary
• 8 Outputs — Open Drain NMOS 1X Pin Configuration 11 8 9 10 20 19 18 S T Q FN - 20 TOP VIEW VDD SLG7NT4618 GND WAKE PWRBTN# AC_PRESENT_SOC AC_OK_CHGR SKL_APL_N SLP_S0ix_N PCH_PWROK IMVP_VR_ON VNN_COMP DDR_VR_PWRGD VCCSTG SLP_S3_N VCCST VTT_CTRL PWRBTN_EC 5VR_PWRGD VCCST_PWRGD VNN_PGD Renesas SLG7NT4618 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices.

SLG7NT4618_DS_r02 5 SLG7NT4618 P in Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 WAKE Digital Input Digital Input without Schmitt trigger

3 PWRBTN# Digital Input Digital Input with Schmitt trigger

4 AC_PRESENT_SOC Digital Output Open Drain NMOS 1X

5 AC_OK_CHGR Digital Input Digital Input without Schmitt trigger

6 SKL_APL_N Analog Input/Output Analog Input/Output

7 SLP_S0ix_N Digital Input Low Voltage Digital Input

8 PCH_PWROK Digital Output Open Drain NMOS 1X

9 IMVP_VR_ON Digital Output Open Drain NMOS 1X

10 VNN_COMP Analog Input/Output Analog Input/Output

11 GND GND Ground

12 DDR_VR_PWRGD Digital Input Low Voltage Digital Input

13 VCCSTG Analog Input/Output Analog Input/Output

14 SLP_S3_N Digital Input Low Voltage Digital Input

15 VCCST Analog Input/Output Analog Input/Output

16 VCCST_PWRGD Digital Output Open Drain NMOS 1X

17 VNN_PGD Digital Output Open Drain NMOS 1X

18 VTT_CTRL Digital Output Open Drain NMOS 1X

19 PWRBTN_EC Digital Output Open Drain NMOS 1X

20 5VR_PWRGD Digital Output Open Drain NMOS 1X

Ordering Information

SLG7NT4618V V= S TQFN - 20 SLG7NT4618VTR VTR= S TQFN - 20 – Tape and Reel (3k units)

SLG7NT4618_DS_r02 5 SLG7NT4618 Absolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 150 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 13 00 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 1.659 3.3 5.665 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 80 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2 - PIN10, PIN12 - PIN20) -- -- 90 mA V IH HIGH - Level Input Voltage Logic Input, at VDD=1.8V 1.10 -- VDD V Logic Input with Schmitt Trigger, at VDD=1.8V 1.27 -- VDD Low - Level Logic Input, at VDD=1.8V 0.98 -- VDD Logic Input, at VDD=3.3V 1.78 -- VDD Logic Input with Schmitt Trigger, at VDD=3.3V 2.13 -- VDD Low - Level Logic Input, at VDD=3.3V 1.13 -- VDD Logic Input, at VDD=5.0V 2.64 -- VDD Logic Input with Schmitt Trigger, at VDD=5.0V 3.16 -- VDD Low - Level Logic Input, at VDD=5.0V 1.23 -- VDD V IL LOW - Level Input Voltage Logic Input, at VDD=1.8V -- -- 0.69 V Logic Input with Schmitt Trigger, at VDD=1.8V -- -- 0.44 Low - Level Logic Input, at VDD=1.8V -- -- 0.52 Logic Input, at VDD=3.3V -- -- 1.21 Logic Input with Schmitt Trigger, at VDD=3.3V -- -- 0.95 Low - Level Logic Input, at VDD=3.3V -- -- 0.69 Logic Input, at VDD=5.0V -- -- 1.84

SLG7NT4618_DS_r02 5 SLG7NT4618 Logic Input with Schmitt Trigger, at VDD=5.0V -- -- 1.51 Low - Level Logic Input, at VDD=5.0V -- -- 0.78 I IH HIGH - Level Input Current Logic Input PINs; V IN = VDD - 1.0 -- 1.0 µA I IL LOW - Level Input Current Logic Input PINs; V IN = 0V - 1.0 -- 1.0 µA V OL LOW - Level Output Voltage Open Drain, I OL = 100uA, 1X Driver, at VDD=1.8 V -- 0.005 0.020 V Open Drain, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.080 0.147 Open Drain, I OL = 5mA, 1X Driver, at VDD=5.0 V -- 0.102 0.180 I OL LOW - Level Output Current Open Drain, V OL =0.15V, 1X Driver, at VDD=1.8 V 1.375 2.534 -- mA Open Drain, V OL =0.4V, 1X Driver, at VDD=3.3 V 7.313 12.37 -- Open Drain, V OL =0.4V, 1X Driver, at VDD=5.0 V 10.82 17.38 -- V ACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis. 1034 -- 1342 mV V ACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis. 522 -- 682 mV V ACMP2 Analog Comparator Threshold Voltage ACMP2 threshold including input offset, reference voltage variation and hysteresis. 735 -- 848 mV V ACMP3 Analog Comparator Threshold Voltage ACMP3 threshold including input offset, reference voltage variation and hysteresis. 735 -- 848 mV V HYST Analog Comparator Hysteresis Voltage (note 1) ACMP 2, 3 -- 25 -- mV ACMP 1 -- 50 -- T DLY5 Delay5 Time At temperature 25°C 252.88 300 334.25 µs At temperature - 40°C +85°C (note 1) 229.09 300 395.73 T SU Start up Time From VDD rising past 1.35 V -- 0.3 -- ms 1. Guaranteed by Design.

SLG7NT4618_DS_r02 5 SLG7NT4618 Timing Diagram 1. Case 1 : PIN#6(SKL_APL_N) - LOW

SLG7NT4618_DS_r02 5 SLG7NT4618 2 . Case 2: PIN#6(SKL_APL_N) - HIGH

SLG7NT4618_DS_r02 5 SLG7NT4618 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 0.2 5 009 U 02 / 25 /20 22 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

SLG7NT4618_DS_r02 5 SLG7NT4618 Package Drawing and Dimensions

20 Lead S T Q FN Package

JEDEC MO - 220, Variation WECE IC Net Weight: 0.015 g

SLG7NT4618_DS_r02 5 SLG7NT4618 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch S T Q FN 20L 2 x3 mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W S T Q FN 20L 2 x3 mm 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). More information can be found at www.jedec.org .

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.