SLG7NT4505V RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: pwong
  • PDF pages: 10

Technical content

Features

  • Low Power Consumption
  • 3.3V Supply
  • Pb - Free / RoHS Compliant
  • Halogen - Free
  • TDFN - 8 Package Pin Configuration TDFN - 8 TOP VIEW Thermal Pad connected to GND Output Summary
  • 2 Outputs — Open Drain NMOS 1X VDD NMI_GATE MBL_PGOOD_M R SENSE GND SMC_INIT_CLK SMC_RST_N EX_VREF Renesas GreenPAK SLG7NT4505 is a low power and small form device. The SoC is housed in a 2mm x 2mm TDFN package which is optimal for using with small devices.

1 Hz Interrupt Generator

SLG7NT4505_DS_r10 1 Page 2 Pin Configuration Pin # Pin Name Type Pin Description 1 VDD Power 3.3V Supply Voltage

2 NMI_GATE Digital Input Digital Input without Schmitt trigger

3 MBL_PGOOD_MR Digital Input Digital Input without Schmitt trigger

4 SENSE Analog

Input/Output Analog Input/Output

5 GND GND Ground

6 SMC_INIT_CLK Digital Output Open Drain NMOS 1X

7 SMC_RST_N Digital Output Open Drain NMOS 1X

8 EX_VREF Analog

Input/Output Analog Input/Output Exposed Bottom Pad GND GND Ground Ordering Options & Configuration Part Number Package Type SLG7NT4505V V = TDFN - 8 SLG7NT4505VTR VTR = TDFN - 8 – Tape and Reel (3k units)

SLG7NT4505_DS_r10 1 Page 3 Absolute Maximum Ratings Parameter Min. Max. Unit V DD to GND - 0.3 4.6 V Voltage at input pins - 0.3 4.6 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 150 °C Junction temperature -- 150 °C ESD Human Body Model 2000 -- V ESD Machine Model 200 -- V

Electrical Characteristics

Symbol Parameter Condition / Note Min Typ Max Unit V DD Supply Voltage 3.0 3.3 3.6 V I Q Quiescent Current Static inputs and outputs -- 30 -- μ A T A Operating temperature - 40 25 85 o C V AIR Analog Input Voltage Range 0 -- 2. 2 V V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side -- -- 24 mA V IH HIGH - Level Input Voltage Logic Input 1.6 -- -- V V IL LOW - Level Input Voltage Logic Input -- -- 0.95 V V OL LOW - Level Output Voltage (note 1) Push - Pull , Open Drain Logic Level Outputs 0 -- 0.4 V I IH HIGH - Level Input Current Logic Input Pins; V IN = VDD - 100 -- 100 nA I IL LOW - Level Input Current Logic Input Pins; V IN = 0V - 100 -- 100 nA I OL LOW - Level Output Current (note 1) Open Drain, 1X Driver -- 20 -- mA V OFFSET Analog Comparator Offset Voltage Analog Comparator 0 -- ±20 -- mV V HYST Analog Comparator Hysteresis Voltage (note 1) ACMP 0 -- 50 -- mV R PULL_UP Internal Pull Up Resistance Pull up on PIN3 80 100 120 k Ω T DLY0 Time Delay0 Delay0 16 20 24 ms T DLY2 Time Delay2 Delay2 1.6 2.0 2.4 ms T SU Start Up Time After VDD reaches 2.5V -- 7 -- ms 1. Guaranteed by Design .

SLG7NT4505_DS_r10 1 Page 4

Description

This is a special oscillator with supervisor system. T hree inputs are used to c ontrol the oscillator . SENSE ( PIN4 ) controls the voltage supply of the chip . I f supply voltage decreases down to the threshold set by EX_VREF (PIN8), the chip disables the oscil lator and sets SMC_INICK to LOW . When the voltage is bigger than threshold set by EX_VREF is detect ed on the SENSE pin, SMC_RST_N (PIN7) is set to HIGH with 20 ms delay and enable s the oscillator. MBL_PWRGD_MR_N (PIN3) is used for manual reset of SMC_RST_N. Use NMI_GATE (NMI_GATE) to disable the oscillator.

SLG7NT4505_DS_r10 1 Page 5 Timing Diagram

SLG7NT4505_DS_r10 1 Page 6 Typical Application Circuit SLG7NT4505 VDD data I data I/O data I/O 4 data I/O 6 data I/O 7 data I/O GND 100nF R1 +3.3V SENSE EX_VREF SMC_INIT_CLK SMC_RST_N NMI_GATE MBL_PGOOD_MR V_SOURCE R3 R4

SLG7NT4505_DS_r10 1 Page 7 Package Top Marking Datasheet Revision Programming Code Number Part Code Revision Date 1.0 1 001 YP A 0 2 / 25 /20 22

SLG7NT4505_DS_r10 1 Page 8 Package Drawing and Dimensions

SLG7NT4505_DS_r10 1 Page 9 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch TDFN 8L 2x2mm Green 8 2x2x0.75 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W TDFN 8L 2x2mm Green Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profi le based on package volume of 3.00 mm 3 (nominal). More information can be found at www.jedec.org .

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