SLG7NT4503VTR

SLG7NT4503V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 13

Technical content

Features

• Low Power Consumption
• Pb - Free / RoHS Compliant
• Halogen - Free
• S T QFN - 20 Package Output Summary
• 2 Outputs — Push Pull 2X
• 7 Outputs — Open Drain NMOS 1X Pin Configuration 11 8 9 10 20 19 18 S T Q FN - 20 TOP VIEW VDD SLG7NT4503 GND SC_PWRGD_ATX CORE_1V1_EN/HPS_1V1_EN FPGA_1V2_EN FPGA1V8/HPS1V5_EN FPGA2V5/HPS2V5_EN FPGA3V3/HPS3V3_EN HPS_RST_N Soft Reset In Core_1V1_PWRGD HPS_1V1_PWRGD HPS_POR_N FPGA1V2_PWRGD FPGA1V8/HPS1V5_PWRGD ERROR ALL_PWRGD FPGA_PS_RESET FPGA2V5/HPS2V5_PWRGD FPGA3V3/HPS3V3_PWRGD Renesas SLG7NT4503 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices.

SLG7NT4503_DS_r10 1 SLG7NT4503 Block Diagram

SLG7NT4503_DS_r10 1 SLG7NT4503 P in Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 SC_PWRGD_ATX Digital Input Digital Input without Schmitt trigger

3 CORE_1V1_EN/HPS_1V1_EN Digital Output Open Drain NMOS 1X

4 FPGA_1V2_EN Digital Output Open Drain NMOS 1X

5 FPGA1V8/HPS1V5_EN Digital Output Open Drain NMOS 1X

6 FPGA2V5/HPS2V5_EN Digital Output Open Drain NMOS 1X

7 FPGA3V3/HPS3V3_EN Digital Output Open Drain NMOS 1X

8 HPS_RST_N Digital Output Open Drain NMOS 1X

9 Soft Reset In Digital Input Digital Input without Schmitt trigger

10 Core_1V1_PWRGD Digital Input Digital Input without Schmitt trigger

11 GND GND Ground

12 HPS_1V1_PWRGD Digital Input Digital Input without Schmitt trigger

13 HPS_POR_N Digital Output Open Drain NMOS 1X

14 FPGA1V2_PWRGD Digital Input Digital Input without Schmitt trigger

15 FPGA1V8/HPS1V5_PWRGD Digital Input Digital Input without Schmitt trigger

16 FPGA2V5/HPS2V5_PWRGD Digital Input Digital Input without Schmitt trigger

17 FPGA3V3/HPS3V3_PWRGD Digital Input Digital Input without Schmitt trigger

18 ERROR Digital Output Push Pull 2X

19 ALL_PWRGD Digital Output Push Pull 2X

20 FPGA_PS_RESET Digital Input Digital Input without Schmitt trigger

Ordering Information

SLG7NT4503V V= S TQFN - 20 SLG7NT4503VTR VTR= S TQFN - 20 – Tape and Reel (3k units)

SLG7NT4503_DS_r10 1 SLG7NT4503 Absolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 150 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 13 00 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 3 3.3 3.6 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 1400 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2 - PIN10, PIN12 - PIN20) -- -- 90 mA V IH HIGH - Level Input Voltage Logic Input, at VDD=3.3V 1.78 -- VDD V V IL LOW - Level Input Voltage Logic Input, at VDD=3.3V -- -- 1.21 V I IH HIGH - Level Input Current Logic Input PINs; V IN = VDD - 1.0 -- 1.0 µA I IL LOW - Level Input Current Logic Input PINs; V IN = 0V - 1.0 -- 1.0 µA V OH HIGH - Level Output Voltage Push Pull, I OH = 3mA, 2X Driver, at VDD=3.3 V 2.87 3.21 -- V V OL LOW - Level Output Voltage Open Drain, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.080 0.147 V Push Pull, I OL = 3mA, 2X Driver, at VDD=3.3 V -- 0.060 0.108 I OH HIGH - Level Output Current Push Pull & PMOS OD, V OH = 2.4 V, 2X Driver, at VDD=3.3 V 11.522 24.16 -- mA I OL LOW - Level Output Current Push Pull, V OL =0.4V, 2X Driver, at VDD=3.3 V 9.750 16.488 -- mA Open Drain, V OL =0.4V, 1X Driver, at VDD=3.3 V 7.313 12.37 -- R PULL_UP Internal Pull Up Resistance Pull up on PINs 3, 4, 5, 6, 7 7 10 13 k Ω Pull up on PIN 13 70 100 130 R PULL_DOWN Internal Pull Down Resistance Pull down on PINs 10, 12, 14, 15, 16, 17, 20 700 1000 1300 k Ω T DLY0 Delay0 Time At temperature 25°C 4.86 5 5.16 s At temperature - 20°C +45°C (note 1) 4.59 5 5.85

SLG7NT4503_DS_r10 1 SLG7NT4503 T SU Start up Time From VDD rising past 1.6V -- 1 -- ms 1. Guaranteed by Design .

SLG7NT4503_DS_r10 1 SLG7NT4503 Functionality Waveforms D0 – PIN# 2 ( SC_PWRGD_ATX ) D1 – PIN# 10 ( Core_1V1_PWRGD ) D2 – PIN# 12 ( HPS_1V1_PWRGD ) D3 – PIN# 14 ( FPGA1V2_PWRGD ) D4 – PIN# 15 ( FPGA1V8/HPS1V5_PWRGD ) D5 – PIN# 16 ( FPGA2V5/HPS2V5_PWRGD ) D6 – PIN# 17 ( FPGA3V3/HPS3V3_PWRGD ) D7 – PIN# 20 ( FPGA_PS_RESET ) D8 – PIN# 3 ( CORE_1V1_EN/HPS_1V1_EN ) D9 – PI N# 4 ( FPGA_1V2_EN ) D10 – PIN# 5 ( FPGA1V8/HPS1V5_EN ) D11 – PIN# 6 ( FPGA2V5/HPS2V5_EN ) D12 – PIN# 7 ( FPGA3V3/HPS3V3_EN ) D13 – PIN# 13 ( HPS_POR_N ) D14 – PIN# 19 ( ALL_PWRGD ) D15 – PIN# 18 ( ERROR ) 1. Sequencer operation

SLG7NT4503_DS_r10 1 SLG7NT4503 2. Sequencer after latched reset state operation 3. Sequencer after reset signal on PIN20 (FPGA_PS_RESET) operation

SLG7NT4503_DS_r10 1 SLG7NT4503 Channel 1 ( yellow/top line) – PIN# 9 ( Soft Reset In ) Channel 2 ( light blue/2nd line) – PIN# 8 ( HPS_RST_N ) with external 5k Ω pull up resistor 4. PIN8 (HPS_RST_N) operation

SLG7NT4503_DS_r10 1 SLG7NT4503 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.0 1 002 L 4503V AA 02 /2 5 /20 22 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

SLG7NT4503_DS_r10 1 SLG7NT4503 Package Drawing and Dimensions

20 Lead S T Q FN Package

JEDEC MO - 220, Variation WECE IC Net Weight: 0.015 g

SLG7NT4503_DS_r10 1 SLG7NT4503 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch S T Q FN 20L 2 x3 mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W S T Q FN 20L 2 x3 mm 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). More information can be found at www.jedec.org .

SLG7NT4503_DS_r10 1 SLG7NT4503 Datasheet Revision History Date Version Change 08 / 18 /201 4 0.10 New design for SLG46722 08/26/2014 0.11 Removed inverter from HPS_POR_N output 08/27/2014 0.12 Corrected Block Diagram, switched to internal version style 09/19/2014 0.13 Updated Device Revision Table 10/06/2014 0.14 Updated Lock status 10/20/2014 1.0 Production Release 02/25/2022 1.01 Updated Company name and logo

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