SLG7NT4445VTR

SLG7NT4445V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 12

Technical content

Features

• Low Power Consumption
• Dynamic Voltage Supply Range
• RoHS Compliant / Halogen - Free
• Pb - Free TDFN - 12 Package
• MSL1 Pin Configuration TDFN - 12 TOP VIEW Thermal Pad connected to GND Output Summary
• 1 Output — Push Pull 1X
• 4 Outputs — Open Drain NMOS 1X VDD PWR_BTN_L BATT_ENABLE AC_PRESENT KSO_SW KSI_SW GND KSI KSO_INV EC_ENTERING_RW EC_IN_RW EC_RST_L SLG7NT4445 Renesas GreenPAK 2 SLG7NT4445 is a low power and small form device. The SoC is housed in a 2.5mm x 2.5mm TDFN package which is optimal for using with small devices.

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 2 Block Diagram

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 3 Pin Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 PWR_BTN_L Digital Input Digital Input with Schmitt trigger

3 BATT_ENABLE Digital Output Open Drain NMOS 1X

4 AC_PRESENT Digital Input Low Voltage Digital Input

5 KSO_SW Digital Output Open Drain NMOS 1X

6 KSI_SW Digital Input Digital Input with Schmitt trigger

7 GND GND Ground

8 KSI Digital Output Open Drain NMOS 1X

9 KSO_INV Digital Input Digital Input with Schmitt trigger

10 EC_ENTERING_RW Digital Input Digital Input with Schmitt trigger

11 EC_IN_RW Digital Output Open Drain NMOS 1X

12 EC_RST_L Bi - directional Digital Input withSchmitt trigger / Push

Bottom Pad Exposed Bottom Pad GND Ground

Ordering Information

SLG7NT4445V V = TDFN - 12 SLG7NT4445VTR VTR = TDFN - 12 - Tape and Reel (3k units)

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 4 A bsolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 150 °C Junction temperature -- 150 °C

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 1.71 -- 5.5 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 1 -- µ A I A Active Current Static inputs and outputs -- 15 -- µ A V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side -- -- 24 mA V IH HIGH - Level Low Voltage Input Voltage Logic Input with Schmitt Trigger, at VDD=1.8V 1.35 -- VDD V Low - Level Logic Input, at VDD=1.8V 1.1 -- VDD Logic Input with Schmitt Trigger, at VDD=3.3 V 2.3 -- VDD L ow - Level Logic Input, at VDD=3.3 V 1.5 -- VDD Logic Input with Schmitt Trigger, at VDD=5.0 V 3.2 -- VDD L ow - Level Logic Input, at VDD=5.0 V 1.7 -- VDD V IL LOW - Level Low Voltage Input Voltage Logic Input with Schmitt Trigger, at VDD=1.8V -- -- 0.45 V Low - Level Logic Input, at VDD=1.8V -- -- 0.50 Logic Input with Schmitt Trigger, at VDD=3.3 V -- -- 0.92 L ow - Level Logic Input, at VDD=3.3 V -- -- 0.66 Logic Input with Schmitt Trigger, at VDD=5.0 V -- -- 1.3

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 5 L ow - Level Logic Input, at VDD=5.0 V -- -- 0.77 I IH HIGH - Level Input Current Logic Input Pins; V IN = VDD - 1.0 -- 1.0 μA I IL LOW - Level Input Current Logic Input Pins; V IN = 0V - 1.0 -- 1.0 μA V O H HIGH - Level Output Voltage (note 1) Push Pull , I OH = 100u A, 1X Driver , at VDD=1.8 V 1.66 -- -- V Push Pull , I OH = 700u A, 1X Driver , at VDD=1.8 V 1.21 -- -- Push Pull , I OH = 3m A, 1 X Driver , at VDD=3.3 V 2.1 -- -- Push Pull , I OH = 5m A, 1 X Driver , at VDD=5.0 V 3.6 -- -- Push Pull , I OH = 8m A, 1 X Driver , at VDD=5.0 V 2.9 -- -- V OL LOW - Level Output Voltage (note 1) Push Pull , I OL = 100u A, 1X Driver , at VDD=1.8 V -- -- 0.040 V Push Pull , I OL = 700u A, 1X Driver , at VDD=1.8 V -- -- 0.415 Open Drain , I OL = 5m A, 1X Driver , at VDD=1.8 V -- -- 0.340 Push Pull , I OL = 3m A, 1 X Driver , at VDD=3.3 V -- -- 0.81 Open Drain , I OL = 20m A, 1X Driver , at VDD=3.3 V -- -- 0.605 Push Pull , I OL = 5m A, 1 X Driver , at VDD=5.0 V -- -- 0.85 Push Pull , I OL = 8m A, 1 X Driver , at VDD=5.0 V -- -- 1.2 Open Drain , I OL = 20m A, 1X Driver , at VDD=5.0 V -- -- 0.36 I OL LOW - Level Output Current (note 1) Push Pull , V OL = 0.15V , 1X Driver , at VDD=1.8 V 0.34 -- -- mA Open Drain , V OL = 0.15V , 1X Driver , at VDD=1.8 V 2.72 -- -- Push Pull , V OL = 0.4V , 1X Driver , at VDD=3.3 V 1.836 -- -- Open Drain , V OL = 0.4V , 1X Driver , at VDD=3.3 V 14.688 -- -- Push Pull , V OL = 0.4V , 1X Driver , at VDD=5.0 V 2.745 -- --

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 6 Open Drain , V OL = 0.4V , 1X Driver , at VDD=5.0 V 21.96 -- -- R PULL_UP Internal Pull Up Resistance Pull up on PINs 6, 12 35 50 65 k Ω R PULL_DOWN Internal Pull Down Resistance Pull down on PIN10 35 50 65 k Ω Pull down on PIN9 210 300 390 T DLY0 Delay0 Time At temperature 25 °C 4.13 5 5.88 ms T DLY1 Delay1 Time At temperature 25 °C 8.27 10 11.7 m s T DLY2 Delay2 Time At temperature 25 °C 5 -- 7.042 s T DLY 3 Delay 3 Time At temperature 25 °C 60 -- 127 µs T SU Start up Time After VDD reaches 1.6V level -- 7 -- ms 1. Guaranteed by Design .

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 7

Description

This device is a reset IC with one shot function , internal Latching system , level shifter and multiplexor . The reset (active LOW) occurs when both PWR_BTN _L ( PIN 2) and KSI_SW (PIN6) are LOW. PWR_BTN _L (PIN 2 ) has 5ms deglitch delay on its line. Also reset logics contains one more 100µs deglitch delay is u sed. The signal from this delay goes to 10ms one - shot system that creates 10ms LOW pulse on reset event. If PWR_BTN_L and KSI_SW are LOW , and AC_PRESENT (PIN4) transitions from HUGH to LOW , these three conditions will latch the BATT_ENABLE (PIN3) LOW for 5 second s minimum . During this EC_RST_L will be asserted and EC_IN_RW will go LOW as well. EC_RST _L is configured to be bidirectional , so it will operate as digital input with Schmitt trigger or as Low Level Digital Output . Also SLG 7NT4445 includes latching system. Its inputs are EC_RST _L and EC_ENTERING_RW . EC_IN_RW is an output configured as open drain. This system is initialized with logic HIGH on its output. It is latched LOW when EC_RST _L goes LOW until EC_ENTERING_RW goes HIGH. Multiplexing system in this device follow the logic: KSI = !( PWR_BTN_L ) | KSI_SW If the AC_PRESENT / BATTERY_ENABLE functionality is not needed, BATTERY_ENABLE can be left floating but AC_PRESENT should be tied low. All pins are in a high impedance state until the chip has powered up.

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 8 Timing Diagram

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 9 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.0 3 002 L 4445V AB 0 2 / 25 /20 2 2 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 10 Package Drawing and Dimensions

12 Lead TDFN Package

JEDEC MO - 252, Variation 2525E

Reset IC with Latch and MUX SLG7NT4445 SLG7NT4445_DS_r 10 3 Page 11 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch TDFN 12L 2.5x2.5mm 0.4P Green 12 2.5x2.5x0.75 3000 3000 178/60 42 168 42 168 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W TDFN 12L 2.5x2.5mm 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 4.6875 mm 3 (nominal). More information can be found at www.jedec.org .

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