SLG7NT4192V

SLG7NT4192V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 11

Technical content

Features

8 Outputs - Open Drain NMOS 1X

1 Output - Push Pull 1X

• Low Power Consumption
• Pb - Free / RoHS Compliant
• Halogen - Free
• STQFN - 20 Package Renesas SLG7NT4192 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices. VDD BC_ACOK_DSW DPWROK BC_ACOK_EC_IN SUS_VR_PWRGD PWRBTN_N VCCST_PWRGD PWRBTN_DSW_N GND SYS_PWROK PWRBTN_EC_IN VBAT_MON RSMRST_PWRGD_N V3.3A_DSW_PWRGD ALL_SYS_PWRGD DDR_VCCIO_PWRGD PCH_PWROK SLG7NT4192

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 Block Diagram

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 P in Configuration Pin # Pin Name Type Pin Description Internal Resistor

1 VDD PWR Supply Voltage --

2 BC_ACOK_DSW Digital Input Digital Input without Schmitt trigger floating

3 DPWROK Digital Output Push Pull 1X floating

4 BC_ACOK_EC_IN Digital Output Open Drain NMOS 1X floating

5 SUS_VR_PWRGD Digital Input Digital Input without Schmitt trigger floating

6 V1 Analog Input/Output Analog Input/Output floating

7 PWRBTN_N Digital Input Digital Input without Schmitt trigger floating

8 VCCST_PWRGD Digital Output Open Drain NMOS 1X floating

9 PWRBTN_DSW_N Digital Output Open Drain NMOS 1X floating

10 V2 Analog Input/Output Analog Input/Output floating

11 GND GND Ground --

12 SYS_PWROK Digital Output Open Drain NMOS 1X floating

13 V3 Analog Input/Output Analog Input/Output floating

14 PWRBTN_EC_IN Digital Output Open Drain NMOS 1X floating

15 VBAT_MON Analog Input/Output Analog Input/Output floating

16 RSMRST_PWRGD_N Digital Output Open Drain NMOS 1X floating

17 V3.3A_DSW_PWRGD Digital Input Digital Input without Schmitt trigger floating

18 ALL_SYS_PWRGD Digital Output Open Drain NMOS 1X floating

19 DDR_VCCIO_PWRGD Digital Input Digital Input without Schmitt trigger floating

20 PCH_PWROK Digital Output Open Drain NMOS 1X floating

Ordering Information

SLG7NT4192V V=STQFN - 20 SLG7NT4192VTR VTR=STQFN - 20 – Tape and Reel (3k units)

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 Absolute Maximum Conditions Parameter Min. Max. Unit Supply Voltage on VDD relative to GND - 0.5 7 V DC Input Voltage GND - 0.5V VDD + 0.5V V Maximum Average or DC Current (Through pin) Push - Pull 1x -- 8 mA OD 1x -- 8 Current at Input Pin - 1.0 1.0 mA Input leakage (Absolute Value) -- 1000 nA Storage Temperature Range - 65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1

Electrical Characteristics

Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 1.71 3.3 3.6 V T A Operating Temperature - 40 25 85 °C C VDD Capacitor Value at VDD -- 0.1 -- µF C IN Input Capacitance -- 4 -- pF I Q Quiescent Current Static inputs and floating outputs -- 85 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I VDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) I GND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) V IH HIGH - Level Input Voltage Logic Input at VDD=1.8V 1.1 -- -- V Logic Input at VDD=3.3V 1.78 -- -- V V IL LOW - Level Input Voltage Logic Input at VDD=1.8V -- -- 0.69 V Logic Input at VDD=3.3V -- -- 1.21 V V OH HIGH - Level Output Voltage Push - Pull 1X, I OH =100µA, at VDD=1.8V 1.69 1.789 -- V Push - Pull 1X, I OH =3mA, at VDD=3.3V 2.735 3.12 -- V V OL LOW - Level Output Voltage Push - Pull 1X, I OL =100µA, at VDD=1.8V -- 0.008 0.03 V Push - Pull 1X, I OL =3mA, at VDD=3.3V -- 0.13 0.228 V Open Drain NMOS 1X, I OL =100µA, at VDD=1.8V -- 0.005 0.02 V Open Drain NMOS 1X, I OL =3mA, at VDD=3.3V -- 0.08 0.147 V I OH HIGH - Level Output Current (see Note 1) Push - Pull 1X, V OH =VDD - 0.2V, at VDD=1.8V 1.066 1.703 -- mA

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 Push - Pull 1X, V OH =2.4V, at VDD=3.3V 6.045 12.08 -- mA I OL LOW - Level Output Current (see Note 1) Push - Pull 1X, V OL =0.15V, at VDD=1.8V 0.917 1.689 -- mA Push - Pull 1X, V OL =0.4V, at VDD=3.3V 4.875 8.244 -- mA Open Drain NMOS 1X, V OL =0.15V, at VDD=1.8V 1.375 2.534 -- mA Open Drain NMOS 1X, V OL =0.4V, at VDD=3.3V 7.313 12.37 -- mA T DLY0 Delay0 Time At temperature 25°C 2.24 2.50 2.75 ms At temperature - 40 +85°C (Note 3) 2.14 2.50 3.33 ms T DLY1 Delay1 Time At temperature 25°C 2.24 2.50 2.75 ms At temperature - 40 +85°C (Note 3) 2.14 2.50 3.33 ms T DLY4 Delay4 Time At temperature 25°C 1.82 2.00 2.24 ms At temperature - 40 +85°C (Note 3) 1.73 2.00 2.71 ms T DLY5 Delay5 Time At temperature 25°C 8.96 10.00 10.75 ms At temperature - 40 +85°C (Note 3) 8.54 10.00 13.03 ms V ACMP0 Analog Comparator0 Threshold Voltage Low to High transition, at temperature 25°C -- 950 988 mV Low to High transition, at temperature - 40 +85°C (Note 3) -- 950 1009 mV High to Low transition, at temperature 25°C 911 950 -- mV High to Low transition, at temperature - 40 +85°C (Note 3) 871 950 -- mV V ACMP1 Analog Comparator1 Threshold Voltage Low to High transition, at temperature 25°C -- 950 988 mV Low to High transition, at temperature - 40 +85°C (Note 3) -- 950 1009 mV High to Low transition, at temperature 25°C 911 950 -- mV High to Low transition, at temperature - 40 +85°C (Note 3) 871 950 -- mV V ACMP2 Analog Comparator2 Threshold Voltage Low to High transition, at temperature 25°C -- 950 988 mV Low to High transition, at temperature - 40 +85°C (Note 3) -- 950 1009 mV High to Low transition, at temperature 25°C 911 950 -- mV High to Low transition, at temperature - 40 +85°C (Note 3) 871 950 -- mV

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 V ACMP3 Analog Comparator3 Threshold Voltage Low to High transition, at temperature 25°C -- 950 988 mV Low to High transition, at temperature - 40 +85°C (Note 3) -- 950 1009 mV High to Low transition, at temperature 25°C 911 950 -- mV High to Low transition, at temperature - 40 +85°C (Note 3) 871 950 -- mV V HYST Analog Comparator Hysteresis Voltage(Note 3) ACMP 0 at temperature 25°C -- 50 -- mV ACMP 0 at temperature ACMP 1 at temperature 25°C -- 50 -- mV ACMP 1 at temperature ACMP 2 at temperature 25°C -- 50 -- mV ACMP 2 at temperature ACMP 3 at temperature 25°C -- 50 -- mV ACMP 3 at temperature T SU Startup Time from VDD rising past 1.35 V -- 0.3 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.18 1.353 1.516 V POFF THR Power Off Threshold V DD Level Required to Switch Off the Chip 0.73 0.914 1.103 V Note: 1. DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. 2. The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6 , 7, 8, 9 and 10 are connected to one side, pins 12, 13, 14, 15, 16, 17, 18, 19 and 20 to another. 3. Guaranteed by Design.

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 Package Top Marking Datasheet Revision Programming Code Number Lock Status Checksum Part Code Revision Date 1.0 6 004 L 0x47C472BA 4192V AD 0 2 / 2 5 /202 2 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 Package Drawing and Dimensions

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 Tape and Reel Specification Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 20L 2x3mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 20L 2x3mm 0.4P Green Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). More information can be found at www.jedec.org.

Power Good Generator Logic SLG7NT4192_DS_r10 6 SLG7NT4192 Recommended Land Pattern

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