SLG7NT41021V

SLG7NT41021V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 8

Technical content

Features

• Low Power Consumption
• Pb - Free / RoHS Compliant
• Halogen - Free
• S T QFN - 20 Package Output Summary
• 4 Outputs — Push Pull 1X
• 5 Outputs — Open Drain NMOS 1X
• 1 Output — 3 - State 1X Pin Configuration 11 8 9 10 20 19 18 S T Q FN - 20 TOP VIEW VDD SLG7NT41021 GND VDDQ_PWRGD SLP_S3_N NFET_V5DUAL_USB_N DDR_NMOS_Q3 V5S_MON PFET_V5DUAL_USB PS1_OUT SLP_S4_N +V5_V12_DDR SUS_WARN_N PS1 SUS_ACK_N V12S_MON PFET_5VDUAL_DDR NFET_5VDUAL_DDR_ N V5S_PWRGD DDR_PMOS_Q2 DDR_PMOS_Q1 Renesas SLG7NT41021 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices.

DDR Sequencer and FET Driver SLG7NT41021_DS_r10 6 SLG7NT41021 P in Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 VDDQ_PWRGD Digital Input Digital Input without Schmitt trigger

3 SLP_S3_N Digital Input Digital Input without Schmitt trigger

4 NFET_V5DUAL_USB_N Digital Output Open Drain NMOS 1X

5 DDR_NMOS_Q3 Digital Output Push Pull 1X

6 V5S_MON Analog Input/Output Analog Input/Output

7 PFET_V5DUAL_USB Digital Output Open Drain NMOS 1X

8 PS1_OUT Digital Output Open Drain NMOS 1X

9 SLP_S4_N Digital Input Digital Input without Schmitt trigger

10 +V5_V12_DDR Analog Input/Output Analog Input/Output

11 GND GND Ground

12 SUS_WARN_N Digital Input Digital Input without Schmitt trigger

13 PS1 Digital Input Digital Input without Schmitt trigger

14 SUS_ACK_N Digital Output Open Drain NMOS 1X

15 V12S_MON Analog Input/Output Analog Input/Output

16 DDR_PMOS_Q2 Digital Output Push Pull 1X

17 DDR_PMOS_Q1 Digital Output Push Pull 1X

18 PFET_5VDUAL_DDR Digital Output 3 - State Output 1X

19 NFET_5VDUAL_DDR_N Digital Output Push Pull 1X

20 V5S_PWRGD Digital Output Open Drain NMOS 1X

Ordering Information

SLG7NT41021V V= S TQFN - 20 SLG7NT41021VTR VTR= S TQFN - 20 – Tape and Reel (3k units)

DDR Sequencer and FET Driver SLG7NT41021_DS_r10 6 SLG7NT41021 Absolute Maximum Conditions Parameter Min. Max. Unit V HIGH to GND - 0.3 7 V Voltage at input pins - 0.3 7 V Current at input pin - 1.0 1.0 mA Storage temperature range - 65 125 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 13 00 -- V Moisture Sensitivity Level 1

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 1.71 3.3 5.5 V T A Operating Temperature - 40 25 85 °C I Q Quiescent Current Static inputs and outputs -- 90 -- µA V O Maximal Voltage Applied to any PIN in High - Impedance State -- -- VDD V I O Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2 - PIN10, PIN12 - PIN20) -- -- 90 mA V IH HIGH - Level Input Voltage Logic Input, at VDD=1.8V 1.10 -- VDD V Logic Input, at VDD=3.3V 1.78 -- VDD Logic Input, at VDD=5.0V 2.64 -- VDD V IL LOW - Level Input Voltage Logic Input, at VDD=1.8V -- -- 0.69 V Logic Input, at VDD=3.3V -- -- 1.21 Logic Input, at VDD=5.0V -- -- 1.84 I IH HIGH - Level Input Current Logic Input PINs; V IN = VDD - 1.0 -- 1.0 µA I IL LOW - Level Input Current Logic Input PINs; V IN = 0V - 1.0 -- 1.0 µA V OH HIGH - Level Output Voltage Push Pull & PMOS OD, I OH = 100uA, 1X Driver, at VDD=1.8 V 1.69 1.789 -- V Push Pull & PMOS OD, I OH = 3mA, 1X Driver, at VDD=3.3 V 2.735 3.12 -- Push Pull & PMOS OD, I OH = 5mA, 1X Driver, at VDD=5.0 V 4.19 4.78 -- V OL LOW - Level Output Voltage Push Pull, I OL = 100uA, 1X Driver, at VDD=1.8 V -- 0.008 0.03 V Open Drain, I OL = 100uA, 1X Driver, at VDD=1.8 V -- 0.005 0.020 Push Pull, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.13 0.228 Open Drain, I OL = 3mA, 1X Driver, at VDD=3.3 V -- 0.080 0.147

DDR Sequencer and FET Driver SLG7NT41021_DS_r10 6 SLG7NT41021 Push Pull, I OL = 5mA, 1X Driver, at VDD=5.0 V -- 0.157 0.270 Open Drain, I OL = 5mA, 1X Driver, at VDD=5.0 V -- 0.102 0.180 I OH HIGH - Level Output Current Push Pull & PMOS OD, V OH = V DD - 0.2, 1X Driver, at VDD=1.8 V 1.066 1.703 -- mA Push Pull & PMOS OD, V OH = 2.4 V, 1X Driver, at VDD=3.3 V 6.045 12.08 -- Push Pull & PMOS OD, V OH = 2.4 V, 1X Driver, at VDD=5.0 V 22.08 34.04 -- I OL LOW - Level Output Current Push Pull, V OL =0.15V, 1X Driver, at VDD=1.8 V 0.917 1.689 -- mA Open Drain, V OL =0.15V, 1X Driver, at VDD=1.8 V 1.375 2.534 -- Push Pull, V OL =0.4V, 1X Driver, at VDD=3.3 V 4.875 8.244 -- Open Drain, V OL =0.4V, 1X Driver, at VDD=3.3 V 7.313 12.37 -- Push Pull, V OL =0.4V, 1X Driver, at VDD=5.0 V 7.215 11.58 -- Open Drain, V OL =0.4V, 1X Driver, at VDD=5.0 V 10.82 17.38 -- V ACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 934 -- 965 mV ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40°C +85°C (note 1) 886 -- 994 V ACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 984 -- 1016 mV ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40°C +85°C (note 1) 933 -- 1046 V ACMP3 Analog Comparator Threshold Voltage ACMP3 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 934 -- 965 mV ACMP3 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40°C +85°C (note 1) 886 -- 994 T DLY1 Delay1 Time At temperature 25°C 108.37 140 167.13 µs At temperature - 40°C +85°C (note 1) 98.18 140 197.87 T SU Start up Time From VDD rising past 1.35 V -- 0.3 -- ms 1. Guaranteed by Design.

DDR Sequencer and FET Driver SLG7NT41021_DS_r10 6 SLG7NT41021 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.0 6 006 L 41021 AC 0 2 / 25 /20 22 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking .

DDR Sequencer and FET Driver SLG7NT41021_DS_r10 6 SLG7NT41021 Package Drawing and Dimensions

20 Lead S T Q FN Package

JEDEC MO - 220, Variation WECE IC Net Weight: 0.015 g

DDR Sequencer and FET Driver SLG7NT41021_DS_r10 6 SLG7NT41021 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch S T Q FN 20L 2 x3 mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W S T Q FN 20L 2 x3 mm 0.4P Green Refer to EIA - 481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J - STD - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). More information can be found at www.jedec.org .

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