SLG7NT408V

SLG7NT408V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 12

Technical content

Features

• 1.5 x 2.0 mm FC-TDFN 8L package (2 fused pins for drain and 2 fused pins for source)
• Logic level ON pin capable of supporting 0.85 V CM OS Logic
• User selectable ramp rate with external capacitor
• 7.8 m Ω RDS ON while supporting 4 A
• Two Over Current Protection Modes
• Short Circuit Current Limit
• Active Current Limit
• Over Temperature Protection
• Pb-Free / Halogen-Free / RoHS compliant
• Operating Temperature: -20 °C to 70 °C
• Operating Voltage: 2.5 V to 5.5 V Pin Configuration

Applications

• Notebook Power Rail Switching
• Tablet Power Rail Switching
• Smartphone Power Rail Switching 8-pin FC-TDFN (Top View) VDD 1 CAP GND D ON 2 SLG7NT408V D 4 S S D S Linear Ramp Control CMOS Input ON Charge Pump +2.5 to 5.5 V CAP 4 A @ 7.8 m Ω Over Current and Over Temperature Protection

000-007NT408-102 Page 2 of 11 SLG7NT408V Pin Description

Ordering Information

Pin # Pin Name Type Pin Description 1 VDD PWR VDD power for load switch control (2.5 V to 5.5 V)

2 ON Input Turns MOSFET ON (4 M Ω pull down resistor)

CMOS input with VIL < 0.3 V, VIH > 0.85 V

3 D MOSFET Drain of Power MOSFET (fused with pin 4)

4 D MOSFET Drain of Power MOSFET (fused with pin 3)

5 S MOSFET Source of Power MOSFET (fused with pin 6)

6 S MOSFET Source of Power MOSFET (fused with pin 5)

7 CAP Input Capacitor for controlling power rail ramp rate

8 GND GND Ground

Part Number Type Production Flow SLG7NT408V FC-TDFN 8L Commercial, -20 °C to 70 °C SLG7NT408VTR FC-TDFN 8L (Tape and Reel) Commercial, - 20 °C to 70 °C

000-007NT408-102 Page 3 of 11 SLG7NT408V Absolute Maximum Ratings

Electrical Characteristics

Parameter Description Conditions Min. Typ. Max. Unit VDD Power Supply -- -- 7 V TS Storage Temperature -65 -- 150 °C ESD HBM ESD Protection Human Body Model 2000 -- -- V MOSFET IDS PK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle -- -- 6 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at thes e or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TA = -20 to 70 °C (unless otherwise stated) Parameter Description Conditions Min. Typ. Max. Unit VDD Power Supply Voltage -20 to 70°C 2.5 -- 5.5 V IDD Power Supply Current (PIN 1) when OFF -- -- 1 µA when ON, No load -- 70 100 µA RDS ON Static Drain to Source ON Resistance T A 25°C @ 100 mA -- 7.8 8.5 m Ω TA 70°C @ 100 mA -- 8.5 9.6 m Ω IDS Operating Current V D = 1.0 V to 5.5 V -- -- 4 A VD Drain Voltage 0.85 -- V DD V TON_Delay ON pin Delay Time 50% ON to Ramp Begin, R L = 20 Ω, CL= 10 µF 0 300 500 µs TTotal_ON Total Turn On Time 50% ON to 90% V S Configurable 1 ms Example: CAP (PIN 7) = 4 nF, V DD = VD = 5 V, Source_Cap = 10 µF, RL = 20 Ω -- 1.96 -- ms TSLEWRATE Slew Rate 10% V S to 90% V S Configurable 1 V/ms Example: CAP (PIN 7) = 4 nF, V DD = VD = 5 V, Source_Cap = 10 µF, RL = 20 Ω -- 3.0 -- V/ms CAP SOURCE Source Cap Source to GND -- -- 500 µF ON_V IH High Input Voltage on ON pin 0.85 -- V DD V ON_V IL Low Input Voltage on ON pin -0.3 0 0.3 V ILIMIT Active Current Limit MOSFET will automatically limit cur - rent when VS > 250 mV -- 6.0 -- A Short Circuit Current Limit MOSFET will automatically limit cur - rent when VS < 250 mV -- -- 0.5 A THERM ON Thermal shutoff turn-on temperature -- 125 -- °C THERM OFF Thermal shutoff turn-off temperature -- 100 -- °C THERM TIME Thermal shutoff time -- -- 1 ms TOFF_Delay OFF Delay Time 50% ON to V S Fall, V DD = V D = 5 V, RL = 20 Ω , no C L -- -- 15 µs TFALL VS Fall Time 90% V S to 10% V S, V DD = V D = 5 V, RL = 20 Ω , no C L -- TBD -- µs Notes: 1. Refer to table for configuration details.

000-007NT408-102 Page 4 of 11 SLG7NT408V SLG7NT408V Turn ON The normal power on sequence is first V DD , with V D only being applied after V DD is > 1 V, and then ON after V D is at least 90% of final value. The normal power off sequence is the power on sequence in reverse. If V DD and V D are turned on at the same time then it is possible that a voltage glitch will appear on V S before V DD achieves 1 V which is the V T of the main MOSFET. The size of the glitch is dependent on source and drain capacitance loading and the ramp rate of V DD & V D. SLG7NT408V Turn ON The V S ramp follows a linear path, not an RC limitation p rovided the ramp is slow enough to not be current l imited by load capacitance. SLG7NT408V Current Limiting The SLG7NT408V has two forms of current limiting. Standard Current Limiting Mode Current is measured by mirroring the current throug h the main MOSFET. The mirrored current is then sen t through a resistor creating a voltage V(i) proportional to the MOSFET current. The V(i) is then compared with a Band Gap voltage V(BG). If V(i) exceeds the Band Gap voltage then the voltage V(g) on the gate of the main MOSFET is reduced. The V(g) continues to drop until V(i) < V(BG). This response is a closed loop response and is therefore very fast and current lim its in less than a few micro-seconds. There is no difference between peak or constant current limit. Temperature Cutoff However, as the V(g) drops the Rds(ON) of the main MOSFET will increase, thus limiting the current, bu t also increasing the power dissipation of the IC. The IC is very small a nd cannot dissipate much power. Therefore, if a cur rent limit condition is sustained the IC will heat up. If the temperature exceeds approximately 120 °C, then V(g) will be brought low completely shutting off the main MOSFET. As the die cools the MOSFET will be turned back on at 100 °C. If the current limiting condition has not been mitigated then the die will again heat up to 120 °C and the process will repeat. Short Circuit Current Limiting Mode When V(S) < 250 mV, which is the case if there is a solder bridge during the manufacturing process or a hard short on the power rail, then the current is limited to approximately 500 mA. This current limit is accomplished in the same manner as the Standard Current Limiting Mode with the exception that the c urrent mirror is 15x greater. Because the current m irror is so much larger, a 15x smaller main MOSFET current is required to gene rate the same V(i). If V(S) rises above approximate ly 250 mV, then this mode is automatically switched out.

000-007NT408-102 Page 5 of 11 SLG7NT408V TTotal_ON vs. CAP @ V DD = 3.3 V TTotal_ON vs. CAP @ V DD = 5.0 V SLG7NT408V T Total_ON : ON (50%) - V S (90%) VDD = 3.3 V, T A = 25 °C. C L = 10 µF, IDS = 100 mA SLG7NT408V T Total_ON : ON (50%) - V S (90%) VDD = 5.0 V, T A = 25 °C. C L = 10 µF, IDS = 100 mA Ttotal_on (ms) VD = 1.5V VD = 2.5V VD = 3.3V 0 2000 4000 6000 8000 10000 12000 14000 16000 Cap (pf) Ttotal_on (ms) VD = 1.50V VD = 2.50V VD = 3.30V VD = 5.00V 0 2000 4000 6000 8000 10000 12000 14000 16000 Cap (pf)

000-007NT408-102 Page 6 of 11 SLG7NT408V TSLEW vs. CAP @ V DD = 3.3 V TSLEW vs. CAP @ V DD = 5.0 V SLG7NT408V T SLEW : V S (10%) - V S (90%) VDD = 3.3 V, T A = 25 °C. C L = 10 µF, IDS = 100 mA SLG7NT408V T SLEW : V S (10%) - V S (90%) VDD = 5.0 V, T A = 25 °C. C L = 10 µF, IDS = 100 mA V/ms VD = 1.50V VD = 2.50V VD = 3.30V 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 1200 0 13000 14000 15000 16000 Cap (pf) V/ms VD = 1.50V VD = 2.50V VD = 3.30V VD = 5.00V 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 1200 0 13000 14000 15000 16000 Cap (pf)

000-007NT408-102 Page 7 of 11 SLG7NT408V TTotal_ON , T ON_Delay and Slew Rate Measurement 90% V S 50% ON TON_DELAY Slew Rate (V/ms) ON VS TTotal_ON 10% V S 50% ON 10% V S TOFF_DELAY TFALL 90% V S

000-007NT408-102 Page 8 of 11 SLG7NT408V Package Top Marking System Definition XXA DDR LL Date Code + Revision Part Code + Assembly Site Lot Traceability Pin 1 Identifier

000-007NT408-102 Page 9 of 11 SLG7NT408V Package Drawing and Dimensions 8 Lead TDFN Package 1.5 x 2.0 mm (Fused Lead) JEDEC MO-252, Variation W2015D Approved: Symbol A b D E L S Symbol Min Nom. Max Unit: mm Min Nom. Max 0.70 0.75 0.80 1.95 2.00 2.05 0.005 - 0.060 1.45 1.50 1.55 0.15 0.20 0.25 0.35 0.40 0.45 0.515 0.565 0.615 0.15 0.20 0.25 A Index Area (D/2 x E/2) L e D E 0.135 0.185 0.235 e 0.50 BSC S

0.37 REF

b (8X)

000-007NT408-102 Page 10 of 11 SLG7NT408V Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.25 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 8L FC Green 8 1.5 x 2.0 x 0.75 3000 3000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 8L W EP0 Y Y Section Y-Y CL F Refer to EIA-481 specification

000-007NT408-102 Page 11 of 11 SLG7NT408V

Revision History

2/252022 1.02 Updated Company name and logo Fixed typos 9/9/2015 1.01 Updated Vd min = 0.85 V Updated Conditions in Electrical Characteristics Table

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