SLG7NT402V

SLG7NT402V RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 16

Technical content

Features

• 1.5 x 2.0 mm FC-TDFN 8L package (2 fused pins for drain and 2 fused pins for source)
• Logic level ON pin capable of supporting 0.85 V CMOS Logic
• User selectable ramp rate with external capacitor
• 8.5 mΩ RDSON while supporting 4 A
• Discharges load when off
• Two Over Current Protection Modes
• Short Circuit Current Limit
• Active Current Limit
• Over Temperat ure Protection
• Pb-Free / Halogen-Free / RoHS compliant
• Operating Temperature: -40 C to 85C
• Operating Voltage : 2.5 V to 5.5 V Pin Configuration

Applications

• Notebook Power Rail Switching
• Tablet Power Rail Switching
• Smartphone Power Rail Switching 8-pin FC-TDFN (Top View) VDD 1 CAP GND D ON 2 SLG7NT402V D 4 S S D S Linear Ramp Control CMOS Input 0.85 to 5.5 V ON Charge Pump VDD +2.5 V to 5.5 V CAP 4 A @ 8.5 mΩ Over Current and Over Temperature Protection CLOADCIN GND CSLEW 4 nF

Revision 1.15 Page 2 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch Pin Description

Ordering Information

Pin # Pin Name Type Pin Description 1V D DP W R VDD supplies the power for the operation of the power switch and internal control circuitry. Bypass the VDD pin to GND with a 0.1 µF (or larger) capacitor.

2 ON Input

A low-to-high transition on this pin initiates the operation of the SLG7NT402V’s state machine. ON is a CMOS input with ON_VIL < 0.3 V and ON_VIH > 0.85 V thresholds. While there is an internal pull-down circuit to GND (~4 MΩ), connect this pin directly to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller. 3, 4 D MOSFET Drain terminal connection of the n-channel MOSFET (2 pins fused for VD). Connect at least a low-ESR 0.1 µF capacitor from this pin to ground. Capacitors used at VD should be rated at 10 V or higher. 5, 6 S MOSFET Source terminal connection of the n-channel MOSFET (2 pins fused for VS). Connect a low-ESR capacitor from this pin to ground and consult the Electrical Characteristics table for recommended CLOAD range. Capacitors used at VS should be rated at 10 V or higher.

7 CAP Input

A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the VS slew rate and overall turn-on time of the SLG7NT402V. For best performance CSLEW value should be ≥ 1.5 nF and voltage level should be rated at 10 V or higher. 8 GND GND Ground connection. Connec t this pin to system analog or power ground plane. Part Number Type Production Flow SLG7NT402V FC-TDFN 8L Industrial, -40 C to 85C SLG7NT402VTR FC-TDFN 8L (Tape and Reel) Industrial, -40 C to 85 C

Revision 1.15 Page 3 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch Absolute Maximum Ratings Parameter Description Conditions Min. Typ. Max. Unit VDD Power Supply -- -- 7 V VD to GND Power Switch Input Voltage to GND -0.3 -- V DD V VS to GND Power Switch Output Voltage to GND -0.3 -- V D V ON and CAP to GND ON and CAP Pin Voltages to GND -0.3 -- V DD V TS Storage Temperature -65 -- 150 °C ESDHBM ESD Protection Human Body Model 2000 -- -- V ESDCDM ESD Protection Charged Device Model 1000 -- -- V MSL Moisture Sensitivity Level 1 JA Thermal Resistance 1.5 x 2mm, 8L TDFN; Determined using 1 in2, 1 oz. copper pads under each VD and VS terminals and FR4 pcb material -- 85 -- °C/W MOSFET IDSPK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle -- -- 6 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of t he device at these or any oth er conditions above those indica ted in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Electrical Characteristics

TA = -40 °C to 85 °C unless otherwise noted. Parameter Description Conditions Min. Typ. Max. Unit VDD Power Supply Voltage -40 °C to 85 °C 2.5 -- 5.5 V IDD Power Supply Current (PIN 1) when OFF -- -- 1 μA when ON, No load -- 70 105 μA RDSON ON Resistance TA 25°C, IDS = 100 mA -- 8.5 10.3 mΩ TA 85°C, IDS = 100 mA -- 10 12 mΩ MOSFET IDS Current from VD to VS Continuous -- -- 4 A VD Drain Voltage 0.85 -- V DD V IFET_OFF MOSFET OFF Leakage Current 2.5 V ≤ VDD ≤ 5.5 V; VS = 0 V; ON = LOW; TA = 25°C -- -- 1 μA TON_Delay ON Delay Time 50% ON to V S Ramp Start -- 300 500 μs TTotal_ON Total Turn On Time 50% ON to 90% VS Set by External CSLEW 1 ms Example: CSLEW = 4 nF, VDD = VD = 5 V, CLOAD = 10 μF, RLOAD = 20 Ω -- 1.8 -- ms VS(SR) Slew Rate 10% VS to 90% VS Set by External CSLEW

1 V/ms

Example: CSLEW = 4 nF, VDD = VD = 5 V, CLOAD = 10 μF, RLOAD = 20 Ω -- 3.0 -- V/ms CLOAD Output Load Capacitance C LOAD connected from VS to GND -- 10 500 μF RDISCHRGE Discharge Resistance 100 200 300 Ω

Revision 1.15 Page 4 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch TON_Delay, VS(SR), and TTotal_ON Timing Details ON_VIH High Input Voltage on ON pin 0.85 -- V DD V ON_VIL Low Input Voltage on ON pin -0.3 0 0.3 V ILIMIT Active Current Limit, IACL MOSFET will automatically limit current when VS > 250 mV -- 6.0 -- A Short Circuit Current Limit, ISCL MOSFET will automatically limit current when VS < 250 mV -- 0.5 -- A THERMON Thermal shutoff turn-on temperature -- 125 -- °C THERMOFF Thermal shutoff turn-off temperature -- 100 -- °C THERMTIME Thermal shutoff time -- -- 1 ms TOFF_Delay OFF Delay Time 50% ON to VS Fall Start, VDD = VD = 5 V, RLOAD = 20 Ω, no CLOAD -- -- 32 μs Notes: 1. Refer to typical timing parameter vs. CSLEW performance charts for additional information when available. Electrical Characteristics (continued) TA = -40 °C to 85 °C unless otherwise noted. Parameter Description Conditions Min. Typ. Max. Unit 90% VS 50% ON TON_Delay VS(SR) (V/ms) ON* VS TTotal_ON 10% VS 50% ON 10% VS TOFF_Delay TFALL 90% VS Note: * Rise and Fall times of the ON signal are 100 ns

Revision 1.15 Page 5 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch Typical Performance Characteristics TTotal_ON vs CSLEW, VD, VDD, and Temperature RDSON vs. Temperature, VDD, and VIN

Revision 1.15 Page 6 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch VS Slew Rate vs. CSLEW, VDD, and Temperature

Revision 1.15 Page 7 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch SLG7NT402V Power-Up/Power-Down Sequence Considerations To ensure glitch-free power-up under all conditions, apply VDD first, followed by VD after VDD exceeds 1 V. Then allow VD to reach 90% of its max value before toggling the ON pin from Low-to-High. Likewise, power-down in reverse order. If VDD and VD need to be powered up simultaneously, glitching can be minimiz ed by having a suitable load capacitor. A 10 F CLOAD will prevent glitches for rise times of VDD and VD less than 2 ms. If the ON pin is toggled HIGH before VDD and VD have reached their steady-state values, the IPS timing parameters may differ from datasheet specifications. The slew rate of output VS follows a linear ramp set by a capacitor connected to the CAP pin. A larger capacitor value at the CAP pin produces a slower ramp, reducing inrush current from capacitive loads. SLG7NT402V Current Limiting Operation The SLG7NT402V has two types of current limiting triggered by the output VS pin voltage. 1. Standard Current Limiting Mode (with Thermal Shutdown Protection) When the VS pin voltage > 250 mV, the output current is initially limited to the Active Current Limit (IACL) specification listed in the Electrical Characteristics table. The ACL monitor’s response time is very fast and is triggered within a few microseconds to sudden (transient) changes in load current. When a load current overload is detected, the ACL monitor increases the FET resistance to keep the current from exceeding the power switch’s IACL threshold. However, if a load-current overload condition persists where the die temperature rises because of the increased FET resistance, the power switch’s internal Thermal Shutdown Protection circuit can be activated. If the die temperature exceeds the listed THERMON specification, the FET is shut OFF completely, thereby allowing the die to cool. When the die cools to the listed THERMOFF temperature threshold, the FET is allowed to turn back on. Thi s process may repeat as long as the output current overload condition persists. 2. Short Circuit Current Limiting Mode (with Thermal Shutdown Protection) When the VS pin voltage < 250 mV (which is the case with a hard short, suc h as a solder bridge on the power rail), the power switch’s internal Short-circuit Current Limit (SCL) monitor lim its the FET current to approximately 500 mA (the I SCL threshold). While the internal Thermal Shutdown Protection circuit remains enabled and since the ISCL threshold is much lower than the IACL threshold, thermal shutdown protection may become activated only at higher ambient temperatures.

Revision 1.15 Page 8 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch Power Dissipation The junction temperature of the SLG7NT402V depends on different factors such as board layout, ambient temperature, and other environmental factors. The prim ary contributor to the increase in the junction temperature of the SLG7NT402V is the power dissipation of its power MOSFET. Its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: where: PD = Power dissipation, in Watts (W) RDSON = Power MOSFET ON resistance, in Ohms (Ω) IDS = Output current, in Amps (A) and where: T J = Junction temperature, in Celsius degrees (°C) ΘJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) TA = Ambient temperature, in Celsius degrees (°C) During active current-limit operation, the SLG7NT402V’s power dissipation can be calculated by taking into account the voltage drop across the power switch (VD - VS) and the magnitude of the output current in active current-limit operation (IACL): where: PD = Power dissipation, in Watts (W) VD = Input Voltage, in Volts (V) RLOAD = Load Resistance, in Ohms (Ω) IACL = Output limited current, in Amps (A) VS = RLOAD x IACL For more information on Dialog GreenFET3 integrated power switc h features, please visit our Documents search page at our website and see App Note “AN-1068 GreenFET3 Integrated Power Switch Basics”. PD = RDSON x IDS TJ = PD x ΘJA + TA PD = (VD - VS) x IACL or PD = (VD – (RLOAD x IACL)) x IACL

close as possible to the SLG7NT402V's PIN1.

1. The GND pin should be connected to system analog or power ground plane.

Figure 1. SLG7NT402V Evaluation Board.

Figure 2. SLG7NT402V Evaluation Board Connection Circuit.

1. Connect oscilloscope probes to D/VIN, S/VOUT, ON, etc.;

4.Toggle the ON signal High or Low to observe SLG7NT402V operation. Figure 3. Typical connections for GFET3 Evaluation.

Revision 1.15 Page 12 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch Package Top Marking System Definition XXA Date Code + Revision Part Code + Assembly Site Lot TraceabilityPin 1 Identifier XX - Part Code Field1 A - Assembly Site Code Field2 DD - Date Code Field1 R - Part Revision Code Field2 LL - Lot Traceability Field1 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z DDR LL

Revision 1.15 Page 13 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch Package Drawing and Dimensions 8 Lead TDFN Package 1.5 x 2.0 mm (Fused Lead) JEDEC MO-252 Symbol A b D E L S SymbolMin Nom. Max Unit: mm Min Nom. Max 0.70 0.75 0.80 1.95 2.00 2.05 0.005 - 0.060 1.45 1.50 1.55 0.15 0.20 0.25 0.35 0.40 0.45 0.515 0.565 0.615 0.15 0.20 0.25 A I n d e xA r e a( D / 2xE / 2 ) L e D E 0.135 0.185 0.235 e 0.50 BSC S

0.37 REF

b (8X)

Revision 1.15 Page 14 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow prof ile based on package volume of 2.25 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 8L FC Green 8 1.5 x 2.0 x 0.75 3000 3000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Cen- ter Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 8L W EP0 Y Y Section Y-Y CL F Refer to EIA-481 specification

Revision 1.15 Page 15 of 15 © 2018 Dialog Semiconductor SLG7NT402V An Ultra-small 3 mm2, 8.5 mΩ, 4 A, Internally-protected Integrated Power Switch

Revision History

11/5/2018 1.15 Updated Style and Formatting 11/30/2015 1.14 Added MSL information 9/18/2015 1.13 Updated Package Marking Information 9/9/2015 1.12 Updated Abs Max Ratings with ESD for Machine Model Updated Conditions in Electrical Characteristics Table

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