SLG59H1313C

SLG59H1313C RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pwong
• PDF pages: 31

Technical content

Features

• Pin-to-pin to FPF2280 with Improved Performance
• Surge protection (IEC61000-4-5: >100 V)
• Input maximum voltage rating: 29 Vdc
• Integrated low RDS ON nFET switch: 23 mΩ (typ)
• 4.5 A continuous current capability
• Over-Voltage Protection (OVP): adjustable 4 V to 2 0 V
• Over-Temperature Protection (OTP): 145°C (typ)
• 7 A Over-Current Protection (OCP)
• Fast OVP turn-off response: typical 50 ns
• 1.3 mm x 1.8 mm in 12-ball WLCSP
• Pb-Free/Halogen-Free /ROHS Compliant Pin Configuration

Applications

• Wearable Devices
• Tablet PCs and Smartphones ON PG OVLO OUT OUT IN OUT IN IN GND GND GND C B A (Laser Marking View) 1.3 x 1.8 x 0.5 mm, 0.4 mm pitch Pin A1 Index Mark Charge Pump + Gate Driver + Bandgap + Logic IN TVS OVP OVLO ON GND 23 mΩ Closed Open Multiple Contacts Multiple Contacts VOUT VIN PG OUT OTP OCP ≥ 1 MΩ VPU RPU CLOAD ≥ 0.47 µF CIN ≥ 0.57 µF

Revision 1.07 Page 2 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Pin Description

Ordering Information

Pin Name Pin # Type Pin Description IN B3, C2, C3 Input IC power supply and load switch input (3 contacts). Bypass the IN pin to GND with a 0.57 µF (or larger) capacitor. Capacitors used at the IN pin should be rated at 30 V or higher. OUT A2, A3, B2 Output Load switch output to Load (3 contacts). Connect a low-ESR capacitor from the OUT pin to ground and follow the C LOAD recommendation in the Electrical Characteristics section. Capacitors used at the OUT pin should be rated at 30 V or higher. PG B1 Output Power Good is an open-drain, active LOW output and becomes asserted when 2.5 V < V IN < V OVLO . For additional details on setting V OVLO , please consult the “OVLO Calculation” section under Applications Information. 1 V IN < V IN_min or VIN ≥ V OVLO

0 Voltage Stable

A high-to-low transition on this pin initiates the operation of the SLG59H1313C’s logic control. ON is an asserted active-LOW, level-sensitive CMOS input with V IL_ON < 0.5 V and V IH_ON > 1.2 V. As the ON pin input circuit is directly connected to internal digital circuits, connect this pin to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller – do not allow this pin to be open-circuited. OVLO C1 Input Overvoltage Lockout Adjustment Pin. To set the SLG59H1313C’s OVLO trip threshold to its internal V IN_OVLO , connect OVLO pin to GND. To set the SLG59H1313C’s OVLO trip threshold with an external resistor network, please consult Applications Information section; - minimum recommended value for R 1 is 1 MΩ GND A4, B4, C4 GND Analog GND (3 contacts) Part Number Type Production Flow SLG59H1313C WLCSP 12L Industrial, -40 °C to 85 °C SLG59H1313CTR WLCSP 12L (Tape and Reel) Industrial, - 40 °C to 85 °C

Revision 1.07 Page 3 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Absolute Maximum Ratings Parameter Description Conditions Min. Typ. Max. Unit VIN to GND Load Switch Input Voltage to Ground Continuous -0.3 -- 29 V V OUT to GND Load Switch Output Voltage to GND -0.3 -- V IN + 0.3 V VOVLO , ON , PG to GND OVLO, ON , PG Pin Voltages to GND -- -- 6 V IIN Switch I/O Current Continuous -- -- 4.5 A tPD Total Power Dissipation at T A = 25°C Continuous -- -- 1.48 W TSTG Storage Temperature Range -65 -- +150 °C TJ Maximum Junction Temperature -- -- +150 °C θJA Package Thermal Resistance, Junction-to-Ambient 1.3 x 1.8 mm 12L WLCSP; Determined using a 1 in 2, 1 oz. copper pad under each IN and OUT terminal and FR4 pcb material. -- -- 84.1 °C/W VIN ESD SYS IEC 61000-4-2 System ESD Air Gap 15 -- -- kV Contact 8 -- -- kV ESD HBM Human Body Model ESD Protection All pins 4 -- -- kV ESD CDM Charged Device Model ESD Protection All pins 1 -- -- kV ESD SURGE VIN Surge Protection ESD Protection IEC 61000-4-5 +100 -- -- V Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at thes e or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions TA = -40 °C to 85 °C (unless otherwise stated) Parameter Description Min. Typ. Max. Unit Basic Operation VIN Load Switch Input Voltage 2.5 -- 20 V TA Operating Temperature -40 -- 85 °C

Electrical Characteristics

TA = -40 °C to 85 °C (unless otherwise stated). Typical values are V IN = 5.0 V, I IN ≤ 3 A, C IN = 0.57 µF, T A = 25 °C Parameter Description Conditions Min. Typ. Max. Unit Basic Operation VIN_CLAMP Input Clamping Voltage I IN = 10 mA -- 35 -- V lQ Input Quiescent Current V IN = 5 V; ON = 0 V -- 245 310 µA lQ_OFF Input Quiescent Current when OFF V IN = 5 V; ON = 1.2 V -- 0.15 1 µA lIN_Q OVLO Supply Current V OVLO = 3 V; V IN = 5 V; V OUT = 0 V -- 165 200 µA

Revision 1.07 Page 4 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation VIN_OVLO Internal Over-Voltage Trip Level VIN Rising, OVLO = GND 6.2 6.5 6.8 V VIN Falling, OVLO = GND 6.0 -- -- V VOVLO_TH OVLO Set Threshold V IN = 2.5 V to V OVLO 1.10 1.20 1.30 V VOVLO_RNG Adjustable OVLO Threshold Range V IN = 2.5 V to V OVLO 4 -- 20 V VOVLO_SELECT External OVLO Select Threshold -- 0.30 0.28 V RDS ON ON Resistance VIN = 5 V; I OUT = 0.1 A; T A = 25 °C -- 23 28 mΩ VIN = 5 V; I OUT = 0.1 A; T A = 85 °C -- 29 34 mΩ CLOAD Output Load Capacitance V IN = 5 V 0.47 -- 500 µF lOVLO OVLO Input Leakage Current V OVLO = V OVLO_TH -100 -- 100 nA THERM ON Thermal Shutdown Turn-on Temperature -- 145 -- THERM HYS Thermal Shutdown Hysteresis -- 20 -- °C lOCP Regular Over Current Protection V IN = 2.5 V to V OVLO -- 7 -- A lSCP Startup Current Protection V IN = 2.5 V to V OVLO -- 1 -- A Digital Signals VOL_PG PG Output LOW Voltage V I/O = 3.3 V; I SINK = 1 mA -- -- 0.4 V VIH_ON ON HIGH Voltage V IN = 2.5 V to V OVLO 1.2 -- -- V VIL_ON ON LOW Voltage V IN = 2.5 V to V OVLO -- -- 0.5 V ILKG_PG PG Leakage Current VI/O = 3.3 V; PG Deasserted, ILKG_ON ON Leakage current V IN = 5 V; V OUT = Float -1.0 -- 1.0 µA Timing Characteristics tDEB Debounce Time Time from 2.5 V < V IN < V IN_OVLO to V OUT = 0.1 x V IN -- 15 -- ms tSTART Soft-Start Time Time from V IN = V IN_min to 0.2 x PG ; VI/O = 1.8 V with 10 kΩ pull-up resistor -- 30 -- ms tON Switch Turn-on Time VIN = 5 V; R LOAD = 100 Ω; VOUT from 0.1 V IN to 0.9 V IN ; CLOAD = 100 µF -- 4 -- ms tOFF Switch Turn-off Time RLOAD = 100 Ω; C LOAD = 0 µF; VIN > V OVLO to V OUT = V IN - 50 mV -- 50 -- ns Notes: 1. Based on bench measurement only. Electrical Characteristics (continued) TA = -40 °C to 85 °C (unless otherwise stated). Typical values are V IN = 5.0 V, I IN ≤ 3 A, C IN = 0.57 µF, T A = 25 °C Parameter Description Conditions Min. Typ. Max. Unit

Revision 1.07 Page 5 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Timing Diagram: Power up and Normal Operation Timing Diagram: OVLO Trigger VIN VOUT PG ON tDEB tON tOFF tSTART 1. Measured @ 80% ON , V OUT = 80% V IN 2. Measured @10/90% 3. Measured @ V IN > 2.5 V to 0.2 x PG ; PG : V IO = 1.8 V w/ 10K Pull Up VIN VOUT PG tSTART 1. Measured @ OVLO Rising V OUT = V IN - 50 mV tOFF VOVLO tSTART

Revision 1.07 Page 6 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation RDSON vs. Temperature and VIN

Figure 29. Typical Power Up/Down operation waveform for V IN = 5 V, RLOAD = 100 Ω

Revision 1.07 Page 22 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Applications Information Typical Application Circuit VIN Over-Voltage Lockout (OVLO) Calculation VOVLO can be set externally and override the SLG59H1313C’s default OVP by connecting an external resistor-divider to the OVLO pin. The following equation produces the desired trip voltage and resistor values: Recommended minimum R 1 = 1 MΩ. Since the minimum recommended value for R 1 is 1 MΩ, the equation can be rewritten to isolate R 2 for a desired V OVLO : On-The-Go (OTG) Functionality During OTG operation, the SLG59H1313C’s initially d isabled and its power FET bulk diode becomes forwar d biased. The bulk diode forward drop when conducting is approximately 0.7 V and remains forward biased until the applied V IN rises higher than 2.5 V. While the IC is disabled and its FET body di ode is forward biased, the max DC current through t he diode is 1.8 A. This current is limited by the thermal performance of the IC (0.7 V x 1.8 A = 1.26 W). Since sustained DC power dissipation in the OFF state should be minimized, the FET’s body diode can withstand transient current operation so long as t he max limit is never exceeded. To enable the operation of the SLG59H1313C, its ON pin must be pulled LOW. The time-domain profile of any transient current through the bulk diode should not exceed the RC time constant formed by the C IN and C LOAD capacitors. At the system level, over-voltage and over-current protection should be provided external to the SLG59H1313C. State Machine + Gate Drivers + Logic IN TVS OVLO OVLO ON GND 23 mΩ CIN ≥ 0.57 µF Closed Open Multiple Contacts Multiple Contacts PG OUT OTP OCP VPU RPU USB Port or Power Adapter Battery Charger 1S1P Li-ion Battery PMIC Application Processor VOUT VIN ≥ 1 MΩ CLOAD ≥ 0.47 µF VOVLO = V OVLO_TH x 1 + R2 = VOVLO VOVLO_TH - 1

1. Since the IN and OUT pins dissipate most of the heat generated during high-load current operation, it is highly recommended
2. To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input C IN and output
3. The GND pin should be connected to system analog or power ground plane.

dedicated only for RDSON evaluation. Figure 30. SLG59H1313C Evaluation Board

Revision 1.07 Page 25 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Package Top Marking System Definition

1313 Part Code Pin A1 Identifier

WWNNNN Date Code + LOT Code ARR Assembly + Rev. Code 1313 - Part ID Field WW - Date Code Field NNN - Lot Traceability Code Field 1 A - Assembly Site Code Field 2 RR - Part Revision Code Field 2 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z

Revision 1.07 Page 26 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Package Drawing and Dimensions

12 Lead WLCSP Package

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Revision 1.07 Page 27 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation SLG59H1313C 12-pin WLCSP PCB Landing Pattern

Revision 1.07 Page 28 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Recommended Reflow Soldering Profile For successful reflow of the SLG59H1313C a recommended thermal profile is illustrated below: Note: This reflow profile is for classification/pre conditioning and are not meant to specify board ass embly profile. Actual board assembly profiles should be developed based on specific process needs and board designs and should not exceed parameters depicted on figure above. Please see more information on IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.643 mm (nominal).

Revision 1.07 Page 29 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation Tape and Reel Specifications Carrier Tape Drawing and Dimensions Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] WLCSP 12L 1.3 x 1.8 mm 0.4P Green 12 1.3 x 1.8 x 0.5 3,000 3,000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width Tape Thickness A0 B0 K0 P0 P1 D0 E F W T WLCSP 12L 1.3 x 1.8 mm 0.4P Green Refer to EIA-481 specification Note: Orientation in carrier: Pin1 is at upper right corner (Quadrant 2).

Revision 1.07 Page 30 of 30 SLG59H1313C A 23 mΩ, 4.5 A nFET Load Switch with Surge Protection and Adjustable OVP in a 2.34 mm 2 WLCSP ©2022 Renesas Electronics Corporation

Revision History

2/2/2022 1.03 Updated Company name and logo Fixed typos 3/18/2021 1.06 Updated Abs Max Table Fixed typos 2/18/2021 1.05 Updated Features 12/20/2018 1.04 Added Layout Guidelines 7/24/2018 1.03 Updated V OVLO_TH spec to 2 decimal places 7/09/2018 1.02 Fixed typos 6/20/2018 1.01 Fixed typo in Landing Pattern Updated style and formatting 3/5/2018 1.00 Production Release

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