SLG55550 RENESAS | Alldatasheet

Document overview

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  • PDF pages: 10

Technical content

Features

  • High Speed USB Switching
  • Low 4.0 pF (typ) On Capacitance
  • Low 4.0 Ω (typ) On Resistance
  • Low 0.5 Ω (typ) On Resistance Flatness
  • 2.8 V to 5.5 V Supply Range
  • Low 8 µA (typ) Supply Current
  • Automatic USB Charger Identification Circuit
  • USB Battery Charging Specificatlon 1.2 compliant
  • Pb-Free / RoHS Compliant
  • Halogen-Free
  • 3 x 3 mm TDFN-10 Package Pin Configuration Thermal Pad connected to GND RDM GND VDD TDM TDP DM TDFN-10 DP CB0 SLG555501 10 CB1 RDP (Top View) FSM Logic VREF1 VREF1 VDD TDP TDM CB0 DM DP VREF2 CB1 RDP RDM Resistor Divider Resistor Divider

000-000555650-101 Page 2 of 9 SLG55550 SLG55550A Pin Description Pin # Name Type Description

1 CB0 Input Switch Control Bit

See Digital Input States Table on page 6

2 DP Input/Output USB Connector D+

3 DM Input/Output USB Connector D-

4 GND GND Ground

5 RDP Input External Resistor Bias Input for D+ and Se lection for External Resistors in

6 RDM Input External Resistor Bias Input for D-

7 VDD PWR Power Supply. Connect a 0.1 µF capacitor between VDD and GND as close as possible to the device

8 TDM Input/Output Host USB Transceiver D- Connection

9 TDP Input/Output Host USB Transceiver D+ Connection

10 CB1 Input Switch Control Bit

See Digital Input States Table on page 6

11 Thermal Pad GND Ground

Ordering Information

SLG55550VTR TDFN-10 - Tape and Reel SLG55550AVTR TDFN-10 - Tape and Reel

000-000555650-101 Page 3 of 9 SLG55550 SLG55550A Absolute Maximum Conditions Parameter Min. Max. Unit Supply Voltage -0.3 6.0 V Continuous Current into any terminal -30 +30 mA Continuous Power Dissipation -- 1951 mW Operating Temperature Range -40 85 °C Junction Temperature 150 °C Storage Temperature Range -65 150 °C Lead Temperature (Soldering, 10s) 260 °C Electrical Characteristics - Power Supply VDD = 2.8V to 5.5V, T A = 25 °C (unless specified otherwise) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Power Supply Range V CB > V IH 2.8 -- 5.5 V IDD Supply Current V DD = 3.3 VCB0 = V CB1 = V DD -- 1 -- µA VCB0 = 0V, V CB1 = V DD -- 7 -- µA External Resistors used. V CB0 = V CB1 = 0V or VCB0 = V DD & VCB1 = 0V -- 7 -- µA Internal Resistors used. V CB0 = V CB1 = 0V or VCB0 = V DD & VCB1 = 0V -- 75 -- µA Supply Current V DD = 5.5 VCB0 = V CB1 = V DD -- 2 -- µA VCB0 = 0V, V CB1 = V DD -- 9 -- µA External Resistors used. V CB0 = V CB1 = 0V or VCB0 = V DD & VCB1 = 0V -- 9 -- µA Internal Resistors used. V CB0 = V CB1 = 0V or VCB0 = V DD & VCB1 = 0V -- 120 -- µA ΔIDD Supply Current Increase 0 ≤ VCB ≤ VIL or V IH ≤ VCB ≤ VDD -- -- 2 µA Electrical Characteristics - Analog Switch VDD = 2.8V to 5.5V, T A = 25 °C (unless specified otherwise) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDP , V DM Analog signal Range 0 -- V DD V RON On Resistance TDP/TDM Switch V DD = -0.4V to 0.4V, I = 10mA -- 4 -- Ω VDP = V DM = 0V to V DD VDD = 5V -- -- 10 Ω ΔRON On Resistance Match be - tween channels TDP/TDM Switch V DD = 5.0V VDP = V DM = 400mV IDP = I DM = 10mA -- 0.1 -- Ω RFLAT On Resistance flatness TDP/TDM Switch V DD = 5.0V VDP = V DM = 0V to V DD IDP = I DM = 10mA -- 0.5 -- Ω

000-000555650-101 Page 4 of 9 SLG55550 SLG55550A RSHORT On Resistance of TDP/TDM Short V CB = 0V VDP = 1V IDP = I DM = 10mA -- 50 70 Ω ITDPOFF , ITDMOFF Off-Leakage Current VDD = 3.6V VDP = V DM = 0.3V to 3.3V VTDP = V TDM = 3.3V to 0.3V VCB = 0V -250 -- 250 nA IDPON , IDMON Off-Leakage Current VDD = 3.6V VDP = V DM = 3.3V to 0.3V VCB = V DD -250 -- 250 nA Electrical Characteristics - Dynamic Performance VDD = 2.8V to 5.5V, T A = 25 °C (unless specified otherwise) Symbol Parameter Condition/Note Min. Typ. Max. Unit TON Turn On Time VTDP or V TDM = 1.5V RL = 300 Ω CL = 35pF --‘ 20 100 µs TOFF Turn Off Time VTDP or V TDM = 1.5V RL = 300 Ω CL = 35pF --‘ 1 5 µs TPLH , T PHL TDP/TDM Switch Propaga - tion Delay RL = R S = 50 Ω -- 60 -- ps TSKEW Output Skew Skew between DP and DM when connected to TDP and TDM R L = R S = 50 Ω -- 40 -- ps COFF TDP/TDM Off-Capacitance f = 1MHz --‘ 2.0 -- pF CON DP/DM On-Capacitance f = 240MHz --‘ 4.0 5.5 pF BW -3dB Bandwidth R L = R S = 50 Ω -- 1000 -- MHz VISO Off-Isolation VTDP, VDP = 0dBm RL = R S =5 0 Ω f = 250MHz -- -20 -- dB VCT Crosstalk VTDP, VDP = 0dBm RL = R S = 50 Ω f = 250MHz -- -25 -- dB Electrical Characteristics - Internal Resistors VDD = 2.8V to 5.5V, T A = 25 °C (unless specified otherwise) Symbol Parameter Condition/Note Min. Typ. Max. Unit RPD DP/DM Short Pull-down 350 500 700 k Ω RT RP RP1/RP2 Ratio 1.485 1.5 1.515 Ratio RRP RP1 + RP2 Resistance 93.75 125.0 156.25 k Ω RT RM RM1/RM2 Ratio 0.8544 0.863 0.872 Ratio RRM RM1 + RM2 Resistance 69.75 93.0 115.18 k Ω Electrical Characteristics - Analog Switch VDD = 2.8V to 5.5V, T A = 25 °C (unless specified otherwise) Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-000555650-101 Page 5 of 9 SLG55550 SLG55550A Electrical Characteristics - Logic Input VDD = 2.8V to 5.5V, T A = 25 °C (unless specified otherwise) Symbol Parameter Condition/Note Min. Typ. Max. Unit VIH CB Input Logic High 1.4 -- -- V VIL CB Input Logic Low -- -- 0.4 V IIN CB Input Leakage Current VDD = 5.5V 0 ≤ VCB ≤ VIL or V IH ≤ VCB ≤ VDD -1 -- 1 µA Electrical Characteristics - ESD Protection VDD = 2.8V to 5.5V, T A = 25 °C (unless specified otherwise) Symbol Parameter Condition/Note Min. Typ. Max. Unit VESD ESD Protection Level (DP and DM Only) Human Body Model -- ±8 -- kV V ESD ESD Protection Level (All other pins) Human Body Model -- ±2 -- kV

000-000555650-101 Page 6 of 9 SLG55550 SLG55550A Digital Input States - SLG55550 VDD RDP <0.4V = Internal Resistor >0.4V = External Resistor CB0 CB1 DP/DM Position Internal or External Resis - tor Connected to DP/DM Comment 3.3V RDP < 0.4V X X -- -- Not Recommended RDP> 0.4V 0 0 Autodetection Circuit Active External Resistor Auto Mode 0 1 Shorted Not Connected Auto Mode Disabled 1 0 Connected to Resistor- Divider External Resistor Auto Mode Disabled 1 1 Connected to TDP/TDM Not Connected USB Traffic Active 5.0V RDP< 0.4V 0 0 Autodetection Circuit Active Internal Resistor Auto Mode 0 1 Shorted Not Connected Auto Mode Disabled 1 0 Connected to Resistor- Divider Internal Resistor Auto Mode Disabled 1 1 Connected to TDP/TDM Not Connected USB Traffic Active RDP> 0.4V 0 0 Autodetection Circuit Active External Resistor Auto Mode 0 1 Shorted Not Connected Auto Mode Disabled 1 0 Connected to Resistor- Divider External Resistor Auto Mode Disabled 1 1 Connected to TDP/TDM Not Connected USB Traffic Active Digital Input States - SLG55550A VDD RDP CB0 CB1 DP/DM Position Internal or External Resis - tor Connected to DP/DM Comment 5.0V X 0 0 Autodetection Circuit Active Internal Resistor Auto Mode X 0 1 Shorted Not Connected Auto Mode Disabled X 1 0 Connected to Resistor- Divider External Resistor Auto Mode Disabled X 1 1 Connected to TDP/TDM Not Connected USB Traffic Active

000-000555650-101 Page 7 of 9 SLG55550 SLG55550A Package Top Marking System Definition Part Code Datecode Lot Revision – Part ID Field: identifies the specific device configuration – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Assembly Site/COO: Specifies Assembly Site/Country of Origin – Revision Code: Device Revision XXXXX DD LLL C RR COO

000-000555650-101 Page 8 of 9 SLG55550 SLG55550A Package Drawing and Dimensions

10 Lead TDFN Package

Approved: Symbol A b C D E e LS Symbol Min Nom. Max Unit: mm Min Nom. Max

0.50 BSC

0.30 0.35 0.40

0.35 REF

0.25 E D b e L S A PIN1 DOT Area - -

000-000555650-101 Page 9 of 9 SLG55550 SLG55550A Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 6.75 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 10L Green 10 3 x 3 x 0.75 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 10L W EP0 Y Y Section Y-Y CL F Refer to EIA-481 specification

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