SLG55221 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: pwong
  • PDF pages: 10

Technical content

Features

  • 5 V Power supply
  • Drain Voltage Range 1.0 V to 20 V
  • Internal Gate Voltage Charge Pump
  • Controlled Load Discharge Rate
  • Controlled Turn on Slew Rate
  • TDFN-8 Package

Applications

  • Power Supply Sequencing with ramp/delay/discharge control
  • Power Rail “Soft” Switch
  • Hot Plugging Applications
  • Low Transient Load Switching
  • Replace high cost P-channel MOSFETs with lower cos t N-channel MOSFETs Pin Configuration Environmental
  • Pb-Free / RoHS compliant
  • Halogen Free Target Application Products
  • Notebook & Netbook Battery Packs
  • Notebook & Netbook Sleep Mode Circuits
  • Server Load Switches
  • Gaming Sleep Mode Power Switches
  • Communications Power Switches DGND S/DIS1 G1/G2 PG DIS2 ON VCC 4 5 SLG552211 Thermal Pad connected to GND TDFN-8 (Top View) VD = 20V Max Vs G1/G2 S/DIS1 ON GND VCC = 5V D PG 8 DIS2 3 LOAD1 LOAD2 The highest V D being switched must be at FET1 and pin 5 of the SLG55221 and SLG55220 FET1 FET2 3.3V Q-PUMP Timing & Logic Discharge SLG55221 VG is pumped to V D + 8V SLG55220 VG is pumped to V D + 4V min

Revision 1.02 Page 2 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation Pin Description Overview The SLG55221/220 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Chan - nel FET switches from a CMOS logic level input. Int ended as a supporting control element for switched voltage rails in energy efficient, advanced power management systems, the SLG55221/220 also integrates circuits to discharge opened switched volt - age rails. The gate driver is available in a variety of configurations supporting a range of turn-on slew rates from 0.80V/ms up to 2V/ms which, depending on load supplying source voltages in the range of 1.0V to 20V results in ramp times from 200 µs to over 20ms (see Application Section). Additionally, an internal discharge circuit provides a controlled path to remove charge from open power rails. The SLG55221/220 gate drive is package d in an 8 pin DFN package. A power good (PG) signal is asserted when FET1 is fully ON. When used with external N-Channel FETs, the SLG55221 supports low transient, energy efficient switching of high current loads at source voltages ranging from 1.0V to 20V. A ‘Low Drive’ version of the device, is available to support applications where FET Vgs cannot exceed 8V.

Ordering Information

Pin # Pin Name Type Pin Description VCC 1 Power Supply Voltage 2 ON Input CMOS Logic Level. See SLG55251 for Control Input ON# instead of ON.

3 DIS2 Output Discharge Connection for Load2

4 GND GND Ground

5 D Input FET Drain Connection (Connect to FET with hi ghest V

D voltage)

6 S/DIS1 Input/Output Source Connection,

Discharge Connection for Load1

7 G1/G2 Output FET Gate Drive for FET1, FET2

8 PG Output CMOS Power Good Signal

(Volts/ms) Delay Time (ms) Discharge Resistor (ohms) Package Type SLG55220 -120010V 1.30 0.50 200 TDFN-8 SLG55221-120010V 1.30 0.50 200 TDFN-8 SLG55220 -120010VTR 1.30 0.50 200 TDFN-8 - Tape and Re el (3k units) SLG55221-120010VTR 1.30 0.50 200 TDFN-8 - Tape and Reel (3k units)

Revision 1.02 Page 3 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation Absolute Maximum Ratings Parameter Min. Max. Unit VD or V S to GND -0.3 40.0 V Voltage at Logic Input pins -0.3 6.5 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Operating temperature range -55 125 °C Junction temperature -- 150 °C ESD Human Body Model -- 2000 V ESD Machine Model -- 200 V

Electrical Characteristics

TA = -10 °C to 75 °C Parameter Description Conditions Min. Typ. Max. Unit VCC Supply Voltage 4.75 5.0 5.25 V TVCC_RAMP VCC Ramp-up Rate See Note 1 0.25 -- -- V/ms Iq Quiescent Current VG not ramping FET = ON -- -- 80 µA VG not ramping FET = OFF -- 0.1 1 µA VG ramping FET = OFF to ON -- 600 1500 µA VD FET Drain Voltage SLG55220 0.95 -- 5.25 V SLG55221 1.0 -- 20 V V GS Gate-Source Voltage SLG55220 4.0 4.7 6.0 V SLG55221 8.0 -- 13 V C G FET Gate Capacitance 500 -- 18000 pF TDELAY Ramp Delay Range 0.25 0.5 0.75 ms TSLEW FET Turn on Slew Rate 0.91 1.30 1.69 V/ms IDISCHARGE Internal Discharge Resistor Nominal discharge time of ~100ms 10mA max rate 140 200 260 Ω V IH HIGH-level input voltage ON (200mV Hysteresis) 2.4 -- 5 .5 V VIL LOW-level Input voltage ON (200mV Hysteresis) -- -- 0.4 V VOH HIGH-level output voltage PG 4.0 -- -- V VOL LOW-level output voltage PG -- -- 0.7 V IOL_LOGIC Logic LOW level output PG Sink Current 1 2 3 mA IG_OL Gate Drive Sink Current 400 -- -- µA IG_OH Gate Drive Source Current 32 -- -- µA ID_IH Drain Pin Current V D = 20V in Standby -- -- <1.0 µA IS_IH Source Pin Current Quiesent V S = 20V -- -- <1.0 µA Notes: 1. If T VCC_RAMP > 5V/ms and ON is asserted, Gate charging will begi n after 1ms.

Revision 1.02 Page 4 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation Application Example In a typical application, de-asserting ON (low) or turns off the external power N-FET. When the FET is turned off, the voltage at the load is discharged through a resistor (400 Ohms to 1000 Ohms or Open) internal to the SLG55221/220 with the discharge current limited to a maximum of 10mA. When ON is asserted (high), gate voltage is not applied to the gate of the external power N-FET until after DLY_t then the gate source (Vgs) voltage is ramped up to 11.5V above the source volt age V S at a slew rate determined by the internal slew rate control element internal to the SLG55221/220. Monotonic rise of Vs is maintained even as ID increases dramatically after the load device turn on threshold voltage is reached. After the source voltage has ramped up to its maximum steady state value, PG (Power Good) is asserted. PG may be used as the ON control of a second SLG55221/220 thereby providing power on sequence control of a number of switched power rails. The devices will not operate if Vcc is below 3.5V and will not operate until V D reaches 0.8V. The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate for variations in load current as the voltage is applied.

Revision 1.02 Page 5 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation Delay Time and Slew Rates The two components of controlling the application of FET source voltage to the load are a fixed time delay before beginning turn on of the FET (DLY_t below) and the Slew Time of the source voltage (Slew_t below). The Delay Time before gate voltage to the FET is applied is 250 µs independent of FET drain voltage, source voltage or SLG55221/220 supply voltage. Having control over the Slew Rate of the FET’s sour ce voltage as the FET is turning on is important in controlling dv/dt caused transients. A power FET, for example, switching a 5 V rail which has a total of 500 µF of decoupling, fully on in 10 µs will generate a 250 A current surge which is very undesirable. If the FET turn on time can be stretched to 1 ms, the current surge to charge the decoupling capacitors is reduced to 2.5 A. The SLG55221/220 controls slew rate of a FET’s source voltage as it is turned on. A range of slew rates are available as device order options. Obviously the time to fully slew the sour ce voltage to fully on is a function of the drain supply voltage. The table and graph below shows source voltage ramp times for various slew rates supported by the SLG55221/220 for a range of specific source voltages. * The minimum time that ON can be de-asserted between switching cycles is 100 ms. Slew Rates (V/ms) Ramp Times (ms) vs. Source Voltages (V) ON V S I S DLY_t Slew_t Discharge_t

Revision 1.02 Page 6 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation Package Top Marking System Definition Part ID Assembly Code Datecode Lot Revision 8 7 6 5 1 2 3 4 – Part ID Field: identifies the specific device configuration – Assembly Code Field: Assembly Location of the device. – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Revision Code: Device Revision XX A DD L R

Revision 1.02 Page 7 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation Package Drawing and Dimensions

8 Lead TDFN Package

Revision 1.02 Page 8 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.00 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 8L Green 8 2 x 2 x 0.75 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 8L W EP0 Y Y Section Y-Y CL F

Revision 1.02 Page 9 of 9 SLG55221-120010 SLG55220-120010 Dual Rail High Voltage Gate Driver ©2022 Renesas Electronics Corporation

Revision History

2/9/2022 1.02 Updated Company name and logo Fixed typos 7/10/2018 1.01 Updated style and formatting

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.