SLG55031

SLG55031 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Paul Cheng
• PDF pages: 13

Technical content

Features

• Drain Voltage Range 0.7 V to 1.5 V
• Controlled Load Discharge Rate
• Controlled Turn on Slew Rate
• Pb-Free / RoHS compliant
• Halogen-Free
• 2mm x 2mm TDFN-8 Package

Applications

• Low Transient Load Switching
• Personal computers and Servers
• Hot Plugging Applications
• Power Rail Switches S LOAD GATE SOURCE ENABLE G CC DRAIN 1 Timing & Logic SLG5AP03x DONE 3CNFG D DRAIN GND 3 4 SOURCE GATE DONE CNFG 3 6 SLG55031 TDFN-8 ENABLE VCC 1 4 5

000-0055031-102 Page 2 of 12 SLG55031 Pin Description Pin Name Pin Number Type Pin Description VCC 1 Power Supply Voltage 5V ENABLE 2 Input CMOS Logic Level. High True for SLG5503 1 CNFG 3 Input Resistor or Capacitor Connection for timi ng configuration GND 4 GND Ground. DRAIN 5 Input FET Drain Connection SOURCE 6 Input Source Connection GATE 7 Output FET Gate Drive DONE 8 Output Output CMOS Open Drain - Power Good, indicates external FET fully on.

Ordering Information

SLG55031VTR External Resistor HIGH True Active 1.5 V < VT < 2.5 V TDFN-8 - Tape and Reel (3 k units)

000-0055031-102 Page 3 of 12 SLG55031 Absolute Maximum Conditions Parameter Min. Max. Unit VCC to GND -0.3 6.0 V Voltage at Logic Input pins -0.3 6.0 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Operating temperature range 0 70 °C Junction temperature -- 150 °C Moisture Sensitivity Level 1 Electrical Characteristics (-10 °C to 75 °C) Symbol Parameter Condition/Note Min. Typ. Max. Unit VCC Supply Voltage 4.75 5.0 5.25 V Iq Quiescent Current ENABLE = 1, V G not ramping 1.5 5 µA ISTBY Standby Current ENABLE = 0 2 3 µA T Operating Temperature 0 25 70 °C VD Driven FET Drain Voltage May dynamically vary 0.7 -- 1. 5 V VG Gate Voltage Tracks Supply V CC 4.75 5.0 5.25 V TVT FET Turn on Delay FET VT <2.0V FET GATE CIN < 4nF 3 8 -- µs I DISCHARGE Internal Discharge Equiva - lent Current Discharges MOSFET Source -- -- 10 mA VIH HIGH-level input voltage ENABLE pin 2.0 -- -- V VIL LOW-level Input voltage ENABLE pin -- -- 1.0 V IIH HIGH-level Input Current Digital pins, V IN = V CC -1.0 -- 1.0 µA IIL LOW-level input Current Digital pins, V IN = 0V -1.0 -- 1.0 µA VOH_LOGIC DONE Pull-up Voltage Open Drain Output Buffer -- -- 5.5 V

000-0055031-102 Page 4 of 12 SLG55031

Description

In a typical application, de-asserting ENABLE turns off the external power N-FET. The voltage at the load is discharged through the discharge control path internal to the SLG55031. The rate of discharge is current limited to 10 mA. When ENABLE is asserted, gate voltage is applied to the gate of the external power N-FET within 10 µs (typical) then the gate voltage is ramped up to V CC - V D (3.5 V typical) at a slew rate determined by the v alue of the external resistor or capacitor connected to the CNFG pin of the SLG55031. Monotoni c rise of the external FET’s source voltage V S is maintained even as Source current increases after the load device turn on threshold voltage is reached. After the Source voltage has ramped up to the Drain Voltage – the voltage drop contribution b y R DS-ON of the FET, the external FET is fully on and the o pen drain DONE signal is asserted. If a voltage is not present on the Drain Sense Pin prior to assertion of ENABLE, the FET’s gate will b e immediately driven high turning the FET fully on. DONE may be used as the ENABLE control of a second SLG55031 connected in series thereby providing power on sequence control of a number of switched power rails, or used in a ‘wired and’ with other DONE signals to indicate all switched power rails are in a power good condition. Configuration Options The SLG55031 is configured with external passive de vices to select between two widely separate ramp sl ew rates. See the following Table for details Configuration Pin Usage Table Resistor to Ground (SLG55031) to 1.5 V Rail Value ( Ω ) 400 K 560 K 750 K Typical Slew Time ( µs) 23 33 45

000-0055031-102 Page 5 of 12 SLG55031 Timing Diagram - Initial P-ON VCC to the SLG55031 must reach V CC min (4.75 V) before the device will begin to be op erational. ENABLE 1 must be asserted 100 µs after 100% of V CC has been attained. If V_DRAIN is present at a minimum of 3 µs prior to assertion of the ENABLE, the Source will begin to ramp towards V_DRAIN after T_VT (10 µs typically), the time required for the gate of the FET to be past turn on threshold (typically 2.0 V). Carefully examine specific FET turn-on threshold as well as FET C-IN and if the values fall outside of the range of values covered in the electrical sp ecifications section of this document, consult Rene sas for applications assis - tance in determining the value of T_VT. Diagram 1 Enable after VCC VCC ENABLE V_DRAIN V_GATE V_SOURCE DONE High True Example T_VCC_to_EN T_DRAIN_to_ENABLE T_VT T_slew

000-0055031-102 Page 6 of 12 SLG55031 If V_DRAIN is not present prior to the assertion EN ABLE, the driven FET will be turned on immediately following assertion of ENABLE and subsequent application of a voltage on t he Drain of the FET will be directly applied to the Source (Diagram 2). Again, V CC must have reached V CC-MIN before ENABLE will operate the device. V_Gate will be pulled to V CC after which the V_Source will track the voltage applied to the Drain of the FET. 1 T_V CC to ENABLE = 100 µs assertion delay (when V CC initially ramping up to 100% of V CC ). 2 Enable assertion transition time must be less than 1 µs. * If V_Drain = 0 V prior to assertion of ENABLE, DONE becomes true co-incident with assertion of ENABLE. * In the case of V_DRAIN after ENABLE, the definition of Arrival and Ramp Time are not valid Diagram 2 VCC ENABLE V_DRAIN V_GATE V_SOURCE DONE* High True Example T_slew = Drain Slew

000-0055031-102 Page 7 of 12 SLG55031 Timing Diagram - Rail Switching The two components of the FET turn-on time consist of the time it takes to drive the FET’s gate up to turn-on threshold (T_VT) added to the time it takes for the FET’s source voltage to ramp (T_Slew) up fully on into the driven load. The timing diagram and table below show the min/max values for these two components vs. different rail source voltage. The T_VT delay is 8 µs - 10 µs typically (with FET VT = 2.0 V) depending on the threshold voltage of the FET being driven (Diagram 3). The Table below and Diagram 3 illustrate source vol tage ramp times for various slew rates and resultin g total turn on time (ENABLE to DONE) when using the SLG55031 for several selected ranges of drain voltages. (See Diagram 4 below for more details) * T_Slew: As V_Source increases from 10% to 90% of V_Drain; e.g. ramp time ** T_Done: From assertion of Enable to V_Source = 90% of V_Drain; e.g. arrival time Diagram 3 Min (µSec) Typ (µSec) Max (µSec) SLG55031 R_ext = 560K Ω V_Drain Voltage (FET VT = 1.5 V to 2.5 V) 1.35 V 1.50 V T_Slew* 20 30 33 T_DONE** 42 46 65 Recommended FET: ON Semi NTMFS4834N ENABLE DONE High True Example T_Slew T_VT VS T_Discharge

000-0055031-102 Page 8 of 12 SLG55031 Timing Definition of Arrival Time and Ramp Time 1 The definition of Arrival Time and Ramp Time is only valid for ENABLE (asserted with a 100 µs delay) after V CC has reached 100% and V_DRAIN is present prior to assertion of ENABLE Diagram 4 Vcc 5V 100us (min.) 1/2VEnable Enable active high 1us (max) ramping rate for SLG55031V Source ramping 90% output rail SLG55031V < 65us SLG55031V 1.35 / 1.5V Arrival Time 1 Enable to 90% output rail Timing for Vcc and Enable 100us (min.) Min. ramp time of 10% - 90% output rail must be not less than 20us for SLG55031V Ramp Time 1 10% – 90% output rail > 20us 3.3V 90% 10% 90%

000-0055031-102 Page 9 of 12 SLG55031 Package Top Marking System Definition Part ID Assembly Code Datecode Lot Revision 8 7 6 5 1 2 3 4 – Part ID Field: identifies the specific device configuration – Assembly Code Field: Assembly Location of the device. – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Revision Code: Device Revision XX A DD L R

000-0055031-102 Page 10 of 12 SLG55031 Package Drawing and Dimensions

8 Lead TDFN Package

Note: Bottom side metal plate is at ground potentia l

000-0055031-102 Page 11 of 12 SLG55031 Tap e and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.00 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 8L Green 8 2 x 2 x 0.75 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 8L W EP0 Y Y Section Y-Y CL F

000-0055031-102 Page 12 of 12 SLG55031

Revision History

2/9/2022 1.01 Updated Company name and logo Fixed typos

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