SLG55022 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: pwong
  • PDF pages: 10

Technical content

Features

  • 12 V Power supply
  • Drain Voltage Range 1.0 V to 20 V
  • Internal Gate Voltage Charge Pump
  • Controlled Turn on Delay
  • Controlled Load Discharge Rate
  • Controlled Turn on Slew Rate
  • 2mm x 2mm TDFN-8 Package
  • Pb-Free / Halogen-Free / RoHS compliant

Applications

  • Power Rail Switches
  • Hot Plugging Applications
  • Soft Switching
  • Personal computers and Servers
  • Data Communications Equipment Pin Configuration D S G PG GND NC 4 5 SLG55022 8-pin TDFN ON VCC 1 (Top View) Load VS S PG GND Timing & Logic Q-PUMP ON VCC = 12V G D VD = 20V Max Discharge

Revision 1.04 Page 2 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Pin Description Overview The SLG55022 N-Channel FET Gate Driver is used for controlling a delayed turn on and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level i nput. Intended as a supporting control element for switched voltage rails in energy efficient, advanced power management systems, the SLG55022 also integrates circuits to discharge opened switched voltage rails. The gate driver is available in a v ariety of configurations supporting a range of turn-on slew rates from 0.80 V/ms up to 4 V/ms which, depending on load supplying source voltages in the range of 1.0 V to 20 V results in ramp times from 200 µs to over 20 ms (see Application Section). Delays until the ramp begins are source voltage independent and range from 250 µs to 5ms. A power good condition is output to indicate that the ramp-up slew of the source voltage is finished. Additionally, an internal discharge circuit provides a controlled path to rem ove charge from open power rails. The SLG55022 gate drive is packaged in an 8 pin DFN package. When used with external N-Channel FETs, the SLG55022 supports low transient, energy efficient switching of high current loads at source voltages ranging from 1.0V to 20V.

Ordering Information

Pin # Pin Name Type Pin Description VCC 1 Power Supply Voltage ON 2 Input CMOS Logic Level. High True NC 3 -- No Connect. GND 4 GND Ground. D 5 Input FET Drain Connection S 6 Input Source Connection G 7 Output FET Gate Drive PG 8 Output Output CMOS Open Drain - Power Good, indicates external FET fully on. Pull-up resistor greater than 300 k Ω recommended. Part Number Type SLG55022-200030V TDFN-8 SLG55022-200030VTR TDFN-8 - Tape and Reel (3k units)

Revision 1.04 Page 3 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Absolute Maximum Ratings Parameter Min. Max. Unit VD or V S to GND -0.3 40.0 V Voltage at Logic Input pins -0.3 6.5 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C ESD Human Body Model -- 2000 V ESD Machine Model -- 200 V Moisture Sensitivity Level 1

Electrical Characteristics

TA = -10 °C to 75 °C Parameter Description Conditions Min. Typ. Max. Unit VCC Supply Voltage 11.5 12.0 12.5 V TVCC_RAMP VCC Ramp-up Rate See Note 1 0.25 -- -- V/ms Iq Quiescent Current VG not ramping FET = ON 50 80 µA VG not ramping FET = OFF 0.1 1 µA VD FET Drain Voltage 1.0 -- 21 V VGS Gate-Source Voltage 8.0 11.5 16 V CG FET Gate Capacitance 500 -- 8000 pF TDELAY Ramp Delay Range 1.5ms Default, 500 µs step 0 500 750 µs TSLEW FET Turn on Slew Rate 1.2 2.0 2.8 V/ms IDISCHARGE Internal Discharge Resistor Nominal discharge time of ~100ms 10mA max rate 180 300 420 Ω V IH HIGH-level input voltage ON (200mV Hysteresis) 2.4 -- 5 .5 V VIL LOW-level Input voltage ON (200mV Hysteresis) -- -- 0.4 V VOH HIGH-level output voltage PG Open Drain -- -- 5.5 V IOL_LOGIC Logic LOW level output PG Sink Current 1 2 3 mA IIH * HIGH-level input current V IH = 3.3V -- -- <1.0 µA Notes: 1. If T VCC_RAMP > 5V/ms and ON is asserted, Gate charging will begi n after 1ms.

Revision 1.04 Page 4 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Device Operation In a typical application, de-asserting ON (low) turns off the external power N-FET. When the FET is turned off, the voltage at the load is discharged through a resistor (300 Ohms) internal to the SLG55022. When ON is asserted (high), the device will not begin driving the gate of the external power FET unless t he voltage at the drain of the device is at or abov e 0.8 V (e.g. V D ≥ 0.8 V) to prevent a ‘shootthrough’ situation to the FET’s source load. Gate voltage is not applied to the gate of the external power N-FET after DLY_t then the gate source (Vgs) voltage is ramped up to 11.5V above the source voltage V S at a slew rate determined by the internal slew rate control element internal to the SLG55022. Monotonic rise of Vs is maintained ev en as ID increases dramatically after the load device turn on threshol d voltage is reached. After the source voltage has ramped up to its maximum steady state value, the Open Drain PG (Power Good) signal is asserted. PG may be used as the ON contro l of a second SLG55022 thereby providing power on sequence control of a number of switched power rails, or used in a ‘wired and’ with other PG signals to indicate all switched power rails are in a power good condition. The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate for variations in load current as the voltage is applied.

Revision 1.04 Page 5 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Delay Time and Slew Rates The two components of controlling the application of FET source voltage to the load are a fixed time delay before beginning turn on of the FET (DLY_t below) and the Slew Time of the source voltage (Slew_t below). Having control over the Slew Rate of the FET’s sour ce voltage as the FET is turning on is important in controlling dv/dt caused transients. A power FET, for example, switching a 5 V rail which has a total of 500 µF of decoupling, fully on in 10 µs will generate a 250 A current surge which is very undesirable. I f the FET turn on time can be stretched to 1 ms, th e current surge to charge the decoupling capacitors is reduced to 2.5 A. The SLG55022 controls slew rate of a FET’s source volta ge as it is turned on. A range of slew rates are available as device order options. Obviously the time to fully slew the source voltage to fully on is a function of the drain supply voltage. The table and graph below shows source voltage ramp times for various slew rates supported by the SLG55022 for a range of specific source voltages. * The minimum time that ON can be de-asserted between switching cycles is 100 ms. Slew Rates (V/ms) Ramp Times (ms) vs. Source Voltages (V) ON V S I S DLY_t Slew_t Discharge_t

Revision 1.04 Page 6 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Package Top Marking System Definition me (ms) Ramp Times (ms) vs. Source Voltage for Various Slew Rates (v/ms) 2.00 Ramp Time (ms) Source Voltage Ramp Times (ms) vs. Source Voltage for Various Slew Rates (v/ms) 2.00 Ramp Time (ms) Source Voltage Ramp Times (ms) vs. Source Voltage for Various Slew Rates (v/ms) 2.00 Part ID Assembly Code Datecode Lot Revision 8 7 6 5 1 2 3 4 – Part ID Field: identifies the specific device configuration – Assembly Code Field: Assembly Location of the device. – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Revision Code: Device Revision XX A DD L R

Revision 1.04 Page 7 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Package Drawing and Dimensions

8 Lead TDFN Package

Revision 1.04 Page 8 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.00 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 8L Green 8 2 x 2 x 0.75 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 8L W EP0 Y Y Section Y-Y CL F

Revision 1.04 Page 9 of 9 SLG55022-200030 High Voltage Gate Driver ©2022 Renesas Electronics Corporation

Revision History

2/9/2022 1.04 Updated Company name and logo Fixed typos 7/10/2018 1.03 Updated style and formatting 7/29/2017 1.02 Added Pb-Free/Halogen Free/RoHS compliance Added MSL

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