SLG55021-200010 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: pwong
  • PDF pages: 9

Technical content

Features

  • 5 V ±5% Power supply
  • SLG55021 Drain Voltage Range 1.0 V to 20 V
  • Internal Gate Voltage Charge Pump
  • Controlled Turn on Delay
  • Controlled Load Discharge Rate
  • Controlled Turn on Slew Rate
  • Stable Slew Rate (±2% typ) over Temperature Range
  • TDFN-8 Package
  • Pb-Free / Halogen-Free / RoHS compliant

Applications

  • Power Rail Switches
  • Hot Plugging Applications
  • Soft Switching
  • Personal computers and Servers
  • Data Communications Equipment Pin Configuration DGND S G PG SHDN# TDFN-8 ON VCC (Top View) 4 5 SLG55021 D LOAD G S ON G CC D Timing & Logic SHDN# Q-PUMP PG 8 Discharge SLG55021 For N-MOSFETS with V GS < 20V

Revision 1.05 Page 2 of 8 SLG55021-200010 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Pin Description Overview The SLG55021 N-Channel FET Gate Driver is used for controlling a delayed turn on and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level i nput. Intended as a supporting control element for switched voltage rails in energy efficient, advanced power management systems, the SLG55021 also integrates circuits to discharge opened switched voltage rails. The gate driver is available in a va riety of configurations supporting a range of turn- on slew rates from 0.80 V/ms up to 4 V/ms which, depending on load supplying source voltages in the range of 1.0 V to 20 V results in ramp times from 200 µs up to over 20 ms (see Application Section). Delays until the ramp begins are source voltage independent and range from 250 µs to 5 ms. A power good condition is output to indicat e that the ramp-up slew of the source voltage is fi nished. Additionally, an internal discharge circuit provides a controlled pa th to remove charge from open power rails. The SLG5 5021 gate drive is packaged in an 8 pin DFN package. When used with external N-Channel FETs, the SLG55021 supports low transient, energy efficient switching of high current loads at source voltages ranging from 1.0 V to 20 V.

Ordering Information

Pin # Pin Name Type Pin Description VCC 1 Power Supply Voltage ON 2 Input CMOS Logic Level. High True SHDN# 3 Input Shut Down# - Low True Signal which immed iately turns FET off GND 4 GND Ground D 5 Input FET Drain Connection S 6 Input Source Connection G 7 Output FET Gate Drive PG 8 Output Output CMOS Open Drain - Power Good, indic ates external FET fully on Part Number Ramp Slew Rate (Volts/ms) Delay Time (ms) Discharge Resistor (ohms) Package Type SLG55021-200010V 2.0 0.15 200 TDFN-8 SLG55021-200010VTR 2.0 0.15 200 TDFN-8 - Tape and Reel (3k units)

Revision 1.05 Page 3 of 8 SLG55021-200010 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Absolute Maximum Ratings Parameter Min. Max. Unit VD or V S to GND -0.3 40.0 V Voltage at Logic Input pins -0.3 6.5 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Operating temperature range -55 125 °C Junction temperature -- 150 °C ESD Human Body Model -- 2000 V ESD Machine Model -- 200 V Moisture Sensitivity Level 1

Electrical Characteristics

TA = -10 °C to 75 °C Parameter Description Conditions Min. Typ. Max. Unit VCC Supply Voltage 4.75 5.0 5.25 V Iq Quiescent Current VG not ramping FET = ON -- <7 10 µA VG not ramping FET = OFF -- 0.1 1 µA VD FET Drain Voltage SLG55021 1.0 -- 20 V VGS Gate-Source Voltage SLG55021 8.0 11.5 13 V CG FET Gate Capacitance 500 -- 8000 pF TDELAY Ramp Delay Range 1.5ms Default, 500 µs step 0.105 0.15 0.195 ms TSLEW FET Turn on Slew Rate 1.4 2.0 2.6 V/ms IDISCHARGE Internal Discharge Resistor Nominal discharge time of ~100ms 10mA max rate 100 200 300 Ω V IH HIGH-level input voltage ON, SHDN# (200mV Hysteresis) 2.4 -- 5.5 V V IL LOW-level Input voltage ON, SHDN# (200mV Hysteresis) -- -- 0.4 V V OH HIGH-level output voltage PG Open Drain -- -- 5.5 V IOL_LOGIC Logic LOW level output PG Sink Current 1 2 3 mA IIH * SHDN# V IH = 3.3V -- -- <1.0 µA IG_OL Gate Drive Sink Current 400 -- -- µA IG_OH Gate Drive Source Current 32 -- -- µA ID_IH Drain Pin Current V D = 20V in Standby -- -- <1.0 µA IS_IH Source Pin Current Quiesent V S = 20V -- -- <1.0 µA Notes: 1. If using an open drain to drive SHDN#; pull up with 10 k Ω to V CC

Revision 1.05 Page 4 of 8 SLG55021-200010 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Application Example In a typical application, de-asserting ON (low) or asserting the low true Shut Down signal (SHDN#) tur ns off the external power N-FET. SHDN# is provided as an asynchronous override to the ON signal. When the FET is turned off, the voltage at the load is discharged through a resistor (typically 200 ohms) internal to the SLG55021 with the discharge current limited to a maximum of 10mA. When ON is asserted (high), gate voltage is n ot applied to the gate of the external power N-FET until after T DELAY then the gate source (Vgs) voltage is ramped up to 11.5 V above the source voltage V S at a slew rate determined by the internal slew rate control element internal to the SLG55021. Mono tonic rise of Vs is maintained even as ID increases dramatically after the load device turn on threshold voltage is reached. After the source voltage has ramped up to its maximum steady state value, the Open Drain PG (Power Good) signal is asserted. PG m ay be used as the ON control of a second SLG55021 t hereby providing power on sequence control of a number of switched p ower rails, or used in a ‘wired and’ with other PG signals to indicate all switched power rails are in a power good condition. The devices will not operate if Vcc is below 3.5 V. The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate for variations in load current as the voltage is applied.

Revision 1.05 Page 5 of 8 SLG55021-200010 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Package Top Marking System Definition Part ID Assembly Code Datecode Lot Revision 8 7 6 5 1 2 3 4 – Part ID Field: identifies the specific device configuration – Assembly Code Field: Assembly Location of the device. – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Revision Code: Device Revision XX A DD L R

Revision 1.05 Page 6 of 8 SLG55021-200010 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Package Drawing and Dimensions

8 Lead TDFN Package

Revision 1.05 Page 7 of 8 SLG55021-200010 High Voltage Gate Driver ©2022 Renesas Electronics Corporation Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.00 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 8L Green 8 2 x 2 x 0.75 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 8L W EP0 Y Y Section Y-Y CL F

Revision 1.05 Page 8 of 8 SLG55021-200010 High Voltage Gate Driver ©2022 Renesas Electronics Corporation

Revision History

2/9/2022 1.05 Updated Company name and logo Fixed typos 7/10/2018 1.04 Updated style and formatting 7/27/2017 1.03 Added Pb-Free/Halogen Free/RoHS compliance Added MSL 9/26/2016 1.02 Removed TBD values Fixed typos

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