SLG46534V

Renesas Technology Corp

GreenPAK Programmable Mixed-signal Matrix with Asynchronous State Machine March 3, 2023

Manufacturer: Renesas Technology Corp

Document: 177 Pages / 2Mb

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Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 177

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
Read Back Protection (Read Lock)
1.8 V (±5%) to 5 V (±10%) Supply
Operating Temperature Range: -40°C to 85°C
RoHS Compliant / Halogen-Free
14-pin STQFN: 2 x 2.2 x 0.55 mm, 0.4 mm pitch

Applications

Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO 4 9 GPI VDD 1 14-pin STQFN (Top View) GPIO SCL/GPIO 6 7 14 13 SDA/GPIO GPIO GPIO GPIO GPIO 5 POR 3-bit LUT3_2 or DFF5 Pin 4 GPIO Programmable Delay RC Oscillator Pin 5 GPIO Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 14 GPIO Pin 6 SCL or GPIO Pin 7 SDA or GPIO Pin 8 GPIO Pin 12 GPIO Pin 11 GPIO Pin 10 GPIO Pin 9 GND ACMP0 ACMP1 ACMP2 Additional Logic Functions Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_2 or DFF2 2-bit LUT2_1 or DFF1 2-bit LUT2_3 or PGEN 3-bit LUT3_1 or DFF4 3bit LUT3_0 or DFF3 3-bit LUT3_4 or DFF7 3-bit LUT3_3 or DFF6 FILTER_1 with Edge Detect I2C Serial Communication ASM 8 states 3-bit LUT3_5 or CNT/DLY2 3-bit LUT3_6 or CNT/DLY3 3-bit LUT3_7 or CNT/DLY4 3-bit LUT3_8 or CNT/DLY5 3-bit LUT3_9 or CNT/DLY6 4-bit LUT4_0 or CNT/DLY0 4-bit LUT4_1 or CNT/DLY1 3-bit LUT3_10 or Pipe Delay FILTER_0 with Edge Detect

8 Byte RAM +

1.0 Overview

The SLG46534 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the IO Pins and the mac - rocells of the SLG46534. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following:

Three Analog Comparators (ACMP)
Nineteen Combination Function Macrocells
Three Selectable DFF/Latch or 2-bit LUTs
One Selectable Continuous DFF/Latch or 3-bit LUT
Four Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
One Selectable Programmable Pattern Generator or 2-bit LUT
Five 8-bit delays/counters or 3-bit LUTs
Two 16-bit delays/counters or 4-bit LUTs
Two Deglitch Filters with Edge Detectors
Asynchronous State Machine
Eight States
Flexible input logic from state transitions
Serial Communications
I 2C Protocol compliant
Pipe Delay – 16 stage/3 output (Part of Combinatio n Function Macrocell)
Programmable Delay
Two Oscillators (OSC)
Configurable 25 kHz/2 MHz
25 MHz RC Oscillator
Crystal Oscillator
Power-On-Reset (POR)
Eight Byte RAM + OTP User Memory
RAM Memory space that is readable and writable via I
User defined initial values transferred from OTP

2.0 Pin Description

2.1 Functional Pin Description

Pin # Pin Name Function

1 VDD Power Supply

2 GPI General Purpose Input

3 GPIO General Purpose IO

4 GPIO General Purpose IO or ACMP0 (+)

5 GPIO General Purpose IO with OE or External Vref (A CMP0 IN-)

6 SCL/GPIO General Purpose IO SCL or GPIOD (NMOS open drain only)

7 SDA/GPIO General Purpose IO SDA or GPIOD (NMOS open drain only)

8 GPIO General Purpose IO with OE or ACMP1 (+)

9 GND Ground

10 GPIO General Purpose IO External Vref (ACMP1 IN-)

11 GPIO General Purpose IO with OE

12 GPIO General Purpose IO with OE

13 GPIO General Purpose IO

14 GPIO General Purpose IO or External Clock Input

3.0 User Programmability

as it remains powered and can be re-written as needed to facilitate rapid design changes. Figure 1. Steps to create a custom GreenPAK device

4.0 Ordering Information

Note 1: Use SLG46534V to order. Shipments are automatically in Tape and Reel. Note 2: “TR” suffix is no longer used. It is a legacy naming convention shown here only for informational purposes. Part Number Type SLG46534V 14-pin STQFN SLG46534VTR 14-pin STQFN - Tape and Reel (3k units)

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8 V ±5% V DD ) Parameter Min. Max. Unit Supply voltage on V DD relative to GND -0.5 7 V DC Input voltage GND - 0.5 V DD + 0.5 V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 11 mA Push-Pull 2x -- 16 OD 1x -- 11 OD 2x -- 21 OD 4x -- 43 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.06 -- V DD V Logic Input with Schmitt Trigger 1.28 -- V DD V Low-Level Logic Input 0.94 -- V DD V VIL LOW-Level Input Voltage Logic Input 0 -- 0.76 V Logic Input with Schmitt Trigger 0 -- 0.49 V Low-Level Logic Input 0 -- 0.52 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.10 0.41 0.66 V I LKG Input leakage (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage Push-Pull, I OH = 100 µA, 1X Drive 1.69 1.79 -- V PMOS OD, I OH = 100 µA, 1X Drive 1.69 1.79 -- V Push-Pull, I OH = 100 µA, 2X Drive 1.70 1.79 -- V PMOS OD, I OH = 100 µA, 2X Drive 1.70 1.79 -- V

© 2023 Renesas Electronics Corporation Page 6 of 175 SLG46534 Revision 1.18 VOL LOW-Level Output Voltage Push-Pull, I OL = 100 µA, 1X Drive -- 0.009 0.013 V Push-Pull, I OL = 100 µA, 2X Drive -- 0.004 0.006 V Open Drain, I OL = 100 µA, 1X Drive -- 0.006 0.009 V Open Drain, I OL = 100 µA, 2X Drive -- 0.003 0.004 V Open Drain NMOS 4X, I OL = 100 µA -- 0.001 0.002 V IOH HIGH-Level Output Pulse Current (see Note 1) Push-Pull, V OH = V DD - 0.2, 1X Drive 1.07 1.70 -- mA PMOS OD, V OH = V DD - 0.2, 1X Drive 1.07 1.70 -- mA Push-Pull, V OH = V DD - 0.2, 2X Drive 2.22 3.41 -- mA PMOS OD, V OH = V DD - 0.2, 2X Drive 2.22 3.41 -- mA IOL LOW-Level Output Pulse Current (see Note 1) Push-Pull, V OL = 0.15 V, 1X Drive 0.92 1.69 -- mA Push-Pull, V OL = 0.15 V, 2X Drive 1.83 3.38 -- mA Open Drain, V OL = 0.15 V, 1X Drive 1.38 2.53 -- mA Open Drain, V OL = 0.15 V, 2X Drive 2.75 5.07 -- mA Open Drain NMOS 4X, V OL = 0.15 V 7.21 9.00 -- mA IVDD Maximum Average or DC Current Through V DD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- V DD V TSU Startup Time From V DD rising past PON THR 0.63 1.36 1.87 ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.41 1.54 1.66 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 1.00 1.15 1.31 V RPUP Pull Up Resistance

1 M Pull Up -- 1 -- M Ω

100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance

1 M Pull Down -- 1 -- M Ω

100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

© 2023 Renesas Electronics Corporation Page 7 of 175 SLG46534 Revision 1.18 5.3 Electrical Characteristics (3.3 V ±10% V DD ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.81 -- V DD V Logic Input with Schmitt Trigger 2.14 -- V DD V Low-Level Logic Input 1.06 -- V DD V VIL LOW-Level Input Voltage Logic Input 0 -- 1.31 V Logic Input with Schmitt Trigger 0 -- 0.97 V Low-Level Logic Input 0 -- 0.67 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.29 0.62 0.94 V I LGK Input leakage (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage Push-Pull, I OH = 3 mA, 1X Drive 2.70 3.12 -- V PMOS OD, I OH = 3 mA, 1X Drive 2.70 3.12 -- V Push-Pull, I OH = 3 mA, 2X Drive 2.85 3.21 -- V PMOS OD, I OH = 3 mA, 2X Drive 2.86 3.21 -- V VOL LOW-Level Output Voltage Push-Pull, I OL = 3 mA, 1X Drive -- 0.13 0.23 V Push-Pull, I OL = 3 mA, 2X Drive -- 0.06 0.11 V Open Drain, I OL = 3 mA, 1X Drive -- 0.08 0.15 V Open Drain, I OL = 3 mA, 2X Drive -- 0.04 0.08 V Open Drain NMOS 4X, I OL = 3 mA -- 0.02 0.04 V IOH HIGH-Level Output Pulse Current (see Note 1) Push-Pull, V OH = 2.4 V, 1X Drive 6.05 12.08 -- mA PMOS OD, V OH = 2.4 V, 1X Drive 6.05 12.08 -- mA Push-Pull, V OH = 2.4 V, 2X Drive 11.54 24.16 -- mA PMOS OD, V OH = 2.4 V, 2X Drive 11.52 24.16 -- mA IOL LOW-Level Output Pulse Current (see Note 1) Push-Pull, V OL = 0.4 V, 1X Drive 4.88 8.24 -- mA Push-Pull, V OL = 0.4 V, 2X Drive 9.75 16.49 -- mA Open Drain, V OL = 0.4 V, 1X Drive 7.31 12.37 -- mA Open Drain, V OL = 0.4 V, 2X Drive 14.54 24.74 -- mA Open Drain NMOS 4X, V OL = 0.4 V 31.32 41.06 -- mA IVDD Maximum Average or DC Current Through V DD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T

© 2023 Renesas Electronics Corporation Page 8 of 175 SLG46534 Revision 1.18 VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- V DD V TSU Startup Time From V DD rising past PON THR 0.61 1.24 1.65 ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.41 1.54 1.66 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 1.00 1.15 1.31 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.4 Electrical Characteristics (5 V ±10% V DD )

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 2.68 -- V DD V Logic Input with Schmitt Trigger 3.34 -- V DD V Low-Level Logic Input 1.15 -- V DD V VIL LOW-Level Input Voltage Logic Input 0 -- 1.96 V Logic Input with Schmitt Trigger 0 -- 1.41 V Low-Level Logic Input 0 -- 0.77 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.44 0.90 1.38 V I LGK Input leakage (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage Push-Pull, I OH = 5 mA, 1X Drive 4.15 4.76 -- V PMOS OD, I OH = 5 mA, 1X Drive 4.16 4.76 -- V Push-Pull, I OH = 5 mA, 2X Drive 4.32 4.89 -- V PMOS OD, I OH = 5 mA, 2X Drive 4.33 4.89 -- V VOL LOW-Level Output Voltage Push-Pull, I OL = 5 mA, 1X Drive -- 0.19 0.24 V Push-Pull, I OL =5 mA, 2X Drive -- 0.09 0.12 V Open Drain, I OL = 5 mA, 1X Drive -- 0.12 0.16 V Open Drain, I OL = 5 mA, 2X Drive -- 0.07 0.08 V Open Drain NMOS 4X, I OL = 5 mA -- 0.03 0.05 V IOH HIGH-Level Output Pulse Current (see Note 1) Push-Pull, V OH = 2.4 V, 1X Drive 22.08 34.04 -- mA PMOS OD, V OH = 2.4 V, 1X Drive 22.08 34.04 -- mA Push-Pull, V OH = 2.4 V, 2X Drive 41.76 68.08 -- mA PMOS OD, V OH = 2.4 V, 2X Drive 41.69 68.08 -- mA IOL LOW-Level Output Pulse Current (see Note 1) Push-Pull, V OL = 0.4 V, 1X Drive 7.22 11.58 -- mA Push-Pull, V OL = 0.4 V, 2X Drive 13.83 23.16 -- mA Open Drain, V OL = 0.4 V, 1X Drive 10.82 17.38 -- mA Open Drain, V OL = 0.4 V, 2X Drive 17.34 34.76 -- mA Open Drain NMOS 4X, V OL = 0.4 V 41.06 55.18 -- mA IVDD Maximum Average or DC Current Through V DD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T

5.5 I2C Specifications

Maximal Voltage Applied to any PIN in High-Impedance State -- -- V DD V TSU Startup Time From V DD rising past PON THR 0.60 1.23 1.61 ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.41 1.54 1.66 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 1.00 1.15 1.31 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit tI Input Filter Spike Suppression (SCL, SDA) V ns VDD = 3.3 V ± 10% 95 VDD = 5.0 V ± 10 % 111 tBUF Bus Free Time between Stop and Start V Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.6 Asynchronous State Machine (ASM) Specifications

5.7 IDD Estimator

Table 1. ASM Specifications Table 2. Typical Current Estimated for Each Macrocell at T = 25°C

5.8 Timing Estimator

5.9 Typical Counter/Delay Offset Measurements

Table 3. Typical Delay Estimated for Each Macrocell at T = 25°C Table 4. Typical Counter/Delay Offset Measurements

5.10 Expected Delays and Widths

5.11 Typical Pulse Width Performance

2 MHz either 35 14 10 ns

Table 5. Expected Delays and Widths (typical) Table 6. Typical Pulse Width Performance at T = 25°C

5.12 OSC Specifications

Table 7. 25 kHz RC OSC0 frequency limits Table 8. 25 kHz RC OSC0 frequency error (error calculated relative to nominal value)

Table 9. 2 MHz RC OSC0 frequency limits Table 10. 2 MHz RC OSC0 frequency error (error calculated relative to nominal value)

Table 11. 25 MHz RC OSC1 frequency limits Table 12. 25 MHz RC OSC1 frequency error (error calculated relative to nominal value)

5.12.3 OSC Power On delay

Table 13. Oscillators Power On delay at room temperature, DLY/CNT Counter data = 100; RC OSC power setting: "Auto Table 14. Oscillators Power On delay at room temperature, DLY/CNT Counter data = 100; RC OSC power setting: "Auto

5.13 ACMP Specifications

Table 15. ACMP Specifications

© 2023 Renesas Electronics Corporation Page 19 of 175 SLG46534 Revision 1.18 VHYS Built-in Hysteresis VHYS = 25 mV VIL = Vin - V HYS /2 VIH = Vin + V HYS /2 LB - Enabled, T = 25°C 7.32 -- 35.5 mV LB - Disabled, T = 25°C 10.0 -- 38.5 mV VHYS = 50 mV VIL = Vin - V HYS VIH = V HYS LB - Enabled, T = 25°C 42.9 -- 57.8 mV LB - Disabled, T = 25°C 44.2 -- 54.3 mV VHYS = 200 mV VIL = Vin - V HYS VIH = V HYS LB - Enabled, T = 25°C 192.7 -- 208.7 mV LB - Disabled, T = 25°C 193.3 -- 204.8 mV VHYS = 25 mV VIL = Vin - V HYS /2 VIH = Vin + V HYS /2 LB - Enabled, LB - Disabled, VHYS = 50 mV VIL = Vin - V HYS VIH = V HYS LB - Enabled, LB - Disabled, VHYS = 200 mV VIL = Vin - V HYS VIH = V HYS LB - Enabled, LB - Disabled, Rsin Series Input Resistance Gain = 1x -- 100.0 -- ΜΩ Gain = 0.5x -- 1.0 -- ΜΩ Gain = 0.33x -- 0.8 -- ΜΩ Gain = 0.25x -- 1.0 -- ΜΩ PROP Propagation Delay, Response Time Low Bandwidth - Enable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 50 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 50 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 50 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 50 mV Low to High, High to Low, Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

© 2023 Renesas Electronics Corporation Page 20 of 175 SLG46534 Revision 1.18 PROP Propagation Delay, Response Time Low Bandwidth - Enable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 250 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 250 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 250 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 250 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 600 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 600 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 600 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 600 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 850 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 850 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 850 mV Low to High, High to Low, Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

© 2023 Renesas Electronics Corporation Page 21 of 175 SLG46534 Revision 1.18 PROP Propagation Delay, Response Time Low Bandwidth - Disable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 850 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 1200 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (1.71..3.3)V, Overdrive = 5 mV, Vref = 1200 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 1200 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, V DD = (3.3..5.5)V, Overdrive = 5 mV, Vref = 1200 mV Low to High, High to Low, G Gain error (including threshold and internal Vref error), T = (-40…+85)°C G = 1, V DD = 1.71 V Vref = 50…1200 mV -- 1 -- Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

© 2023 Renesas Electronics Corporation Page 22 of 175 SLG46534 Revision 1.18 Vref Internal Vref error, Vref = 1200 mV V DD = 1.8 V ± 5 % V DD = 3.3 V ± 10 % V DD = 5.0 V ± 10 % Internal Vref error, Vref = 1000 mV V DD = 1.8 V ± 5 % V DD = 3.3 V ± 10 % V DD = 5.0 V ± 10 % Internal Vref error, Vref = 500 mV V DD = 1.8 V ± 5 % V DD = 3.3 V ± 10 % V DD = 5.0 V ± 10 % Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

6.0 Summary of Macrocell Function

6.1 IO Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain Outputs
Push Pull Outputs
Analog IO
10 k Ω /100 k Ω /1 M Ω pull-up/pull-down resistors
40 mA Open Drain 4X Drive output

6.2 Connection Matrix

Digital matrix for circuit connections based on us er design

6.3 Analog Comparators (3 total)

Selectable hysteresis 0 mV / 25 mV / 50 mV / 200 m V
Wake and Sleep Control (Part of Combination Functi on Macrocell)

6.4 Voltage Reference

Used for references on Analog Comparators

6.5 Combination Function Macrocells (19 total)

Three Selectable DFF/Latch or 2-bit LUTs
Five Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
One Selectable Programmable Pattern Generator or 2 -bit LUT
Five Selectable 8-bit CNT/DLY or 3-bit LUT
Two Selectable 16-bit CNT/DLY or 4-bit LUT or Wake and Sleep Controller
Two Deglitch Filters with Edge Detectors

6.6 Asynchronous State Machine

Eight States
Flexible input logic from state transitions

6.7 Serial Communications

I 2C Protocol compliant

6.8 Pipe Delay (Part of Combination Function Macrocell)

16 stage / 3 output
One 1 stage fixed output
Two 1-16 stage selectable outputs

6.9 Programmable Delay

125 ns/250 ns/375 ns/500 ns @ 3.3 V
Includes Edge Detection function

6.10 RC Oscillator

25 kHz and 2 MHz selectable frequency
25 MHz RC Oscillator
First stage divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
Second stage divider for 25 kHz and 2 MHz (5): Output to Matrix: OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, OSC/64

6.11 Crystal Oscillator

6.12 Eight byte RAM + OTP User Memory

RAM Memory space that is readable and writable via I

7.0 IO Pins

The SLG46534 has a total of 12 multi-function IO pi ns which can function as either a user defined Inpu t or Output, as well as serving as a special function, or serving as a signal for programming of the on-chip Non Volatile Memory (NVM). Refer to Section 2.0 Pin Description for normal and programming modepin definitions. Normal Mode pin definitions are as follows:

Pin 1: V DD power supply
Pin 2: general purpose input
Pin 3: general purpose input or output
Pin 4: general purpose input or output or analog c omparator 0(+)
Pin 5: general purpose input or output with OE or analog comparator 0(-)
Pin 6: general purpose input or OD output SCL
Pin 7: general purpose input or OD output SDA
Pin 8: general purpose input or output with OE or analog comparator 1(+)
Pin 9: ground
Pin 10: general purpose input or output or analog comparator 0/1/2(-)
Pin 11: general purpose input or output with OE
Pin 12: general purpose input or output with OE
Pin 13: general purpose input or output or external clock input for OSC0 25 kHz/2 MHz
Pin 14: general purpose input or output or externa l clock input for OSC1 25 MHz Programming Mode pin definitions are as follows:
Pin 1: V DD power supply
Pin 2: V PP programming voltage
Pin 6: Programming SCL
Pin 7: Programming SDA
Pin 9: ground
Pin 12: programming mode control Of the 12 user defined IO pins on the SLG46534, all but one of the pins (Pin 2) can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin.

7.1 Input Modes

Each IO pin can be configured as a digital input pi n with/without buffered Schmitt Trigger, or can als o be configured as a low voltage digital input. Pins 4, 5, 8 and10 can also be configured to serve as analog inputs to the on-chip comparators.

7.2 Output Modes

Pins 3, 4, 5, 6, 7, 8, 10, 11, 12, 13 and 14 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All IO pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k Ω , 100 k Ω and 1 M Ω . In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other IO pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 IO Register Settings

7.4.1 PIN 2 Register Settings PIN 4 Register Settings PIN 6 Register Settings

Table 16. PIN 2 Register Settings Table 17. PIN 3 Register Settings Table 18. PIN 4 Register Settings

7.4.2 PIN 5 Register Settings

Table 19. PIN 5 Register Settings

7.4.3 PIN 6 Register Settings

7.4.4 PIN 7 Register Settings

Table 20. PIN 6 Register Settings Table 21. PIN 7 Register Settings

7.4.5 PIN 8 Register Settings

7.4.6 PIN 10 Register Settings

Table 22. PIN 8 Register Settings Table 23. PIN 10 Register Settings

7.4.7 PIN 11 Register Settings

7.4.8 PIN 12 Register Settings

Table 24. PIN 11 Register Settings Table 25. PIN 12 Register Settings

7.4.9 PIN 13 Register Settings

7.4.10 PIN 14 Register Settings

Table 26. PIN 13 Register Settings Table 27. PIN 14 Register Settings

7.5 GPI Structure

7.5.1 GPI Structure (for Pin 2)

Figure 2. PIN 2 GPI Structure Diagram

7.6 Matrix OE IO Structure

7.6.1 Matrix OE IO Structure (for Pins 5, 11, 12)

Figure 3. Matrix OE IO Structure Diagram

7.6.2 Matrix OE IO Structure (for Pins 6 and 7)

Figure 4. Matrix OE IO Structure Diagram

7.6.3 Matrix OE 4X Drive Structure (for Pin 8)

Figure 5. Matrix OE IO 4X Drive Structure Diagram

Figure 6. IO 4X Drive Structure Diagram

7.7 IO Structure

7.7.1 IO Structure (for Pins 3, 4, 13, 14)

Figure 7. IO Structure Diagram

8.0 Connection Matrix

Ground. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines. For a complete list of the SLG46534’s register table, see Section 21.0 Appendix A - SLG46534 Register Definition. Figure 8. Connection Matrix Figure 9. Connection Matrix Example

8.1 Matrix Input Table

Table 28. Matrix Input Table

0 Ground 0 0 0 0 0 0

1 Pin2 Digital Input 0 0 0 0 0 1

2 Reserved 0 0 0 0 1 0

3 Pin3 Digital Input 0 0 0 0 1 1

4 Reserved 0 0 0 1 0 0

5 Pin4 Digital Input 0 0 0 1 0 1

6 Pin5 Digital Input 0 0 0 1 1 0

7 Pin8 Digital Input 0 0 0 1 1 1

8 LUT2_0 / DFF0 Output 0 0 1 0 0 0

9 LUT2_1 / DFF1 Output 0 0 1 0 0 1

10 LUT2_2 / DFF2 Output 0 0 1 0 1 0

11 LUT2_3 / PGEN Output 0 0 1 0 1 1

12 LUT3_0 / DFF3 Output 0 0 1 1 0 0

13 LUT3_1 / DFF4 Output 0 0 1 1 0 1

14 LUT3_2 / DFF5 Output 0 0 1 1 1 0

15 LUT3_3 / DFF6 Output 0 0 1 1 1 1

16 LUT3_4 / DFF7 Output 0 1 0 0 0 0

17 LUT3_5 / CNT_DLY2(8bit) Output 0 1 0 0 0 1

18 LUT3_6 / CNT_DLY3(8bit) Output 0 1 0 0 1 0

19 LUT3_7 / CNT_DLY4(8bit) Output 0 1 0 0 1 1

20 LUT3_8 / CNT_DLY5(8bit) Output 0 1 0 1 0 0

21 LUT3_9 / CNT_DLY6(8bit) Output 0 1 0 1 0 1

22 LUT4_0 / CNT_DLY0(16bit) Output 0 1 0 1 1 0

23 LUT4_1 / CNT_DLY1(16bit) Output 0 1 0 1 1 1

24 LUT3_10 / Pipe Delay (1st stage) Output 0 1 1 0 0 0

25 Pipe Delay Output0 0 1 1 0 0 1

26 Pipe Delay Output1 0 1 1 0 1 0

27 Internal OSC Pre-Divided by 1/2/4/8 Output and Post-Divided by

28 Internal OSC Pre-Divided by 1/2/4/8 Output and Post-Divided by

29 Internal OSC Pre-Divided by 1/2/4/8 Output (25MHz ) 0 1 1 1 0 1

30 Filter0 / Edge Detect0 Output 0 1 1 1 1 0

31 Filter1 / Edge Detect1 Output 0 1 1 1 1 1

32 Pin6 Digital or I2C_virtual_0 Input 1 0 0 0 0 0

33 Pin7 Digital or I2C_virtual_1 Input 1 0 0 0 0 1

34 I2C_virtual_2 Input 1 0 0 0 1 0

35 I2C_virtual_3 Input 1 0 0 0 1 1

36 I2C_virtual_4 Input 1 0 0 1 0 0

37 I2C_virtual_5 Input 1 0 0 1 0 1

38 I2C_virtual_6 Input 1 0 0 1 1 0

39 I2C_virtual_7 Input 1 0 0 1 1 1

40 ASM-stateX-dout0 1 0 1 0 0 0

41 ASM-stateX-dout1 1 0 1 0 0 1

42 ASM-stateX-dout2 1 0 1 0 1 0

43 ASM-stateX-dout3 1 0 1 0 1 1

44 ASM-stateX-dout4 1 0 1 1 0 0

45 ASM-stateX-dout5 1 0 1 1 0 1

46 ASM-stateX-dout6 1 0 1 1 1 0

47 ASM-stateX-dout7 1 0 1 1 1 1

48 Pin10 Digital Input 1 1 0 0 0 0

49 Reserved 1 1 0 0 0 1

50 Pin11 Digital Input 1 1 0 0 1 0

51 Reserved 1 1 0 0 1 1

52 Pin12 Digital Input 1 1 0 1 0 0

53 Pin13 Digital Input 1 1 0 1 0 1

54 Reserved 1 1 0 1 1 0

55 Reserved 1 1 0 1 1 1

56 Pin14 Digital Input 1 1 1 0 0 0

57 ACMP_0 Output 1 1 1 0 0 1

58 ACMP_1 Output 1 1 1 0 1 0

59 ACMP_2 Output 1 1 1 0 1 1

60 Reserved 1 1 1 1 0 0

61 Programmable Delay with Edge Detector Output 1 1 1 1 0 1

8.2 Matrix Output Table

Table 29. Matrix Output Table

8.3 Connection Matrix Virtual Inputs

As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macroce lls on the device. Eight of the Connection Matrix inputs have the special ch aracteristic that the state of these signal lines c omes from a corresponding data bit written as a register value via I 2C. This gives the user the ability to write data vi a the serial channel, and have this information translated into signals that can be dri ven into the Connection Matrix and from the Connect ion Matrix to the digital inputs of other macrocells on the device. The I 2C address for reading and writing these register values is at byte 0244. Six of the eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I 2C write command to these register bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values from a previous write command (if that has happened). Two of the eight Connection Matrix Virtual Inputs are shared with Pin digital inputs,(Pin6 Digital or I2C_virtual_0 Input) and (Pin7 Digital or I2C_virtual_1 Input). If the virtual input mode is selected, an I 2C write command to these register bits will set the signal values going into the Connection Matrix to the desi red state. A read command to these register bits wi ll read either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values from a previous write command (if that has happened). Two register bits select whether the Connection Matrix input comes from the pin input or from the virtual register:

reg <1074> Select SCL & Virtual Input 0 or PIN6
reg <1082> Select SDA & Virtual Input 1 or PIN7 See table below for Connection Matrix Virtual Inputs.

8.4 Connection Matrix Virtual Outputs

The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via I 2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output. The I 2C addresses for reading these register values are at bytes 0240 to 0247. Write commands to these same register values will be ignored (with the exception of the Virtual Input register bits at byte 0244). Matrix Input Number Matrix Input Signal Function Register Bit Addresses (d)

32 I2C_virtual_0 Input reg<1952>

33 I2C_virtual_1 Input reg<1953>

34 I2C_virtual_2 Input reg<1954>

35 I2C_virtual_3 Input reg<1955>

36 I2C_virtual_4 Input reg<1956>

37 I2C_virtual_5 Input reg<1957>

38 I2C_virtual_6 Input reg<1958>

39 I2C_virtual_7 Input reg<1959>

9.0 Combination Function Macrocells

Three macrocells that can serve as either 2-bit LU Ts or as D Flip Flops;
Five macrocells that can serve as either 3-bit LUT s or as D Flip Flops with Set/Reset Input;
One macrocell that can serve as either 3-bit LUT o r as Pipe Delay;
One macrocell that can serve as either 2-bit LUT o r as Programmable Pattern Generator (PGEN);
Five macrocells that can serve as either 3-bit LUT s or as 8-Bit Counter / Delays;
Two macrocells that can serve as either 4-bit LUTs or as 16-Bit Counter / Delays. Inputs/Outputs for the 17 combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). 9.1 2-Bit LUT or D Flip Flop Macrocells There are three macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implem ent LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, whic h goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (D) and clock (clk) inputs for the Flip Flop, with the output going back to the connection matrix. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change. Latch: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High)

Figure 10. 2-bit LUT0 or DFF0

created within each of the two 2-bit LUT logic cells. Table 33. 2-bit LUT Standard Digital Functions Table 30. 2-bit LUT0 Truth Table Table 31. 2-bit LUT1 Truth Table Table 32. 2-bit LUT2 Truth Table

Table 34. DFF0 Register Settings Table 35. DFF1 Register Settings Table 36. DFF2 Register Settings

9.2 Initial Polarity Operations

Figure 13. DFF Polarity Operations

Figure 14. 3-bit LUT0 or DFF3 with RST/SET

Figure 25. 3-bit LUT17 or DFF14 with RST/SET

Table 37. 3-bit LUT0 Truth Table Table 38. 3-bit LUT1 Truth Table Table 39. 3-bit LUT2 Truth Table Table 40. 3-bit LUT3 Truth Table Table 41. 3-bit LUT4 Truth Table Table 42. 3-bit LUT11 Truth Table Table 43. 3-bit LUT12 Truth Table Table 44. 3-bit LUT13 Truth Table

created within each of the six 3-bit LUT logic cells. Table 49. 3-bit LUT Standard Digital Functions Table 45. 3-bit LUT14 Truth Table Table 46. 3-bit LUT15 Truth Table Table 47. 3-bit LUT16 Truth Table Table 48. 3-bit LUT17 Truth Table

Table 50. DFF3 Register Settings Table 51. DFF4 Register Settings

Table 52. DFF5 Register Settings Table 53. DFF6 Register Settings Table 54. DFF7 Register Settings

9.4 Initial Polarity Operations

Figure 26. DFF Polarity Operations with nReset

Figure 27. DFF Polarity Operations with nSet

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. for OUT0 and reg <1263:1260> for OUT1. The 16-input mux is used to select the amount of delay. be the total time delay of the Pipe Delay logic cell. Note: CLK is rising edge triggered. Figure 28. 3-bit LUT10 or Pipe Delay

16 Flip-Flops nRST

1 Pipe OUT

Table 56. Pipe Delay Register Settings Table 55. 3-bit LUT10 Truth Table

These macrocells can also operate in a one-shot mode, which will generate an output pulse of user-defined width. These macrocells can also operate in a frequency detection or edge detection mode. Data via I2C for further details. Figure 29. 3-bit LUT5 or CNT/DLY2

Table 57. 3-bit LUT5 Truth Table Table 58. 3-bit LUT6 Truth Table Table 59. 3-bit LUT7 Truth Table Table 60. 3-bit LUT8 Truth Table Table 61. 3-bit LUT9 Truth Table

Table 62. CNT/DLY2 Register Settings Table 63. CNT/DLY3 Register Settings

Table 64. CNT/DLY4 Register Settings Table 65. CNT/DLY5 Register Settings

Table 66. CNT/DLY6 Register Settings

© 2023 Renesas Electronics Corporation Page 73 of 175 SLG46534 Revision 1.18 9.7 4-Bit LUT or 16-Bit Counter / Delay Macrocells There are two macrocells that can serve as either 4-bit LUTs or as 16-bit Counter / Delays. When used to implement LUT function, the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, whi ch goes back into the Connection Matrix. When used to implement 16-Bit Counter / Delay function, four input signals from the connection matrix go to the external clock (ext_clk), reset (DLY_in/CNT_Res et), Keep and Up for the counter/delay, with the ou tput going back to the connection matrix. These two macrocells have an optional Finite State Machine (FSM) function. There are two matrix inputs for Up and Keep to support FSM functionality. Any counter within Green PAK is counting down by default. In FSM mode (CNT/DLY0 and CNT/DLY1) it is possible to reverse counting by applying High level to Up input. Also, there is a possibility to pause counting by applying High level to Keep input, after the level goes Low, the counter will proceed counting. These macrocells can also operate in a one-shot mode, which will generate an output pulse of user-defined width. These macrocells can also operate in a frequency detection. Delay time and Output Period can be calculated using the following formulas:

Delay time: [(Counter data + 2) / CLK input freque ncy – Offset*];
Output Period: [(Counter data + 1) / CLK input fre quency – Offset*]. One Shot pulse width can be calculated using formula:
Pulse width = [(Counter Data + 2) / CLK input freq uency – Offset*]; *Offset is the asynchronous time offset between the input signal and the first clock pulse. For timing diagrams refer to section 9.8 CNT/DLY/FSM Timing Diagrams. Note: Counters initialize with counter data after POR Both of these macrocells can have their active count value read via I 2C. See Section 19.5.1.2 Reading Counter Data via I2C for further details.

Figure 34. 4-bit LUT0 or CNT/DLY0

Figure 35. 4-bit LUT1 or CNT/DLY1

Table 69. 4-bit LUT Standard Digital Functions Table 67. 4-bit LUT0 Truth Table. Table 68. 4-bit LUT1 Truth Table.

Table 70. CNT/DLY0 Register Settings Table 71. CNT/DLY1 Register Settings

9.8 CNT/DLY/FSM Timing Diagrams

Figure 36. Delay Mode Timing Diagram Figure 37. Counter Mode Timing Diagram

diagram shows one-shot function for non-inverted output. Figure 38. One-Shot Function Timing Diagram

not restart while pulse is high. second rising edge has not come after the last rising edge in specified time. second falling edge has not come after the last falling edge in specified time. the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come. Table 72. DLY/CNTx One-Shot / Freq. Detect Output Polarity

Figure 39. Frequency Detection Mode Timing Diagram

Figure 40. Edge Detection Mode Timing Diagram

shorter than the delay time. Figure 41. Delay Mode Timing Diagram

9.8.7 CNT/FSM Mode CNT/DLY0, CNT/DLY1

Figure 42. CNT/FSM Timing Diagram (reset rising edge mode, oscillator is forced on, UP = 0) for counter data = 3 Figure 43. CNT/FSM Timing Diagram (set rising edge mode, oscillator is forced on, UP = 0) for counter data = 3

9.8.8 Difference in Counter Value for Counter, Delay, One-Shot and Frequency Detect Modes

two rising edges of the clock signal in Delay/One-Shot/Frequency Detect modes compared to Counter mode. See Figure 46. a Look Up Table (LUT), or Programmable Pattern Generator (PGEN). pattern repeats. See figure Figure 48. Figure 46. Counter Value, Counter Data = 3

9.10 Wake and Sleep controller (WS)

selected bit of 16-bit counter.

ACMP Power Up Input from matrix = 1 (for each ACMP separately);
CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPs);
Register WS => enable (for each ACMP separately);
CNT/DLY0 set/reset input = 0 (for all ACMPs);
In case of using OSC1 (25 MHz), OSC0 must be set t o Force Power On. As the OSC any oscillator with any pre divider can be used. The user can select a period of time while the ACMPs are sleeping in a range of 1 - 65535 clock cycles. Before they are sent to sleep their outputs are latched so the ACMPs remain their state (High or Low) while sleeping. WS controller has the following settings:
Wake and Sleep Output State (High/Low) If OSC is powered off (Power Down option is selected; power down input = 1) and Wake and Sleep Output State = High, the ACMP is continuously on.

Figure 49. WS controller

© 2023 Renesas Electronics Corporation Page 89 of 175 SLG46534 Revision 1.18 If OSC is powered off (Power Down option is selected; power down input = 1) and Wake and Sleep Output State = Low, the ACMP is continuously off. Both cases WS function is turned off.

Counter Data (Range: 1 - 65535) User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS counter will reset to zero and High level signal on its output will turn the ACMPs on. When Reset signal goes out, the WS counter will go Low and turn the ACMPs off until the counter counts up to the end Set - when active signal appears, the WS counter will stop and Low level signal on its output will turn the ACMPs off. When Set signal goes out, the WS counter will go on counting and High level signal will turn the ACMPs on while counter is counting up to the end.
Edge Select defines the edge for Q mode High level Set/Reset - switches mode Set/Reset when level is High Note: Q mode operates only in case of "High Level Set/Reset”.
Wake time selection - time required for wake signa l to turn the ACMPs on Normal Wake Time - when WS signal is High, it takes a BG time (100/550 µs) to turn the ACMPs on They w ill stay on until WS signal is Low again. Wake time is one clock peri od. It should be longer than BG turn on time and mi nimal required comparing time of the ACMP . Short Wake Time - when WS signal is High, it takes a BG time (100/550 µs) to turn the ACMPs on. They will stay on for 1 µs and turn off regardless of WS signal. The WS signal width does not matter.
Keep - pauses counting while Keep = 1
Up - reverses counting If Up = 1, CNT is counting up from user selected value to 65535. If Up = 0, CNT is counting down from user selected value to 0.

9.10.1 WS Register Settings

Table 73. WS Register Settings

10.0 Analog Comparators (ACMP)

powered down, output is low. PWR UP = 1 => ACMP is powered up. PWR UP = 0 => ACMP is powered down. enable the ACMPs with the POR signal, and not the VDD signal. Note: Regulator and Charge Pump set to automatic ON/OFF . Figure 50. Maximum Power On Delay vs. V DD ,

be Vref + hysteresis/2 (high threshold) and Vref – hysteresis/2 (low threshold). Force BandGap option is set as Disabled. Table 74. Gain Divider Input Resistance Table 75. Gain Divider Accuracy Buffer Bandwidth = 1 kHz, Vhys = 0 mV, Gain = 1.

Note: when V DD < 1.8V voltage reference should not exceed 1100 mV. Figure 54. Typical Input Threshold Variation (including Vref variation, ACMP offset) vs. Table 76. Built-in Hysteresis Tolerance at T = 25°C

10.1 ACMP0 Block Diagram

Figure 55. ACMP0 Block Diagram

10.2 ACMP0 Register Settings

Table 77. ACMP0 Register Settings

10.3 ACMP1 Block Diagram

Figure 56. ACMP1 Block Diagram

10.4 ACMP1 Register Settings

Table 78. ACMP1 Register Settings

10.5 ACMP2 Block Diagram

Figure 57. ACMP2 Block Diagram

10.6 ACMP2 Register Settings

Table 79. ACMP2 Register Settings

11.0 Pipe Delay (PD)

The SLG46534 has a pipe delay logic cell that is shared with the 3-bit LUT10 in one of the Combination Function macrocells. The user can select one of these functions to use in a design, but not both. Please see Section 9.5 3-Bit LUT or Pipe Delay Macrocell for the description of this Combination Function macrocell.

12.0 Programmable Delay / Edge Detector

Note : The input signal must be longer than the delay, otherwise it will be filtered out.

12.1 Programmable Delay Timing Diagram - Edge Detector Output

Figure 58. Programmable Delay Figure 59. Edge Detector Output

12.2 Programmable Delay Register Settings

Table 80. Programmable Delay Register Settings

13.0 Additional Logic Functions

are two deglitch filters, each with edge detector functions. See section 5.11 Typical Pulse Width Performance .

13.1 Deglitch Filter / Edge Detector

13.2 Deglitch Filter Register Settings

Figure 60. Deglitch Filter / Edge Detector Table 81. Programmable Delay Register Settings

14.0 Voltage Reference (VREF)

14.1 Voltage Reference Overview

see Figure 61. below, which shows the reference output structure.

14.2 VREF Selection Table

Table 82. VREF Selection Table

11101 PIN 5: ACMP0(-)/2 PIN 10: ACMP1(-)/2 PIN 11: AC MP2(-)/2

11100 PIN 10: ACMP0(-)/2 PIN 10: ACMP1(-)/2 PIN 10: A CMP2(-)/2

11011 PIN 5: ACMP0(-) PIN 10: ACMP1(-) PIN 11: ACMP2(- )

11010 PIN 10: ACMP0(-) PIN 10: ACMP1(-) PIN 10: ACMP2 (-)

11001 V DD / 4 V DD / 4 V DD / 4

11000 V DD / 3 V DD / 3 V DD / 3

14.3 VREF Block Diagram

Figure 61. Voltage Reference Block Diagram

15.0 RC Oscillator (RC Osc)

The SLG46534 has three internal oscillators. RC Osc illator that runs at 25 kHz / 2 MHz (OSC0), Oscilla tor that runs at 25 MHz (OSC1) and Crystal Oscillator. It is possible to use all three oscillators simultaneously. The fundamental frequency can also come from clock input (Pin 14 for 25 kHz / 2 MHz and Pin 13 for 25 MHz or Crystal OSC), see section 20.0 External Clocking. 15.1 25 kHz/2 MHz and 25 MHz RC Oscillators There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix Input lines. The predivider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. The second stage divider (only for 25 kHz / 2 MHz Oscillator) has an input of freq uency from the predivider, and outputs one of seven different frequencies on Connection Matrix Input lines <27> (OUT0) and <28> (OUT1). See Figure 62. and Figure 63. below for details. There are two modes of the POWER CONTROL pin, (reg<1658> for 25 kHz / 2 MHz OSC and reg<1657> for 25 MHz OSC):

POWER DOWN <0> . If PWR CONTROL input of oscillator is LOW, the oscillator will be turned on. If PWR CONTROL input of oscillator is HIGH the oscillator will be turned off and OSC divider will reset.
FORCE ON <1> . If PWR CONTROL input of oscillator is HIGH, the oscillator will be turned on. If PWR CONTROL input of oscillator is LOW the oscillator will be turned off. The PWR CONTROL signal has the highest priority. The SLG46534 has a 25 kHz / 2 MHz OSC FAST START-UP function reg<1338> (1 – on, 0 – off). It allows th e OSC to run immediately after power-up. Start-up time is less t han one cycle. Note that when OSC FAST START-UP is on, the current consumption will rise. The user can select two OSC POWER MODEs (reg<1343 for 25 kHz / 2 MHz OSC and reg<1341> for 25 MHz OSC):
If AUTO POWER ON <0> is selected, the OSC will run only when any macrocell that uses OSC is powered on.
If FORCE POWER ON <1> is selected, the OSC will run when the SLG46534 is powered on. OSC can be turned on by:
Register control (force power on)
Delay mode, when delay requires OSC
CNT/FSM

Figure 62. 25 kHz / 2 MHz RC OSC Block Diagram Figure 63. 25 MHz RC OSC Block Diagram

25 MHz Osc

15.2 Oscillator Power On delay

Note 1: OSC power mode: "Auto Power On”. Note 2: ‘OSC enable’ signal appears when any macrocell that uses OSC is powered on. Figure 64. Oscillator Startup Diagram Figure 65. RC Oscillator Maximum Power On Delay vs. V

15.3 Oscillator Accuracy

Note 1: OSC power setting: Force Power On; Clock to matrix input - enable; Bandgap: turn on by register - enable. Note 2: For more information see section 5.12 OSC Specifications. Figure 66. RC Oscillator Maximum Power On Delay vs. V Figure 67. OSC1 (25 MHz) Maximum Power On Delay vs. V DD at 85°C

Note: 25 MHz RC OSC1 performance is not guaranteed at V DD < 2.5 V. Figure 70. OSC1 (25 MHz) Frequency vs. Temperature

16.0 Crystal Oscillator

recommended by the manufacturer can be used. longer rise and fall delays may result in more duty cycle skew for higher frequency clocks. Figure 71. Crystal OSC Block Diagram Figure 72. External Crystal Connection Table 83. External Components Selection Table

17.0 Power On Reset (POR)

The SLG46534 has a power-on reset (POR) macrocell t o ensure correct device initialization and operatio n of all macrocells in the device. The purpose of the POR circuit is to ha ve consistent behavior and predictable results when the V DD power is first ramping to the device, and also while the V DD is falling during power-down. To accomplish this g oal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the IO pins.

17.1 General Operation

The SLG46534 is guaranteed to be powered down and nonoperational when the V DD voltage (voltage on PIN1) is less than Power Off Threshold (see in Electrical Characteristics ta ble), but not less than -0.6 V. Another essential c ondition for the chip to be powered down is that no voltage higher (see Note 1) than the V DD voltage is applied to any other PIN. For example, if V DD voltage is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46534, the voltage applied on the V DD should be higher than the Power_ON threshold (see voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the V DD voltage rises to the Power_ON threshold. After the POR sequence has started, the SLG46534 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. Note 2. The Power_ON threshold is defined in Electrical Characteristics table. To power down the chip the V DD voltage should be lower than the operational and t o guarantee that chip is powered down it should be less than Power Off Threshold. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the V DD , this rule also applies to the case when the chip is powered on.

17.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 73. . DD value, temperature and even will vary from chip to chip (process influence). Figure 73. POR sequence

17.3 Macrocells Output States During POR Sequence

states during the POR sequence ( Figure 74. describes the output signals states). last are output PINs that become active and determined by the input signals. Figure 74. Internal Macrocell States during POR sequence

17.3.1 Initialization

Input PINs, ACMP , pull up/down;
DFFs, Delays/Counters, Pipe Delay;
Output PIN corresponds to the internal logic.

The POR signal going high indicates the mentioned power-up sequence is complete. input PIN.There is no effect from input pin when input voltage is applied at the same time as V DD .

17.3.2 Power Down

during a slow rampdown, outputs can possibly switch state during this time. Figure 75. Power Down

1 V VREF Out Signal

18.0 Asynchronous State Machine (ASM) Macrocell

18.1 ASM Macrocell Overview

will cause transitions from one state to another state, as shown in Figure 76. . inputs, 24 are user selectable for driving general state transitions, and 1 is for driving a state transition to an Initial / Reset state. state when active, shown in red, in the Figure 76. . For more details refer to section 18.2 ASM Inputs . RAM. For more details refer to section 18.3 ASM Outputs . signals are properly processed, and state transitions are deterministic. The GPAK Designer development tools support user de signs for the ASM macrocell at both the physical le vel and logic level. Figure 76. is a representation of the user design at the logi cal level, and Figure 77. shows the physical resources inside the a physical mapping of the input and outputs required for the desired functionality. Figure 76. Asynchronous State Machine State Transitions

Figure 77. Asynchronous State Machine

18.2 ASM Inputs

selectable for driving general state transitions, and 1 is for driving a state transition to an Initial / Reset state. inputs is level sensitive, and active high. A high level input will trigger a state transition. user can select going into a particular state to be 3, shown in Figure 79. . have transitions going from a state to all other states, shown in Figure 80. . state within the ASM Editor inside GPAK Designer is the initial state. Figure 78. Asynchronous State Machine Inputs

18.3 ASM Outputs

8 bits per state. The values loaded in each of the 8 bits define the signal level on each of the 8 ASM macrocell outputs. Figure 81. Connection Matrix Output RAM

must be in reset all the time. Table 84. ASM Editor - Connection Matrix Output RAM

18.4 Basic ASM Timing

and Figure 83. . The time from a valid input signal to the time th at there is a valid change of state and valid signa ls being

and the longest state transition (input on matrix output and output on matrix input).

No clock source is needed, it reacts only to input signals
The input signals do not have to be synchronized to each other, the macrocell will react to the earliest valid signal for state
This macrocell does not have traditional set-up and hold time specifications which are related to incoming clock, as this

macrocell has no clock source.

The macrocell only consumes power while in state transition.

18.6 ASM Power Considerations

and Figure 84. below, the current consumption of the macrocell will be a fraction of a µA between state transitions, and will

rise only during state transitions. See Section 5.7 IDD Estimator to find average current during state transitions. Figure 82. State Transition Figure 83. State Transition Timing Figure 84. State Transition

18.8 ASM Special Case Timing Considerations

18.8.1 State Transition Pulse Input Timing

that does meet minimum pulse width. Figure 85. State Transition Timing and Power Consumption Figure 86. State Transition Figure 87. State Transition Pulse Input Timing

18.8.2 State Transition Competing Input Timing

There will be situations where two input signals can be valid inputs that will drive two different state transitions from a given state. signal satisfies the pulse width criteria described in the paragraph above, as shown in Figure 90. . Figure 88. State Transition - Competing Inputs Figure 89. State Transition Timing - Competing Inputs Indeterminate Figure 90. State Transition Timing - Competing Inputs Determinable

18.8.3 ASM State Transition Sequential Timing

example of this sequential behavior is shown in Figure 91. and the associated timing is shown in Figure 92. .

18.8.4 State Transition Closed Cycling

Figure 93. involves cycling between two states, but any numbe r of two – eight states can be included in state tr ansition closed cycling of this nature. Figure 94. shows the associated timing for closed cycling. Figure 91. State Transition - Sequential Figure 92. State Transition - Sequential Timing Figure 93. State Transition - Closed Cycling Figure 94. State Transition - Closed Cycling Timing

19.0 I2C Serial Communications Macrocell

19.1 I2C Serial Communications Macrocell Overview

to route signals in the manner most appropriate for the user’s application. the device, giving an I 2C bus Master the capability to remotely read the current value of any macrocell. section 19.5 I2C Serial Command Register Protection for more details on I 2C read/write memory protection. Note: GreenPAK I 2C is fully compatible with standard I 2C protocol.

19.2 I2C Serial Communications Device Addressing

by an Acknowledge bit (ACK), which is sent by this device to indicate successful communication of the Control Byte data. addressing and implementation of these special functions, to ensure reliable operation. for all commands to the SLG46534. Address. Figure 95. shows this basic command structure. Figure 95. Basic Command Structure

19.3 I2C Serial General Timing

be found in the AC Characteristics section.

19.4.1 Byte Write Command

that the SLG46534 generates the Acknowledge bit. Figure 96. I2C General Timing Characteristics Figure 97. Byte Write Command, R/W = 0

19.4.2 Sequential Write Command

generates the Acknowledge bit.

19.4.3 Current Address Read Command

for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition. Figure 98. Sequential Write Command, R/W = 0 Figure 99. Current Address Read Command, R/W = 1

19.4.4 Random Read Command

R/W bit set to “1”, after which the SLG46534 issues an Acknowledge bit, followed by the requested eight data bits.

19.4.5 Sequential Read Command

read. The Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition. Figure 100. Random Read Command Figure 101. Sequential Read Command

19.4.6 I2C Serial Command Register Map

unless protection bits are set to prevent this.

reg<1832> I 2C lock for read bits <1535:0> (Bank 0/1/2). If the system provides any read commands to the addresses in these three banks, the device will respond with ‘FFH’ in data field.
reg<1871> I 2C lock for write bits <1535:0> (Bank 0/1/2). If the system provides any write commands to the addresses in these three banks, the device will acknowledge these commands, but will not do internal writes to the register space.
reg<1870> I 2C lock for write all bits (Bank 0/1/2/3). If the system provides any write commands to the addresses in these four banks, the device will acknowledge these commands, but will not do internal writes to the register space. Note 1. reg<1870> is higher priority than reg<1871>, and if reg<1870> is set, than reg<1871> does not have any effect. Note 2. If the user sets Pins 8 and 9 function to a selection other than SDA and SCL, all access via I2C will be disabled. If reg <1870> is not set, register bits in Bank 3 are open to read and write commands via I 2C with the following exceptions:
reg<1871> Bank 0/1/2 I 2C-write protection bit is always protected from I 2C write
reg<1867:1864> I 2C Control Code Bit [3:0] is always protected from I2C write Note 4. Any write commands that come to the device via I 2C that are not blocked, based on the protection bit s, will change the contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and a POR event will restore the register bits to original programmed contents of the NVM. See Section 21.0 Appendix A - SLG46534 Register Definition for detailed information on all registers.

Figure 102. Register Bank Map

19.5.1 Register Read/Write Protection

There are six read/write protect modes for the design sequence from being corrupted or copied. See Table 85 for details.. Table 85. Read/Write Protection Options

1833 Reserved R R R R R R

1832 I2C Lock for read

1871 I 2C Lock for write

1870 I2C Lock for write all

19.5.1.1 I2C Serial Reset Command

2C Serial Reset Command is not available during emulation.

Figure 103. Reset Command Timing

19.5.1.2 Reading Counter Data via I 2C

16-bit CNT0 and CNT1, and 8-bit counters CNT4 and CNT6.

19.5.1.3 User RAM and OTP Memory Array

and the highest order byte in this array is located at I 2C address 0xDF. Table 86. RAM Array Table

20.0 External Clocking

The SLG46534 supports several ways to use an external, higher accuracy clock as a reference source for internal operations

20.1 Crystal Mode

When reg<1136> is set to 1, an external crystal can be connected to pins 12 and 13 for supplying an accurate clock source. See section 16.0 Crystal Oscillator. An external clocking signal on pin 13 can be used in place of the crystal. The high and low limits for crystal frequency that can be selected are 32.768 kHz and 40 MHz.

20.2 Pin 14 Source for 25 KHz / 2 MHz Clock

When reg<1358> is set to 1, an external clocking signal on pin 14 will be routed in place of the internal RC oscillator derived 25 kHz/2 MHz clock source. See Figure 62. . The high and low limits for external frequency that can be selected are 0 MHz and 77 MHz.

20.3 Pin 13 Source for 25 MHz Clock

When reg<1357> is set to 1, an external clocking signal on pin 13 will be routed in place of the internal RC oscillator derived 25 MHz clock source. See Figure 63. . The high and low limits for external frequency that can be selected are 0 MHz and 84 MHz.

21.0 Appendix A - SLG46534 Register Definition

Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write Note: For reg<0> to reg<1495>, I 2C Read is valid (assuming reg <1832> = 0), I 2C Write is valid (assuming reg <1871> = 0) Matrix 64-to-1 MUX's 6 selection bits 00 reg<5:0> Matrix OUT ASM-state0-EN0 Valid Valid reg<7:6> Reserved Valid Valid 01 reg<13:8> Matrix OUT ASM-state0-EN1 Valid Valid reg<15:14> Reserved Valid Valid 02 reg<21:16> Matrix OUT ASM-state0-EN2 Valid Valid reg<23:22> Reserved Valid Valid 03 reg<29:24> Matrix OUT ASM-state1-EN0 Valid Valid reg<31:30> Reserved Valid Valid 04 reg<37:32> Matrix OUT ASM-state1-EN1 Valid Valid reg<39:38> Reserved Valid Valid 05 reg<45:40> Matrix OUT ASM-state1-EN2 Valid Valid reg<47:46> Reserved Valid Valid 06 reg<53:48> Matrix OUT ASM-state2-EN0 Valid Valid reg<55:54> Reserved Valid Valid 07 reg<61:56> Matrix OUT ASM-state2-EN1 Valid Valid reg<63:62> Reserved Valid Valid 08 reg<69:64> Matrix OUT ASM-state2-EN2 Valid Valid reg<71:70> Reserved Valid Valid 09 reg<77:72> Matrix OUT ASM-state3-EN0 Valid Valid reg<79:78> Reserved Valid Valid 0A reg<85:80> Matrix OUT ASM-state3-EN1 Valid Valid reg<87:86> Reserved Valid Valid 0B reg<93:88> Matrix OUT ASM-state3-EN2 Valid Valid reg<95:94> Reserved Valid Valid 0C reg<101:96> Matrix OUT ASM-state4-EN0 Valid Valid reg<103:102> Reserved Valid Valid 0D reg<109:104> Matrix OUT ASM-state4-EN1 Valid Valid reg<111:110> Reserved Valid Valid 0E reg<117:112> Matrix OUT ASM-state4-EN2 Valid Valid reg<119:118> Reserved Valid Valid 0F reg<125:120> Matrix OUT ASM-state5-EN0 Valid Valid reg<127:126> Reserved Valid Valid 10 reg<133:128> Matrix OUT ASM-state5-EN1 Valid Valid reg<135:134> Reserved Valid Valid 11 reg<141:136> Matrix OUT ASM-state5-EN2 Valid Valid reg<143:142> Reserved Valid Valid 12 reg<149:144> Matrix OUT ASM-state6-EN0 Valid Valid reg<151:150> Reserved Valid Valid

© 2023 Renesas Electronics Corporation Page 141 of 175 SLG46534 Revision 1.18 13 reg<157:152> Matrix OUT ASM-state6-EN1 Valid Valid reg<159:158> Reserved Valid Valid 14 reg<165:160> Matrix OUT ASM-state6-EN2 Valid Valid reg<167:166> Reserved Valid Valid 15 reg<173:168> Matrix OUT ASM-state7-EN0 Valid Valid reg<175:174> Reserved Valid Valid 16 reg<181:176> Matrix OUT ASM-state7-EN1 Valid Valid reg<183:182> Reserved Valid Valid 17 reg<189:184> Matrix OUT ASM-state7-EN2 Valid Valid reg<191:190> Reserved Valid Valid 18 reg<197:192> Matrix OUT ASM-state-RSTB Valid Valid reg<199:198> Reserved Valid Valid 19 reg<205:200> Reserved Valid Valid reg<207:206> Reserved Valid Valid 1A reg<213:208> Reserved Valid Valid reg<215:214> Reserved Valid Valid 1B reg<221:216> Matrix OUT PIN3 Digital Output Source Val id Valid reg<223:222> Reserved Valid Valid 1C reg<229:224> Reserved Valid Valid reg<231:230> Reserved Valid Valid 1D reg<237:232> Reserved Valid Valid reg<239:238> Reserved Valid Valid 1E reg<245:240> Matrix OUT PIN4 Digital Output Source Val id Valid reg<247:246> Reserved Valid Valid 1F reg<253:248> Matrix OUT PIN5 Digital Output Source Val id Valid reg<255:254> Reserved Valid Valid 20 reg<261:256> Matrix OUT PIN5 Output Enable Valid Valid reg<263:262> Reserved Valid Valid 21 reg<269:264> Matrix OUT PIN6 Digital Output Source (SCL with VI/In - put & NMOS open-drain) Valid Valid reg<271:270> Reserved Valid Valid 22 reg<277:272> Matrix OUT PIN7 Digital Output Source (SDA with VI/Input & NMOS open-drain) Valid Valid reg<279:278> Reserved Valid Valid 23 reg<285:280> Matrix OUT PIN8 Digital Output Source Val id Valid reg<287:286> Reserved Valid Valid 24 reg<293:288> Matrix OUT PIN8 Output Enable Valid Valid reg<295:294> Reserved Valid Valid 25 reg<301:296> Matrix OUT PIN10 Digital Output Source Va lid Valid reg<303:302> Reserved Valid Valid 26 reg<309:304> Reserved Valid Valid reg<311:310> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 142 of 175 SLG46534 Revision 1.18 27 reg<317:312> Reserved Valid Valid reg<319:318> Reserved Valid Valid 28 reg<325:320> Matrix OUT PIN11 Digital Output Source Va lid Valid reg<327:326> Reserved Valid Valid 29 reg<333:328> Matrix OUT PIN11 Output Enable Valid Valid reg<335:334> Reserved Valid Valid 2A reg<341:336> Reserved Valid Valid reg<343:342> Reserved Valid Valid 2B reg<349:344> Matrix OUT PIN12 Digital Output Source Va lid Valid reg<351:350> Reserved Valid Valid 2C reg<357:352> Matrix OUT PIN12 Output Enable Valid Valid reg<359:358> Reserved Valid Valid 2D reg<365:360> Matrix OUT PIN13 Digital Output Source Va lid Valid reg<367:366> Reserved Valid Valid 2E reg<373:368> Reserved Valid Valid reg<375:374> Reserved Valid Valid 2F reg<381:376> Reserved Valid Valid reg<383:382> Reserved Valid Valid 30 reg<389:384> Reserved Valid Valid reg<391:390> Reserved Valid Valid 31 reg<397:392> Reserved Valid Valid reg<399:398> Reserved Valid Valid 32 reg<405:400> Matrix OUT PIN14 Digital Output Source Va lid Valid reg<407:406> Reserved Valid Valid 33 reg<413:408> Matrix OUT ACMP0 PDB (Power Down) Valid Va lid reg<415:414> Reserved Valid Valid 34 reg<421:416> Matrix OUT ACMP1 PDB (Power Down) Valid Va lid reg<423:422> Reserved Valid Valid 35 reg<429:424> Matrix OUT ACMP2 PDB (Power Down) Valid Va lid reg<431:430> Reserved Valid Valid 36 reg<437:432> Reserved Valid Valid reg<439:438> Reserved Valid Valid 37 reg<445:440> Matrix OUT Input of Filter_0 with fixed time edge detec - tor Valid Valid reg<447:446> Reserved Valid Valid 38 reg<453:448> Matrix OUT Input of Filter_1 with fixed time edge detec - tor Valid Valid reg<455:454> Reserved Valid Valid 39 reg<461:456> Matrix OUT Input of Programmable Delay & Edge De - tector Valid Valid reg<463:462> Reserved Valid Valid 3A reg<469:464> Matrix OUT OSC 25KHz/2MHz PDB (Power Dow n) Valid Valid reg<471:470> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 143 of 175 SLG46534 Revision 1.18 3B reg<477:472> Matrix OUT OSC 25MHz PDB (Power Down) Val id Valid reg<479:478> Reserved Valid Valid 3C reg<485:480> Matrix OUT IN0 of LUT2_0 or Clock Input of DFF0 Valid Valid reg<487:486> Reserved Valid Valid 3D reg<493:488> Matrix OUT IN1 of LUT2_0 or Data Input o f DFF0 Valid Valid reg<495:494> Reserved Valid Valid 3E reg<501:496> Matrix OUT IN0 of LUT2_1 or Clock Input of DFF1 Valid Valid reg<503:502> Reserved Valid Valid 3F reg<509:504> Matrix OUT IN1 of LUT2_1 or Data Input o f DFF1 Valid Valid reg<511:510> Reserved Valid Valid 40 reg<517:512> Matrix OUT IN0 of LUT2_2 or Clock Input of DFF2 Valid Valid reg<519:518> Reserved Valid Valid 41 reg<525:520> Matrix OUT IN1 of LUT2_2 or Data Input o f DFF2 Valid Valid reg<527:526> Reserved Valid Valid 42 reg<533:528> Matrix OUT IN0 of LUT2_3 or Clock Input of PGEN Valid Valid reg<535:534> Reserved Valid Valid 43 reg<541:536> Matrix OUT IN1 of LUT2_3 or RSTB of PGEN Valid Valid reg<543:542> Reserved Valid Valid 44 reg<549:544> Matrix OUT IN0 of LUT3_0 or Clock Input of DFF3 Valid Valid reg<551:550> Reserved Valid Valid 45 reg<557:552> Matrix OUT IN1 of LUT3_0 or Data Input o f DFF3 Valid Valid reg<559:558> Reserved Valid Valid 46 reg<565:560> Matrix OUT IN2 of LUT3_0 or RSTB (SETB) of DFF3 Valid Valid reg<567:566> Reserved Valid Valid 47 reg<573:568> Matrix OUT IN0 of LUT3_1 or Clock Input of DFF4 Valid Valid reg<575:574> Reserved Valid Valid 48 reg<581:576> Matrix OUT IN1 of LUT3_1 or Data Input o f DFF4 Valid Valid reg<583:582> Reserved Valid Valid 49 reg<589:584> Matrix OUT IN2 of LUT3_1 or RSTB (SETB) of DFF4 Valid Valid reg<591:590> Reserved Valid Valid 4A reg<597:592> Matrix OUT IN0 of LUT3_2 or Clock Input of DFF5 Valid Valid reg<599:598> Reserved Valid Valid 4B reg<605:600> Matrix OUT IN1 of LUT3_2 or Data Input o f DFF5 Valid Valid reg<607:606> Reserved Valid Valid 4C reg<613:608> Matrix OUT IN2 of LUT3_2 or RSTB (SETB) of DFF5 Valid Valid reg<615:614> Reserved Valid Valid 4D reg<621:616> Matrix OUT IN0 of LUT3_3 or Clock Input of DFF6 Valid Valid reg<623:622> Reserved Valid Valid 4E reg<629:624> Matrix OUT IN1 of LUT3_3 or Data Input o f DFF6 Valid Valid reg<631:630> Reserved Valid Valid 4F reg<637:632> Matrix OUT IN2 of LUT3_3 or RSTB (SETB) of DFF6 Valid Valid reg<639:638> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 144 of 175 SLG46534 Revision 1.18 50 reg<645:640> Matrix OUT IN0 of LUT3_4 or Clock Input of DFF7 Valid Valid reg<647:646> Reserved Valid Valid 51 reg<653:648> Matrix OUT IN1 of LUT3_4 or Data Input o f DFF7 Valid Valid reg<655:654> Reserved Valid Valid 52 reg<661:656> Matrix OUT IN2 of LUT3_4 or RSTB (SETB) of DFF7 Valid Valid reg<663:662> Reserved Valid Valid 53 reg<669:664> Matrix OUT IN0 of LUT3_5 or Delay2 Input (or Counter2 RST Input) Valid Valid reg<671:670> Reserved Valid Valid 54 reg<677:672> Matrix OUT IN1 of LUT3_5 or External Clock Input of Delay2 (or Counter2) Valid Valid reg<679:678> Reserved Valid Valid 55 reg<685:680> Matrix OUT IN2 of LUT3_5 Valid Valid reg<687:686> Reserved Valid Valid 56 reg<693:688> Matrix OUT IN0 of LUT3_6 or Delay3 Input (or Counter3 RST Input) Valid Valid reg<695:694> Reserved Valid Valid 57 reg<701:696> Matrix OUT IN1 of LUT3_6 or External Clock Input of Delay3 (or Counter3) Valid Valid reg<703:702> Reserved Valid Valid 58 reg 709:704> Matrix OUT IN2 of LUT3_6 Valid Valid reg<711:710> Reserved Valid Valid 59 reg<717:712> Matrix OUT IN0 of LUT3_7 or Delay4 Input (or Counter4 RST Input) Valid Valid reg<719:718> Reserved Valid Valid 5A reg<725:720> Matrix OUT IN1 of LUT3_7 or External Clock Input of Delay4 (or Counter4) Valid Valid reg<727:726> Reserved Valid Valid 5B reg<733:728> Matrix OUT IN2 of LUT3_7 Valid Valid reg<735:734> Reserved Valid Valid 5C reg<741:736> Matrix OUT IN0 of LUT3_8 or Delay5 Input (or Counter5 RST Input) Valid Valid reg<743:742> Reserved Valid Valid 5D reg<749:744> Matrix OUT IN1 of LUT3_8 or External Clock Input of Delay5 (or Counter5) Valid Valid reg<751:750> Reserved Valid Valid 5E reg<757:752> Matrix OUT IN2 of LUT3_8 Valid Valid reg<759:758> Reserved Valid Valid 5F reg<765:760> Matrix OUT IN0 of LUT3_9 or Delay6 Input (or Counter6 RST Input) Valid Valid reg<767:766> Reserved Valid Valid 60 reg<773:768> Matrix OUT IN1 of LUT3_9 or External Clock Input of Delay6 (or Counter6) Valid Valid reg<775:774> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 145 of 175 SLG46534 Revision 1.18 61 reg<781:776> Matrix OUT IN2 of LUT3_9 Valid Valid reg<783:782> Reserved Valid Valid 62 reg<789:784> Matrix OUT IN0 of LUT3_10 or Input of Pi pe Delay Valid Valid reg<791:790> Reserved Valid Valid 63 reg<797:792> Matrix OUT IN1 of LUT3_10 or RSTB of Pip e Delay Valid Valid reg<799:798> Reserved Valid Valid 64 reg<805:800> Matrix OUT IN2 of LUT3_10 or Clock of Pi pe Delay Valid Valid reg<807:806> Reserved Valid Valid 65 reg<813:808> Matrix OUT IN0 of LUT4_0 or Delay0 Input (or Counter0 RST/SET Input) Valid Valid reg<815:814> Reserved Valid Valid 66 reg<821:816> Matrix OUT IN1 of LUT4_0 or External Clock Input of Delay0 (or Counter0) Valid Valid reg<823:822> Reserved Valid Valid 67 reg<829:824> Matrix OUT IN2 of LUT4_0 or UP Input of FSM0 Valid Valid reg<831:830> Reserved Valid Valid 68 reg<837:832> Matrix OUT IN3 of LUT4_0 or KEEP Input o f FSM0 Valid Valid reg<839:838> Reserved Valid Valid 69 reg<845:840> Matrix OUT IN0 of LUT4_1 or Delay1 Input (or Counter1 RST/SET Input) Valid Valid reg<847:846> Reserved Valid Valid 6A reg<853:848> Matrix OUT IN1 of LUT4_1 or External Clock Input of Delay1 (or Counter1) Valid Valid reg<855:854> Reserved Valid Valid 6B reg<861:856> Matrix OUT IN2 of LUT4_1 or UP Input of FSM1 Valid Valid reg<863:862> Reserved Valid Valid 6C reg<869:864> Matrix OUT IN3 of LUT4_1 or KEEP Input o f FSM1 Valid Valid reg<871:870> Reserved Valid Valid 6D reg<877:872> Matrix OUT PD of crystal oscillator by reg<1268> Valid Valid reg<879:878> Reserved Valid Valid 6E reg<887:880> Reserved Valid Valid 6F reg<895:888> Reserved Valid Valid 70 reg<903:896> Reserved Valid Valid 71 reg<911:904> Reserved Valid Valid 72 reg<919:912> Reserved Valid Valid 73 reg<927:920> Reserved Valid Valid 74 reg<935:928> Reserved Valid Valid 75 reg<943:936> Reserved Valid Valid 76 reg<951:944> Reserved Valid Valid 77 reg<959:952> Reserved Valid Valid 78 reg<967:960> Reserved Valid Valid 79 reg<975:968> Reserved Valid Valid 7A reg<983:976> Reserved Valid Valid 7B reg<991:984> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 146 of 175 SLG46534 Revision 1.18 7C reg<999:992> Reserved Valid Valid 7D reg<1007:1000> Reserved Valid Valid 7E reg<1015:1008> Reserved Valid Valid 7F reg<1023:1016> Reserved Valid Valid PIN 2 reg<1024> Reserved Valid Valid reg<1025> Reserved Valid Valid reg<1027:1026> Reserved Valid Valid reg<1029:1028> PIN2 Pull Down Resistor Value Selection 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1031:1030> PIN2 Mode Control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Valid Valid Reserved reg<1032> Reserved reg<1033> Reserved reg<1035:1034> Reserved reg<1037:1036> Reserved reg<1039:1038> Reserved PIN 3 reg<1040> Reserved Valid Valid reg<1041> PIN3 Driver Strength Selection 0: 1X 1: 2X Valid Valid reg<1042> PIN3 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1044:1043> PIN3 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1047:1045> PIN3 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved Valid Valid Reserved reg<1048> Reserved reg<1049> Reserved reg<1051:1050> Reserved reg<1053:1052> Reserved reg<1055:1054> Reserved Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 147 of 175 SLG46534 Revision 1.18 PIN 4 reg<1056> Reserved Valid Valid reg<1057> PIN4 Driver Strength Selection 0: 1X 1: 2X Valid Valid reg<1058> PIN4 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1060:1059> PIN4 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1063:1061> PIN4 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input/Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain Valid Valid PIN 5 reg<1064> Reserved Valid Valid reg<1065> PIN5 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1067:1066> PIN5 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1069:1068> PIN5 Mode Control (sig_pin5_oe = 0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output Valid Valid reg<1071:1070> PIN5 Mode Control (sig_pin5_oe = 1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Valid Valid PIN 6 reg<1072> Reserved Valid Valid reg<1073> IO6 Driver Strength Selection 0: 1X 1: 2X Valid Valid reg<1074> Select SCL & Virtual Input 0 or PIN6 0: SCL & Virtual Input 0 1: PIN6 Valid Valid reg<1076:1075> PIN6 Pull Down Resistor Value Selection 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid 86 reg<1079:1077> PIN6 (or SCL) Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger, 010: Low Voltage Digital Input 011: Reserved 100: Reserved 101: Open Drain NMOS 110: Reserved 111: Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 148 of 175 SLG46534 Revision 1.18 PIN 7 reg<1080> Reserved Valid Valid reg<1081> PIN7 (or SDA) Driver Strength Selection 0: 1X (I 2C up to 400 KHz) 1: 2X (I 2C up to 1 MHz) Valid Valid reg<1082> Select SDA & Virtual Input 1 or PIN7 0: SDA & Virtual Input 1 1: PIN7 Valid Valid reg<1084:1083> PIN7 Pull Down Resistor Value Selection 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1087:1085> PIN7 (or SDA) Mode Control (input mode is selected by register at SDA, output mode is fixed as OD at SDA) 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Reserved 101: Open Drain NMOS 110: Reserved 111: Reserved Valid Valid PIN 8 reg<1088> PIN8 4X Drive (4X, NMOS Open Drain) Se - lection 0: 4X Drive OFF 1: 4X Drive ON (if sig_pin8_oe = '1' & PIN8 Mode Control = '1X') Valid Valid reg<1089> PIN8 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1091:1090> PIN8 Pull Up/Down Resistor Value Selection 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1093:1092> PIN8 Mode Control (sig_pin8_oe = 0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output Valid Valid reg<1095:1094> PIN8 Mode Control (sig_pin8_oe = 1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 149 of 175 SLG46534 Revision 1.18 PIN 10 reg<1096> PIN10 4X Drive (4X, NMOS Open Drain) Se - lection 0: 4X Drive OFF (Default) 1: 4X Drive ON (if PIN10 Mode Control = '101') Valid Valid reg<1097> PIN10 Driver Strength Selection 0: 1X 1: 2X Valid Valid reg<1098> PIN10 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1100:1099> PIN10 Pull Up/Down Resistor Value Selec - tion 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1103:1101> PIN10 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input/Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain Valid Valid Reserved reg<1104> Reserved reg<1105> Reserved reg<1107:1106> Reserved reg<1109:1108> Reserved reg<1111:1110> Reserved PIN 11 reg<1112> Reserved Valid Valid reg<1113> PIN11 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1115:1114> PIN11 Pull Up/Down Resistor Value Selec - tion 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1117:1116> PIN11 Mode Control (sig_pin11_oe = 0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Valid Valid reg<1119:1118> PIN11 Mode Control (sig_pin11_oe = 1) 00: Push Pull 1X 01: Push Pull 2X 10: Reserved 11: Reserved Valid Valid Reserved reg<1120> Reserved reg<1121> Reserved reg<1122> Reserved reg<1124:1123> Reserved reg<1127:1125> Reserved Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 150 of 175 SLG46534 Revision 1.18 PIN 12 reg<1128> Reserved Valid Valid reg<1129> PIN12 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1131:1130> PIN12 Pull Up/Down Resistor Value Selec - tion 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1133:1132> PIN12 Mode Control (sig_pin12_oe = 0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Valid Valid reg<1135:1134> PIN12 Mode Control (sig_pin12_oe = 1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Valid Valid PIN 13 reg<1136> X1 & X2 for crystal OSC enable 0: Disable 1: Enable Valid Valid reg<1137> PIN13 Driver Strength Selection 0: 1X 1: 2X Valid Valid reg<1138> PIN13 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1140:1139> PIN13 Pull Up/Down Resistor Value Selec - tion 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1143:1141> PIN13 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Sel for XOSC (X1) 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved Valid Valid Reserved reg<1144> Reserved reg<1145> Reserved reg<1147:1146> Reserved reg<1149:1148> Reserved reg<1151:1150> Reserved Reserved reg<1152> Reserved reg<1153> Reserved reg<1155:1154> Reserved reg<1157:1156> Reserved reg<1159:1158> Reserved Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 151 of 175 SLG46534 Revision 1.18 PIN 14 reg<1160> Reserved Valid Valid reg<1161> PIN14 Driver Strength Selection 0: 1X 1: 2X Valid Valid reg<1162> PIN14 Pull Up/Down Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1164:1163> PIN14 Pull Up/Down Resistor Value Selec - tion 00: Floating 01: 10 K 10: 100 K 11: 1 M Valid Valid reg<1167:1165> PIN14 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved Valid Valid ACMP1 reg<1168> ACMP1 Positive Input Source Select 0: IO8 1: ACMP0 IN+ source Valid Valid reg<1169> ACMP1 Analog Buffer Enable (Max. BW 1MHz) 0: Disable analog buffer 1: Enable analog buffer Valid Valid reg<1171:1170> ACMP1 Hysteresis Enable 00: 0 mV 01: 25 mV 10: 50 mV 11: 200 mV Valid Valid ACMP0 reg<1172> ACMP0 Positive Input Source Select 0: IO4 1: V DD Valid Valid reg<1173> ACMP0 Analog Buffer Enable (Max. BW

1 MHz)

0: Disable analog buffer 1: Enable analog buffer Valid Valid reg<1175:1174> ACMP0 Hysteresis Enable 00: 0 mV 01: 25 mV 10: 50 mV 11: 200 mV Valid Valid Reserved 93 reg<1177:1176> Reserved reg<1179:1178> Reserved ACMP2 reg<1180> Reserved reg<1182:1181> ACMP2 Hysteresis Enable 00: 0 mV 01: 25 mV 10: 50 mV 11: 200 mV Valid Valid ACMP1 100 uA Current Source Enable 93 reg<1183> ACMP1 100 uA Current Source Enable 0: Disable 1: Enable Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 152 of 175 SLG46534 Revision 1.18 LUT3_x Function Select reg<1184> LUT3_3 or DFF6 with RSTB/SETB Select 0: LUT3_3 1: DFF6 with RSTB/SETB Valid Valid reg<1185> LUT3_2 or DFF5 with RSTB/SETB Select 0: LUT3_2 1: DFF5 with RSTB/SETB Valid Valid reg<1186> LUT3_1 or DFF4 with RSTB/SETB Select 0: LUT3_1 1: DFF4 with RSTB/SETB Valid Valid reg<1187> LUT3_0 or DFF3 with RSTB/SETB Select (Two consecutive DFFs if reg<1471> = 1 for SM) 0: LUT3_0 1: DFF3 with RSTB/SETB Valid Valid LUT2_x Function Select reg<1188> LUT2_3 or PGEN Select 0: LUT2_3 1: PGEN Valid Valid reg<1189> LUT2_2 or DFF2 Select 0: LUT2_2 1: DFF2 Valid Valid reg<1190> LUT2_1 or DFF1 Select 0: LUT2_1 1: DFF1 Valid Valid reg<1191> LUT2_0 or DFF0 Select 0: LUT2_0 1: DFF0 Valid Valid LUT4_x Function Select reg<1192> LUT4_1 or DLY/CNT1(16bits) Select 0: LUT4_1 1: DLY/CNT1(16bits) Valid Valid reg<1193> LUT4_0 or DLY/CNT0(16bits) Select 0: LUT4_0 1: DLY/CNT0(16bits) Valid Valid LUT3_x Function Select reg<1194> LUT3_9 or DLY/CNT6(8bits) Select 0: LUT3_9 1: DLY/CNT6(8bits) Valid Valid reg<1195> LUT3_8 or DLY/CNT5(8bits) Select 0: LUT3_8 1: DLY/CNT5(8bits) Valid Valid reg<1196> LUT3_7 or DLY/CNT4(8bits) Select 0: LUT3_7 1: DLY/CNT4(8bits) Valid Valid reg<1197> LUT3_6 or DLY/CNT3(8bits) Select 0: LUT3_6 1: DLY/CNT3(8bits) Valid Valid reg<1198> LUT3_5 or DLY/CNT2(8bits) Select 0: LUT3_5 1: DLY/CNT2(8bits) Valid Valid reg<1199> LUT3_4 or DFF7 with RSTB/SETB Select 0: LUT3_4 1: DFF7 with RSTB/SETB Valid Valid LUT2_1 / DFF1 reg<1200> LUT2_1 <0> Valid Valid reg<1201> LUT2_1 <1> / DFF1 Initial Polarity Select 0: Low 1: High Valid Valid reg<1202> LUT2_1 <2> / DFF1 Output Select 0: Q output 1: QB output Valid Valid reg<1203> LUT2_1 <3> / DFF1 or Latch Select 0: DFF function 1: Latch function Valid Valid LUT2_0 / DFF0 96 reg<1204> LUT2_0 <0> Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 153 of 175 SLG46534 Revision 1.18 reg<1205> LUT2_0 <1> / DFF0 Initial Polarity Select 0: Low 1: High Valid Valid reg<1206> LUT2_0 <2> / DFF0 Output Select 0: Q output 1: QB output Valid Valid reg<1207> LUT2_0 <3> / DFF0 or Latch Select 0: DFF function 1: Latch function Valid Valid LUT2_3 / PGEN 97 reg<1211:1208> LUT2_3<3:0> or PGEN 4bit counter da - ta<3:0> Valid Valid LUT2_2 / DFF2 reg<1212> LUT2_2 <0> Valid Valid reg<1213> LUT2_2 <1> / DFF2 Initial Polarity Select 0: Low 1: High Valid Valid reg<1214> LUT2_2 <2> / DFF2 Output Select 0: Q output 1: QB output Valid Valid reg<1215> LUT2_2 <3> / DFF2 or Latch Select 0: DFF function 1: Latch function Valid Valid LUT3_0 / DFF3 reg<1219:1216> LUT3_0 <3:0> Valid Valid reg<1220> LUT3_0 <4> / DFF3 Initial Polarity Select 0: Low 1: High Valid Valid reg<1221> LUT3_0 <5> / DFF3 RSTB or SETB Select 0: RSTB from Matrix Output 1: SETB from Matrix Output Valid Valid reg<1222> LUT3_0 <6> / DFF3 Output Select 0: Q output 1: QB output Valid Valid reg<1223> LUT3_0 <7> / DFF3 or Latch Select 0: DFF function 1: Latch function Valid Valid LUT3_1 / DFF4 reg<1227:1224> LUT3_1 <3:0> Valid Valid reg<1228> LUT3_1 <4> / DFF4 Initial Polarity Select 0: Low 1: High Valid Valid reg<1229> LUT3_1 <5> / DFF4 RSTB or SETB Select 0: RSTB from Matrix Output 1: SETB from Matrix Output Valid Valid reg<1230> LUT3_1 <6> / DFF4 Output Select 0: Q output 1: QB output Valid Valid reg<1231> LUT3_1 <7> / DFF4 or Latch Select 0: DFF function 1: Latch function Valid Valid LUT3_2 / DFF5 reg<1235:1232> LUT3_2 <3:0> Valid Valid reg<1236> LUT3_2 <4> / DFF5 Initial Polarity Select 0: Low 1: High Valid Valid reg<1237> LUT3_2 <5> / DFF5 RSTB or SETB Select 0: RSTB from Matrix Output 1: SETB from Matrix Output Valid Valid reg<1238> LUT3_2 <6> / DFF5 Output Select 0: Q output 1: QB output Valid Valid 9A reg<1239> LUT3_2 <7> / DFF5 or Latch Select 0: DFF function 1: Latch function Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 154 of 175 SLG46534 Revision 1.18 LUT3_3 / DFF6 reg<1243:1240> LUT3_3 <3:0> Valid Valid reg<1244> LUT3_3 <4> / DFF6 Initial Polarity Select 0: Low 1: High Valid Valid reg<1245> LUT3_3 <5> / DFF6 RSTB or SETB Select 0: RSTB from Matrix Output 1: SETB from Matrix Output Valid Valid reg<1246> LUT3_3 <6> / DFF6 Output Select 0: Q output 1: QB output Valid Valid reg<1247> LUT3_3 <7> / DFF6 or Latch Select 0: DFF function 1: Latch function Valid Valid LUT3_4 / DFF7 reg<1251:1248> LUT3_4 <3:0> Valid Valid reg<1252> LUT3_4 <4> / DFF7 Initial Polarity Select 0: Low 1: High Valid Valid reg<1253> LUT3_4 <5> / DFF7 RSTB or SETB Select 0: RSTB from Matrix Output 1: SETB from Matrix Output Valid Valid reg<1254> LUT3_4 <6> / DFF7 Output Select 0: Q output 1: QB output Valid Valid reg<1255> LUT3_4 <7> / DFF7 or Latch Select 0: DFF function 1: Latch function Valid Valid LUT3_10 / Pipe Delay 9D reg<1259:1256> LUT3_10 <3:0> / Pipe Delay OUT0 Select Valid Valid reg<1263:1260> LUT3_10 <7:4> / Pipe Delay OUT1 Select Valid Valid reg<1265:1264> Select the Edge Mode of Programmable De - lay & Edge Detector 00: Rising Edge Detector 01: Falling Edge Detector 10: Both Edge Detector 11: Both Edge Delay Valid Valid reg<1267:1266> Delay Value Select for Programmable Delay & Edge Detector (V DD = 3.3 V, typical) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns Valid Valid reg<1269:1268> Crystal oscillator Power down enable 00: No matrix PD 01: matrix PD for crystal oscillator 10: Reserved 11: Reserved Valid Valid reg<1270> LUT3_10 or Pipe Delay Select 0: LUT3_10 1: Pipe Delay Valid Valid reg<1271> Pipe Delay OUT1 Polarity Select 0: Non-inverted 1: Inverted Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 155 of 175 SLG46534 Revision 1.18 DLY/CNT2 reg<1273:1272> DLY2 Mode Select or Asynchronous CNT2 Reset 00: On both Falling and Rising Edges (for Delay & Counter Reset) 01: on Falling Edge only (for Delay & Count - er Reset) 10: on Rising Edge only (for Delay & Count - er Reset) 11: No Delay on either Falling or Rising Edges / High Level Reset Valid Valid reg<1276:1274> DLY/CNT2 Clock Source Select 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25 MHz OSC clock 110: External Clock 111: Counter1 Overflow Valid Valid reg<1277> DLY/CNT2 Output Selection if DLY/CNT2 Mode Selection is "11" 0: Default Output 1: Edge Detector Output Valid Valid reg<1279:1278> DLY/CNT2 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNT3 reg<1281:1280> DLY3 Mode Select or Asynchronous CNT3 Reset 00: On both Falling and Rising Edges (for Delay & Counter Reset) 01: on Falling Edge only (for Delay & Count - er Reset) 10: on Rising Edge only (for Delay & Count - er Reset) 11: No Delay on either Falling or Rising Edges / High Level Reset Valid Valid reg<1284:1282> DLY/CNT3 Clock Source Select 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25 MHz OSC clock 110: External Clock 111: Counter2 Overflow Valid Valid reg<1285> DLY/CNT3 Output Selection if DLY/CNT3 Mode Selection is "11" 0: Default Output 1: Edge Detector Output Valid Valid reg<1287:1286> DLY/CNT3 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 156 of 175 SLG46534 Revision 1.18 DLY/CNT4 reg<1289:1288> DLY4 Mode Select or Asynchronous CNT4 Reset 00: On both Falling and Rising Edges (for Delay & Counter Reset) 01: on Falling Edge only (for Delay & Count - er Reset) 10: on Rising Edge only (for Delay & Count - er Reset) 11: No Delay on either Falling or Rising Edges / High Level Reset Valid Valid reg<1292:1290> DLY/CNT4 Clock Source Select 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25MHz OSC clock 110: External Clock 111: Counter3 Overflow Valid Valid reg<1293> DLY/CNT4 Output Selection if DLY/CNT4 Mode Selection is "11" 0: Default Output 1: Edge Detector Output Valid Valid reg<1295:1294> DLY/CNT4 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNT5 reg<1297:1296> DLY5 Mode Select or Asynchronous CNT5 Reset 00: On both Falling and Rising Edges (for Delay & Counter Reset) 01: on Falling Edge only (for Delay & Count - er Reset) 10: on Rising Edge only (for Delay & Count - er Reset) 11: No Delay on either Falling or Rising Edges / High Level Reset Valid Valid reg<1300:1298> DLY/CNT5 Clock Source Select 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25MHz OSC clock 110: External Clock 111: Counter4 Overflow Valid Valid reg<1301> DLY/CNT5 Output Selection if DLY/CNT5 Mode Selection is "11" 0: Default Output 1: Edge Detector Output Valid Valid reg<1303:1302> DLY/CNT5 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 157 of 175 SLG46534 Revision 1.18 DLY/CNT6 reg<1305:1304> DLY6 Mode Select or Asynchronous CNT6 Reset 00: On both Falling and Rising Edges (for Delay & Counter Reset) 01: on Falling Edge only (for Delay & Count - er Reset) 10: on Rising Edge only (for Delay & Count - er Reset) 11: No Delay on either Falling or Rising Edges / High Level Reset Valid Valid reg<1308:1306> DLY/CNT6 Clock Source Select 000: Internal OSC clock 001: OSC/4 010: OSC/12, 011: OSC/24 100: OSC/64 101: 25MHz OSC clock 110: External Clock 111: Counter5 Overflow Valid Valid reg<1309> DLY/CNT6 Output Selection if DLY/CNT6 Mode Selection is "11" 0: Default Output 1: Edge Detector Output Valid Valid reg<1311:1310> DLY/CNT6 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNT0 reg<1313:1312> DLY0 Mode Select or Asynchronous CNT0 Reset (16bits) 00: On both Falling and Rising Edges (for Delay & Counter Reset) 01: on Falling Edge only (for Delay & Count - er Reset) 10: on Rising Edge only (for Delay & Count - er Reset) 11: No Delay on either Falling or Rising Edges / High Level Reset or Set Valid Valid reg<1316:1314> DLY/CNT0 Clock Source Select (16bits) 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25MHz OSC clock 110: External Clock 111: Counter6 Overflow Valid Valid reg<1317> CNT0/FSM0's Q are Set to data or Reset to 0s Selection (16bits) 0: Reset to 0s 1: Set to data (Reg<1583:1576, 1591:1584>) Valid Valid reg<1319:1318> DLY/CNT0 Mode Selection (16bits) 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 158 of 175 SLG46534 Revision 1.18 DLY/CNT1 reg<1321:1320> DLY1 Mode Select or Asynchronous CNT1 Reset (16bits) 00: On both Falling and Rising Edges (for Delay & Counter Reset) 01: on Falling Edge only (for Delay & Count - er Reset) 10: on Rising Edge only (for Delay & Count - er Reset) 11: No Delay on either Falling or Rising Edges / High Level Reset or Set Valid Valid reg<1324:1322> DLY/CNT1 Clock Source Select (16bits) 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25MHz OSC clock 110: External Clock 111: Counter0 Overflow Valid Valid reg<1325> CNT1/FSM1's Q are Set to data or Reset to 0s Selection (16bits) 0: Reset to 0s 1: Set to data (Reg<1599:1592, 1607:1600>) Valid Valid reg<1327:1326> DLY/CNT1 Mode Selection (16bits) 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNTx One-Shot / Freq. Detect Output Polarity reg<1328> DLY/CNT0 stop & restarting enable in CNT mode when new data is loaded 0: Disable 1: Enable Valid Valid reg<1329> Select the Polarity of DLY/CNT6's One Shot / Freq. Detect Output 0: Default Output 1: Inverted Output Valid Valid reg<1330> Select the Polarity of DLY/CNT5's One Shot / Freq. Detect Output 0: Default Output 1: Inverted Output Valid Valid reg<1331> Select the Polarity of DLY/CNT4's One Shot / Freq. Detect Output 0: Default Output 1: Inverted Output Valid Valid reg<1332> Select the Polarity of DLY/CNT3's One Shot / Freq. Detect Output 0: Default Output 1: Inverted Output Valid Valid reg<1333> Select the Polarity of DLY/CNT2's One Shot / Freq. Detect Output 0: Default Output 1: Inverted Output Valid Valid reg<1334> Select the Polarity of DLY/CNT1's One Shot / Freq. Detect Output 0: Default Output 1: Inverted Output Valid Valid reg<1335> Select the Polarity of DLY/CNT0's One Shot / Freq. Detect Output 0: Default Output 1: Inverted Output Valid Valid Oscillator reg<1337:1336> OSC Clock Pre-divider for 25 MHz 00: Div1 01: Div2 10: Div4 11: Div8 Valid Valid reg<1338> OSC Fast Start-Up Enable for 25 KHz/2 MHz 0: Disable 1: Enable Valid Valid reg<1340:1339> OSC Clock Pre-divider for 25 KHz/2 MHz 00: Div1 01: Div2 10: Div4 11: Div8 Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 159 of 175 SLG46534 Revision 1.18 reg<1341> Force 25 MHz Oscillator ON 0: Auto Power ON (If any CNT/DLY use 25MHz source) 1: Force Power ON Valid Valid reg<1342> Oscillator (25 KHz: Ring OSC, 2M: RC-OSC) Select 0: 25 KHz Ring OSC 1: 2 MHz RC-OSC Valid Valid reg<1343> Force 25 KHz/2MHz Oscillator ON 0: Auto Power ON (if any CNT/DLY use 25K/2MHz source) 1: Force Power ON Valid Valid reg<1346:1344> Internal OSC 25 KHz/2 MHz Frequency Di - vider Control for matrix input <28> 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 Valid Valid reg<1349:1347> Internal OSC 25 KHz/2 MHz Frequency Di - vider Control for matrix input <27> 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 Valid Valid reg<1350> OSC Clock 25 KHz/2 MHz to matrix input <28> enable 0: Disable 1: Enable Valid Valid reg<1351> OSC Clock 25 KHz/2 MHz to matrix input <27> enable 0: Disable 1: Enable Valid Valid reg<1354:1352> ASM_reg_init<2:0> for ASM state default setup bits Valid Valid reg<1355> Reserved Reserved Valid Valid reg<1356> OSC Clock 25 MHz to matrix input <29> en - able 0: Disable 1: Enable Valid Valid reg<1357> External Clock Source Select instead of 25 MHz 0: Internal Oscillator 1: External Clock from Pin13 Valid Valid reg<1358> External Clock Source Select instead of 25 KHz/2 MHz 0: Internal Oscillator 1: External Clock from Pin14 Valid Valid reg<1359> DLY/CNT1 stop & restarting enable in CNT mode when new data is loaded 0: Disable 1: Enable Valid Valid ASM 8-to-1 MUX’s 3 selection bits AA reg<1362:1360> ASM_state0_dec8x1_EN1 Valid Valid reg<1363> Reserved Valid Valid reg<1366:1364> ASM_state0_dec8x1_EN0 Valid Valid reg<1367> Reserved Valid Valid AB reg<1370:1368> ASM_state1_dec8x1_EN0 Valid Valid reg<1371> Reserved Valid Valid reg<1374:1372> ASM_state0_dec8x1_EN2 Valid Valid reg<1375> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 160 of 175 SLG46534 Revision 1.18 AC reg<1378:1376> ASM_state1_dec8x1_EN2 Valid Valid reg<1379> Reserved Valid Valid AC reg<1382:1380> ASM_state1_dec8x1_EN1 Valid Valid reg<1383> Reserved Valid Valid AD reg<1386:1384> ASM_state2_dec8x1_EN1 Valid Valid reg<1387> Reserved Valid Valid reg<1390:1388> ASM_state2_dec8x1_EN0 Valid Valid reg<1391> Reserved Valid Valid AE reg<1394:1392> ASM_state3_dec8x1_EN0 Valid Valid reg<1395> Reserved Valid Valid reg<1398:1396> ASM_state2_dec8x1_EN2 Valid Valid reg<1399> Reserved Valid Valid AF reg<1402:1400> ASM_state3_dec8x1_EN2 Valid Valid reg<1403> Reserved Valid Valid reg<1406:1404> ASM_state3_dec8x1_EN1 Valid Valid reg<1407> Reserved Valid Valid reg<1410:1408> ASM_state4_dec8x1_EN1 Valid Valid reg<1411> Reserved Valid Valid reg<1414:1412> ASM_state4_dec8x1_EN0 Valid Valid reg<1415> Reserved Valid Valid reg<1418:1416> ASM_state5_dec8x1_EN0 Valid Valid reg<1419> Reserved Valid Valid reg<1422:1420> ASM_state4_dec8x1_EN2 Valid Valid reg<1423> Reserved Valid Valid reg<1426:1424> ASM_state5_dec8x1_EN2 Valid Valid reg<1427> Reserved Valid Valid reg<1430:1428> ASM_state5_dec8x1_EN1 Valid Valid reg<1431> Reserved Valid Valid reg<1434:1432> ASM_state6_dec8x1_EN1 Valid Valid reg<1435> Reserved Valid Valid reg<1438:1436> ASM_state6_dec8x1_EN0 Valid Valid reg<1439> Reserved Valid Valid reg<1442:1440> ASM_state7_dec8x1_EN0 Valid Valid reg<1443> Reserved Valid Valid reg<1446:1444> ASM_state6_dec8x1_EN2 Valid Valid reg<1447> Reserved Valid Valid reg<1450:1448> ASM_state7_dec8x1_EN2 Valid Valid reg<1451> Reserved Valid Valid reg<1454:1452> ASM_state7_dec8x1_EN1 Valid Valid reg<1455> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 161 of 175 SLG46534 Revision 1.18 Filter / Edge Detector reg<1457:1456> Select the edge mode of Edge Detector_1 00: Rising Edge 01: Falling Edge 10: Both Edge 11: Delay Valid Valid reg<1458> Filter_1/Edge Detector_1 output Polarity Se - lect 0: Filter_1 output 1: Filter_1 output inverted Valid Valid reg<1459> Filter_1or Edge Detector_1 Select (Typ. 30 ns @V DD = 3.3 V) 0: Filter_1 1: Edge Detector_1 Valid Valid reg<1461:1460> Select the edge mode of Edge Detector_0 00: Rising Edge 01: Falling Edge 10: Both Edge 11: Delay Valid Valid reg<1462> Filter_0/Edge Detector_0 output Polarity Se - lect 0: Filter_0 output 1: Filter_0 output inverted Valid Valid reg<1463> Filter_0 or Edge Detector_0 Select (Typ. 47 ns @V DD = 3.3 V) 0: Filter_0 1: Edge Detector_0 Valid Valid VREF / Bandgap [1464] Reserved Valid Valid [1466:1465] Bandgap OK for ACMP Output Delay Time Select, the start Time is "Resetb_core go to High" 00 or 10 with registers [1474:1472] = 100 (Wide V DD range, 1.7V ~ 5.5V): Auto-delay mode, 550 uS for V DD < 2.7V & 100 uS for 2.7 V < V DD 00 or 10 with registers [1474:1472] = X10: Always 100 uS delay for 2.7 V < V DD 00 or 10 with registers [1474:1472] = XX1: Always 550uS delay for V DD < 2.7 V, 01: Always 550us delay regardless of registers [1474:1472] & V DD , 11: Always 100 us delay with 2.7V < V DD regardless of registers [1474:1472] Valid Valid reg<1467> Reserved Valid Valid reg<1468> Reserved Valid Valid reg<1469> Reserved Valid Valid reg<1470> Reserved Valid Valid reg<1471> Two consecutive DFFs enable for SM 0: Disable 1: Enable Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 162 of 175 SLG46534 Revision 1.18 reg<1474:1472> Power divider (V DD /3, V DD /4) ON/OFF 0XX: Power divider off (if there is no use of V DD /3, V DD /4 @ ACMP negative in) 100: Reservedb X10: Reserved XX1:Reserved Valid Valid reg<1475> V DD Bypass Enable when device power is 1.8 V 0: Regulator Auto ON 1: Regulator OFF (V DD Bypass) Valid Valid reg<1476> Force Bandgap ON 0: Auto-Mode 1: Enable (if chip is Power Down, the Band - gap will Power Down even if it is Set to 1). Valid Valid reg<1477> NVM Power Down 0: None (Or Programming Enable) 1: Power Down (Or Programming Disable) Valid Valid reg<1478> Reserved Valid Valid reg<1479> GPIO Quick Charge Enable 0: Disable 1: Enable Valid Valid reg<1482:1480> Reserved Valid Valid reg<1483> Reserved Valid Valid reg<1486:1484> Reserved Valid Valid reg<1487> Reserved Valid Valid BA reg<1488> Reserved Valid Valid reg<1489> Wake time Selection in Wake Sleep Mode 0: short wake time 1: normal wake time Valid Valid reg<1490> ACMP0 Wake & Sleep function Enable 0: Disable 1: Enable Valid Valid reg<1491> ACMP1 Wake & Sleep function Enable 0: Disable 1: Enable Valid Valid reg<1492> ACMP2 Wake & Sleep function Enable 0: Disable 1: Enable Valid Valid reg<1493> Reserved Valid Valid reg<1494> Wake Sleep Output State When WS Oscilla - tor is Power Down if DLY/CNT0 Mode Selec - tion is "11" 0: Low 1: High Valid Valid reg<1495> Wake Sleep Ratio Control Mode Selection if DLY/CNT0 Mode Selection is "11" 0: Default Mode 1: Wake Sleep Ratio Control Mode Valid Valid BB reg<1503:1496> Reserved Valid Valid BC reg<1511:1504> Reserved Valid Valid BD reg<1519:1512> Reserved Valid Valid BE reg<1527:1520> Reserved Valid Valid BF reg<1535:1528> Reserved Valid Valid LUT / DLY/CNT Control Data C0 reg<1543:1536> LUT3_5 <7:0> or DLY/CNT2 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid C1 reg<1551:1544> LUT3_6 <7:0> or DLY/CNT3 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid C2 reg<1559:1552> LUT3_7 <7:0> or DLY/CNT4 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid C3 reg<1567:1560> LUT3_8 <7:0> or DLY/CNT5 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 163 of 175 SLG46534 Revision 1.18 C4 reg<1575:1568> LUT3_9 <7:0> or DLY/CNT6 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid C5 reg<1583:1576> LUT4_0 <15:0> or DLY/CNT0 (16bits, <15:0> = <1591:1576>) Control Data 1 - 65535 (Delay Time = [Counter Control Data + 2] / Freq) Valid Valid C6 reg<1591:1584> Valid Valid C7 reg<1599:1592> LUT4_1 <15:0> or DLY/CNT1 (16bits, <15:0> = <1607:1592>) Control Data 1 - 65535 (Delay Time = [Counter Control Data + 2] / Freq) Valid Valid C8 reg<1607:1600> Valid Valid C9 reg<1615:1608> PGEN pattern data <15:0> = <1623:1608> Valid Valid CA reg<1623:1616> Valid Valid ACMP0 CB reg<1628:1624> ACMP0-IN Voltage Select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: V DD /3 11001: V DD /4 11010: PIN10: EXT_VREF 11011: PIN5: ACMP0- 11100: PIN10: EXT_VREF/2 11101: PIN5: ACMP0-/2 Valid Valid reg<1630:1629> ACMP0 Positive Input Divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X Valid Valid reg<1631> ACMP0 Low Bandwidth (MAX: 1MHz) En - able 0: OFF 1:ON Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 164 of 175 SLG46534 Revision 1.18 ACMP1 CC reg<1636:1632> ACMP1-IN Voltage Select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: V DD /3 11001: V DD /4 11010: PIN10: EXT_VREF 11011: Reserved 11100: PIN10: EXT_VREF/2 11101: Reserved Valid Valid reg<1638:1637> ACMP1 Positive Input Divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X Valid Valid reg<1639> ACMP1 Low Bandwidth (MAX: 1MHz) En - able 0: OFF 1: ON Valid Valid ACMP2 CD reg<1644:1640> ACMP2-IN Voltage Select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: V DD /3 11001: V DD /4 11010: PIN10: EXT_VREF 11011: Reserved 11100: PIN10: EXT_VREF/2 11101: Reserved Valid Valid reg<1646:1645> ACMP2 Positive Input Divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X Valid Valid reg<1647> ACMP2 Low Bandwidth (MAX: 1MHz) En - able 0: OFF 1: ON Valid Valid Reserved CE reg<1652:1648> Reserved reg<1654:1653> Reserved reg<1655> Reserved Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 165 of 175 SLG46534 Revision 1.18 Misc. CF reg<1656> Reserved Valid Valid reg<1657> Switch from “Matrix OUT: OSC 25MHz PD” to “Matrix OUT: OSC 25MHz Force On” 0: OSC PD 1: OSC Force On (Matrix Output <59>) Valid Valid reg<1658> Switch from “Matrix OUT: OSC 25KHz/2MHz PD” to “Matrix OUT: OSC 25KHz/2MHz Force On” 0: OSC PD 1: OSC Force On (Matrix Output <58>) Valid Valid reg<1659> Reserved Valid Valid CF reg<1660> Reserved Valid Valid reg<1661> Reserved Valid Valid reg<1662> I 2C reset bit with reloading NVM into Data register 0: Keep existing condition 1: Reset execution Valid Valid reg<1663> Reserved Valid Valid D0 reg<1671:1664> RAM 8 outputs for ASM-state0 Valid Valid D1 reg<1679:1672> RAM 8 outputs for ASM-state1 Valid Valid D2 reg<1687:1680> RAM 8 outputs for ASM-state2 Valid Valid D3 reg<1695:1688> RAM 8 outputs for ASM-state3 Valid Valid D4 reg<1703:1696> RAM 8 outputs for ASM-state4 Valid Valid D5 reg<1711:1704> RAM 8 outputs for ASM-state5 Valid Valid D6 reg<1719:1712> RAM 8 outputs for ASM-state6 Valid Valid D7 reg<1727:1720> RAM 8 outputs for ASM-state7 Valid Valid D8 reg<1735:1728> User configurable RAM / OTP Byte 0 Valid Valid D9 reg<1743:1736> User configurable RAM / OTP Byte 1 Valid Valid DA reg<1751:1744> User configurable RAM / OTP Byte 2 Valid Valid DB reg<1759:1752> User configurable RAM / OTP Byte 3 Valid Valid DC reg<1767:1760> User configurable RAM / OTP Byte 4 Valid Valid DD reg<1775:1768> User configurable RAM / OTP Byte 5 Valid Valid DE reg<1783:1776> User configurable RAM / OTP Byte 6 Valid Valid DF reg<1791:1784> User configurable RAM / OTP Byte 7 Valid Valid E0 reg<1799:1792> Reserved Invalid Invalid E1 reg<1807:1800> Reserved Invalid Invalid E2 reg<1815:1808> Reserved Invalid Invalid E3 reg<1823:1816> Reserved Invalid Invalid E4 reg<1831:1824> Reserved Valid Valid reg<1832> I 2C lock for read bits <1535:0> (Bank 0/1/2) 0: Disable (Programmed data can be read.), 1: Enable (Programmed data can't be read.) Valid Invalid reg<1833> Reserved Valid Invalid reg<1835:1834> Reserved Valid Invalid reg<1839:1836> Reserved Valid Invalid E6 reg<1847:1840> 16-bit Pattern ID Byte 0 (From NVM): ID[23:16] Valid Valid E7 reg<1855:1848> Reserved Valid Invalid E8 reg<1863:1856> Reserved Valid Invalid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 166 of 175 SLG46534 Revision 1.18 reg<1867:1864> I2C Control Code Bit [3:0] Value for slave address Vali d Invalid reg<1868> Reserved Valid Valid reg<1869> Reserved Valid Valid reg<1870> I 2C lock for write all bits (Bank 0/1/2/3) 0: writable 1: Non-writable Valid Valid reg<1871> I 2C lock for write bits <1535:0> (Bank 0/1/2) 0: writable 1: Non-writable Valid Invalid EA reg<1879:1872> CNT4 Counted Value Valid Invalid EB reg<1887:1880> CNT0 (16bits) = <1895:1880> Counted Val - ue Valid Invalid EC reg<1895:1888> Valid Invalid ED reg<1903:1896> CNT6 Counted Value Valid Invalid EE reg<1911:1904> CNT1 (16bits) = <1919:1904> Counted Val - ue Valid Invalid EF reg<1919:1912> Valid Invalid Matrix Input reg<1920> Matrix Input 0 GND Valid Invalid reg<1921> Matrix Input 1 Pin2 Digital Input Valid Inval id reg<1922> Matrix Input 2 GND Valid Invalid reg<1923> Matrix Input 3 Pin3 Digital Input Valid Inval id reg<1924> Matrix Input 4 GND Valid Invalid reg<1925> Matrix Input 5 Pin4 Digital Input Valid Inval id reg<1926> Matrix Input 6 Pin5 Digital Input Valid Inval id reg<1927> Matrix Input 7 PIN8 Digital Input Valid Inval id reg<1928> Matrix Input 8 LUT2_0 / DFF0 Output Valid Inv alid reg<1929> Matrix Input 9 LUT2_1 / DFF1 Output Valid Inv alid reg<1930> Matrix Input 10 LUT2_2 / DFF2 Output Valid In valid reg<1931> Matrix Input 11 LUT2_3 / PGEN Output Valid In valid reg<1932> Matrix Input 12 LUT3_0 / DFF3 Output Valid In valid reg<1933> Matrix Input 13 LUT3_1 / DFF4 Output Valid In valid reg<1934> Matrix Input 14 LUT3_2 / DFF5 Output Valid In valid reg<1935> Matrix Input 15 LUT3_3 / DFF6 Output Valid In valid reg<1936> Matrix Input 16 LUT3_4 / DFF7 Output Valid In valid reg<1937> Matrix Input 17 LUT3_5 / CNT_DLY2(8bit) Out put Valid Invalid reg<1938> Matrix Input 18 LUT3_6 / CNT_DLY3(8bit) Out put Valid Invalid reg<1939> Matrix Input 19 LUT3_7 / CNT_DLY4(8bit) Out put Valid Invalid reg<1940> Matrix Input 20 LUT3_8 / CNT_DLY5(8bit) Out put Valid Invalid reg<1941> Matrix Input 21 LUT3_9 / CNT_DLY6(8bit) Out put Valid Invalid reg<1942> Matrix Input 22 LUT4_0 / CNT_DLY0(16bit) Ou tput Valid Invalid reg<1943> Matrix Input 23 LUT4_1 / CNT_DLY1(16bit) Ou tput Valid Invalid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 167 of 175 SLG46534 Revision 1.18 reg<1944> Matrix Input 24 LUT3_10 / Pipe Delay (1st s tage) Output Valid Invalid reg<1945> Matrix Input 25 Pipe Delay Output0 Valid Inva lid reg<1946> Matrix Input 26 Pipe Delay Output1 Valid Inva lid reg<1947> Matrix Input 27 Fixed "L" output because it is OSC clock. Valid Invalid reg<1948> Matrix Input 28 Fixed "L" output because it is OSC clock. Valid Invalid reg<1949> Matrix Input 29 Fixed "L" output because it is OSC clock. Valid Invalid reg<1950> Matrix Input 30 Filter0 / Edge Detect0 Outp ut Valid Invalid reg<1951> Matrix Input 31 Filter1 / Edge Detect1 Outp ut Valid Invalid reg<1952> Matrix Input 32 Virtual Input <0> Valid Valid reg<1953> Matrix Input 33 Virtual Input <1> Valid Valid reg<1954> Matrix Input 34 Virtual Input <2> Valid Valid reg<1955> Matrix Input 35 Virtual Input <3> Valid Valid reg<1956> Matrix Input 36 Virtual Input <4> Valid Valid reg<1957> Matrix Input 37 Virtual Input <5> Valid Valid reg<1958> Matrix Input 38 Virtual Input <6> Valid Valid reg<1959> Matrix Input 39 Virtual Input <7> Valid Vali d reg<1960> Matrix Input 40 RAM_0 Output for ASM-state V alid Invalid reg<1961> Matrix Input 41 RAM_1 Output for ASM-state V alid Invalid reg<1962> Matrix Input 42 RAM_2 Output for ASM-state V alid Invalid reg<1963> Matrix Input 43 RAM_3 Output for ASM-state V alid Invalid reg<1964> Matrix Input 44 RAM_4 Output for ASM-state V alid Invalid reg<1965> Matrix Input 45 RAM_5 Output for ASM-state V alid Invalid reg<1966> Matrix Input 46 RAM_6 Output for ASM-state V alid Invalid reg<1967> Matrix Input 47 RAM_7 Output for ASM-state V alid Invalid reg<1968> Matrix Input 48 Pin10 Digital Input Valid Inv alid reg<1969> Matrix Input 49 GND Valid Invalid reg<1970> Matrix Input 50 Pin11 Digital Input Valid Inv alid reg<1971> Matrix Input 51 GND Valid Invalid reg<1972> Matrix Input 52 Pin12 Digital Input Valid Inv alid reg<1973> Matrix Input 53 Pin13 Digital Input Valid Inv alid reg<1974> Matrix Input 54 GND Valid Invalid reg<1975> Matrix Input 55 GND Valid Invalid reg<1976> Matrix Input 56 Pin14 Digital Input Valid Inv alid reg<1977> Matrix Input 57 ACMP_0 Output Valid Invalid reg<1978> Matrix Input 58 ACMP_1 Output Valid Invalid reg<1979> Matrix Input 59 ACMP_2 Output Valid Invalid reg<1980> Reserved Valid Invalid reg<1981> Matrix Input 61 Programmable Delay with Edge Detector Output Valid Invalid reg<1982> Matrix Input 62 Resetb_core Valid Invalid reg<1983> Matrix Input 63 V DD Valid Invalid Reserved F8 reg<1991:1984> Reserved Valid Invalid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

© 2023 Renesas Electronics Corporation Page 168 of 175 SLG46534 Revision 1.18 F9 reg<1999:1992> Reserved Valid Invalid FA reg<2007:2000> Reserved Valid Invalid FB reg<2015:2008> Reserved Valid Valid FC reg<2023:2016> Reserved Valid Invalid FD reg<2031:2024> Reserved Valid Invalid FE reg<2039:2032> Reserved Valid Valid FF reg<2047:2040> Reserved Valid Valid Address Signal Function Register Bit Definition I2C Interface Byte Register Bit Read Write

22.0 Package Top Marking System Definition

22.1 Before February 1, 2021

22.2 After February 1, 2021

23.0 Package Drawing and Dimensions

STQFN 14L 2 x 2.2mm 0.4P COL Package JEDEC MO-220, Variation WECE

24.0 Tape and Reel Specifications

24.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 14L 2x2.2 mm 0.4P COL 14 2 x 2.2 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 14L 2x2.2 mm 0.4P COL Refer to EIA-481 specification

25.0 Recommended Landing Pattern

26.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.42 mm 3 (nominal). More information can be found at www.jedec.org.

27.0 Revision History

3/3/2023 1.18 Added notes to section Ordering Informa tion 1/25/2023 1.17 Corrected figure POR Sequence 3/4/2022 1.16 Updated R PUP and R PDWN in section Electrical Specifications Renesas rebranding Corrected registers [1076:1075], [1084:1083], [1087:1085] Updated Crystal Oscillator Description 2/2/2021 1.15 Updated section Package Top Marking Sys tem Definition 8/18/2020 1.14 Updated ACMP Spec Added note for CNTs Corrected Reset Command Timing figure Updated Pin Block Diagrams 10/25/2019 1.13 Updated disclaimer Updated register <1328> and register <1359> Corrected registers <1466:1464> Corrected 2-bit LUT2 or PGEN figure Updated registers <1047:1045>, <1143:1141>, <1167:1165>, <1636:1632> Corrected Table Read/Write Protection Options Fixed typos 11/13/2018 1.12 Updated to Dialog style Updated Oscillator Startup Diagram 8/9/2018 1.11 Updated reg<1079:1077>, reg<1087:1085> in Appendix A 6/13/2018 1.10 Updated I2C section Fixed typos 4/17/2018 1.09 Updated ASM Specifications Corrected CNT/FSM Timing Diagram Fixed typos 12/26/2017 1.08 Updated section RC Oscillator Updated Electrical Spec Fixed typos 10/12/2017 1.07 Updated Electrical Spec Fixed typos Updated I2C Specifications Updated subsection I2C Serial Reset Command Updated I2C Serial Command Register Protection Added Register Read/Write Protection subsection 5/24/2017 1.06 Fixed typos Updated reg<1831:1824> Updated Electrical Characteristics 5/5/2017 1.05 Updated Absolute Maximum Conditions Corrected table Typical Delay Estimated for Each Block at T = 25°C 4/21/2017 1.04 Fixed typos Updated POR section 3/31/2017 1.03 Fixed quality of CNT Timing Diagrams Updated Section Programmable Delay / Edge Detector Fixed typos 12/20/2016 1.02 Corrected Oscillator Electrical Spec Updated Silego Website & Support Fixed typos Corrected figure WS controller Added table DLY/CNTx One-Shot / Freq. Detect Output Polarity Added data to table Programmable Delay Register Settings Updated figure Deglitch Filter / Edge Detector

© 2023 Renesas Electronics Corporation Page 174 of 175 SLG46534 Revision 1.18 11/16/2016 1.01 Fixed typos Corrected figure OSC1 Power On Delay Corrected table Typical Counter/Delay Offset Measurements Added subsection Difference in Counter Value for Counter, Delay, One-Shot and Frequency Detect Modes 10/21/2016 1.00 Production Release Date Version Change

© 2023 Renesas Electronics Corporation Page 175 of 175 SLG46534 Revision 1.18 RoHS Compliance Renesas Electronics Corporation’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous sub stances in electrical and electronic equipment. RoH S certificates from our suppliers are available on request.

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Product Information

SLG46534V specifications and overview.

Summary

GreenPAK Programmable Mixed-signal Matrix with Asynchronous State Machine March 3, 2023

Description

GreenPAK Programmable Mixed-signal Matrix with Asynchronous State Machine March 3, 2023

Source title SLG46534V Datasheet(PDF) - Renesas Technology Corp

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