SLDS145B

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TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Digital Visual Interface (DVI) Compliant1 /C0068Supports Pixel Rates Up to 165 MHz (Including 1080p and WUXGA at 60Hz) /C0068Universal Graphics Controller Interface − 12-Bit, Dual-Edge and 24-Bit, Single-Edge Input Modes − Adjustable 1.1 V to 1.8 V and Standard

3.3 V CMOS Input Signal Levels

− Fully Differential and Single-Ended Input Clocking Modes − Standard Intel 12-Bit Digital Video Port Compatible as on Intel™ 81x Chipsets /C0068Enhanced PLL Noise Immunity − On-Chip Regulators and Bypass Capacitors for Reducing System Costs /C0068Enhanced Jitter Performance − No HSYNC Jitter Anomaly − Negligible Data-Dependent Jitter /C0068Programmable Using I2C Serial Interface /C0068Monitor Detection Through Hot-Plug and Receiver Detection /C0068Single 3.3-V Supply Operation /C006864-Pin TQFP Using TI’s PowerPAD™ Package /C0068TI’s Advanced 0.18 μm EPIC-5™ CMOS Process Technology /C0068Pin Compatible With SiI164 DVI Transmitter

description

The TFP410 is a Texas Instruments PanelBus flat panel display product, part of a comprehensive family of end-to-end DVI 1.0-compliant solutions, targeted at the PC and consumer electronics industry. The TFP410 provides a universal interface to allow a glue-less connection to most commonly available graphics controllers. Some of the advantages of this universal interface include selectable bus widths, adjustable signal levels, and differential and single-ended clocking. The adjustable 1.1-V to 1.8-V digital interface provides a low-EMI, high-speed bus that connects seamlessly with 12-bit or 24-bit interfaces. The DVI interface supports flat panel display resolutions up to UXGA at 165 MHz in 24-bit true color pixel format. The TFP410 combines PanelBus circuit innovation with TI’s advanced 0.18 μm EPIC-5 CMOS process technology and TI’s ultralow ground inductance PowerPAD package. The result is a compact 64-pin TQFP package providing a reliable, low-current, low-noise, high-speed digital interface solution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either V CC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Copyright © 2002 − 2011, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Footnote: 1. The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high-speed digital connection to digital displays and has been adopted by industry-leading PC and consumer electronics manufacturers. The TFP410 is compliant to the DVI Revision 1.0 specification. PanelBus, PowerPAD, and EPIC-5 are trademarks of Texas Instruments. VESA is a trademark of Video Electronics Standards Association. Intel is a trademark of Intel Corporation. Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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TX2− TV DD TX1+ TX1− TGND TX0+ TX0− TV DD TXC+ TXC− TGND TFADJ PV DD PGND NC DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 IDCK− IDCK+ DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DGND 56 78 47 46 45 44 4348 42 40 39 3841 91 0 1 1 1 2 1 3 37 36 35 34 33 14 15 16 PAP PACKAGE (TOP VIEW) DGND DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DKEN RESERVED DV DD DVDD DE VREF HSYNC VSYNC CTL3/A3/DK3 CTL2/A2/DK2 CTL1/A1/DK1 EDGE/HTPLG PD MSEN/PO1 DVDD ISEL/RST DSEL/SDA BSEL/SCL DGND

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram 12/24 Bit I/F Data Format Universal Input T.M.D.S. Transmitter Serializer Serializer Serializer Control I2C Slave I/F For DDC 1.8-V Regulators With Bypass Capacitors PLL TX2± TX1± TX0± TXC± TFADJ IDCK± DATA[23:0] DE VSYNC HSYNC EDGE/HTPLG MSEN PD ISEL/RST BSEL/SCL DSEL/SDA VREF Encoder Encoder Encoder CTL/A/DK[3:1] DKEN Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION Input DATA[23:12] 36−47 I The upper 12 bits of the 24-bit pixel bus In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode, the state of DATA[23:16] is input to the I2C register CFG. This allows 8 bits of user configuration data to be read by the graphics controller through the I2C interface (see the I2C register descriptions section). Note: All unused data inputs should be tied to GND or VDD. DATA[11:0] 50−55, 58−63 I The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latch edge (both rising and falling) of the clock. IDCK− IDCK+ I Differential clock input. The TFP410 supports both single-ended and fully differential clock input modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended clock source and the IDCK− input (pin 56) should be tied to GND. In the differential clock input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK− signals as the timing reference for latching incoming data DATA[23:0], DE, HSYNC, & VSYNC. The differential clock input mode is only available in the low signal swing mode. DE 2 I Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel data or control data on any given input clock cycle. During active video (DE = high), the transmitter encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes HSYNC, VSYNC and CTL[3:1]. HSYNC 4 I Horizontal sync input VSYNC 5 I Vertical sync input

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Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION CTL3/A3/DK3 CTL2/A2/DK2 CTL1/A1/DK1 I The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) and DKEN (pin 35) inputs. All three inputs support 3.3-V CMOS signal levels and contain weak pulldown resistors so that if left unconnected they default to all low. When the I2C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low), these three inputs become the control inputs, CTL[3:1], which can be used to send additional information across the DVI link during the blanking interval (DE = low). The CTL3 input is reserved for HDCP compliant DVI TXs (TFP510) and the CTL[2:1] inputs are reserved for future use. When the I2C bus is disabled (ISEL = low) and the de-skew mode is enabled (DKEN = high), these three inputs become the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixel data inputs DATA[23:0], relative to the clock input IDCK±. When the I2C bus is enabled (ISEL = high), these three inputs become the 3 LSBs of the I 2C slave address, A[3:1]. Configuration/Programming MSEN/PO1 11 O Monitor sense/programmable output 1. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-kΩ pullup resistor connected to VDD is required on this pin. When I2C is disabled (ISEL = low), a low level indicates a powered on receiver is detected at the differential outputs. A high level indicates a powered on receiver is not detected. This function is only valid in dc-coupled systems. When I2C is enabled (ISEL = high), this output is programmable through the I2C interface (see the I2C register descriptions section). ISEL/RST 13 I I2C interface select/I2C RESET (active low, asynchronous) If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C register descriptions section. If ISEL is low, then I 2C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN). If ISEL is brought low and then back high, the I 2C state machine is reset. The register values are changed to their default values and are not preserved from before the reset. BSEL/SCL 15 I Input bus select/I2C clock input. The operation of this pin depends on whether the I 2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level selects 12-bit input, dual-edge input mode. When I2C is enabled (ISEL = high), this pin functions as the I 2C clock input (see the I 2C register descriptions section). In this configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor connected to VDD. DSEL/SDA 14 I/O DSEL/I2C data. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), this pin is used with BSEL and VREF to select the single-ended or differential input clock mode (see the universal graphics controller interface modes section). When I 2C is enabled (ISEL = high), this pin functions as the I 2C bidirectional data line. In this configuration, this pin has an open-drain output that requires an external 5-k Ω pullup resistor connected to VDD. EDGE/HTPLG 9 I Edge select/hot plug input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This input is 3.3-V tolerant only. When I2C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock IDCK+. This is the case for both single-ended and differential input clock modes. When I 2C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal (see the DVI or VESA™ P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-KΩ resistor.

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION DKEN 35 I Data de-skew enable. The de-skew function can be enabled either through I2C or by this pin when I2C is disabled. When de-skew is enabled, the input clock to data setup/hold time can be adjusted in discrete trim increments. The amount of trim per increment is defined by t(STEP). When I2C is disabled (ISEL = low), a high level enables de-skew with the trim increment determined by pins DK[3:1] (see the data de-skew section). A low level disables de-skew and the default trim setting is used. When I2C is enabled (ISEL = high), the value of DKEN and the trim increment are selected through I2C. In this configuration, the DKEN pin should be tied to either GND or VDD to avoid a floating input. VREF 3 I Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC, VSYNC, and IDCK±). For high-swing 3.3-V input signal levels, VREF should be tied to VDD. For low-swing input signal levels, VREF should be set to half of the maximum input voltage level. See the recommended operating conditions section for the allowable range for VREF. The desired VREF voltage level is typically derived using a simple voltage-divider circuit. PD 10 I Power down (active low). In the powerdown state, only the digital I/O buffers and I2C interface remain active. When I2C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects the powerdown mode. When I2C is enabled (ISEL = high), the power-down state is selected through I2C. In this configuration, the PD pin should be tied to GND. Note: The default register value for PD is low, so the device is in powerdown mode when I2C is first enabled or after an I2C RESET. Reserved RESERVED 34 In This pin is reserved and must be tied to GND for normal operation. DVI Differential Signal Output Pins TX0+ TX0− O Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active video and HSYNC and VSYNC during the blanking interval. TX1+ TX1− O Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active video and CTL[1] during the blanking interval. TX2+ TX2− O Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video and CTL[3:2] during the blanking interval. TXC+ TXC− O DVI differential output clock. TFADJ 19 I Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the value of the pullup resistor RTFADJ connected to TVDD. Power and Ground Pins DVDD 1, 12, 33 Power Digital power supply. Must be set to 3.3 V nominal. PVDD 18 Power PLL power supply. Must be set to 3.3 V nominal. TVDD 23, 29 Power Transmitter differential output driver power supply. Must be set to 3.3 V nominal. DGND 16, 48, 64 Ground Digital ground PGND 17 Ground PLL ground TGND 20, 26, 32 Ground Transmitter differential output driver ground NC 49 NC No connection required. If connected, tie high.

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD (DVDD, PVDD, TVDD) 3.0 3.3 3.6 V Input reference voltage V Low-swing mode 0.55 VDDQ/2‡ 0.9 V Input reference voltage, VREF High-swing mode DVDD V DVI termination supply voltage, AVDD (see Note 1) DVI receiver 3.14 3.3 3.46 V DVI Single-ended termination resistance, RT (see Note 2) DVI receiver 45 50 55 Ω TFADJ resistor for DVI-compliant V(SWING) range, R(TFADJ) 400 mV = V(SWING) = 600 mV 505 510 515 Ω Operating free-air temperature range, TA 0 25 70 °C ‡ VDDQ defines the maximum low-level input voltage, it is not an actual input voltage. NOTES: 1. AV DD is the termination supply voltage of the DVI link. 2. R T is the single-ended termination resistance at the receiver end of the DVI link.

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) dc specifications PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT V High level input voltage (CMOS input) VREF = DVDD 0.7 VDD VVIH High-level input voltage (CMOS input) 0.5 V /C0020 VREF /C0020 0.95 V VREF + 0.2 V V Low level input voltage (CMOS input) VREF = DVDD 0.3VDD VVIL Low-level input voltage (CMOS input) 0.5 V /C0020 VREF /C0020 0.95 V VREF − 0.2 V VOH High-level digital output voltage (open-drain output) VDD = 3 V, IOH = 20 μA 2.4 V VOL Low-level digital output voltage (open-drain output) VDD = 3.6 V, IOL = 4 mA 0.4 V IIH High-level input current VI = 3.6 V ±25 μA IIL Low-level input current VI = 0 ±25 μA VH DVI single-ended high-level output voltage AVDD − 0.01 AVDD + 0.01 V VL DVI single-ended low-level output voltage AVDD = 3.3 V ± 5%, R † 50 Ω ± 10% AVDD − 0.6 AVDD − 0.4 V VSWING DVI single-ended output swing voltage RT† = 50 Ω ± 10%, RTFADJ = 510 Ω ± 1% 400 600 mVP-P VOFF DVI single-ended standby/off output voltage RTFADJ = 510 Ω ± 1% AVDD − 0.01 AVDD + 0.01 V IPD Power-down current (see Note 3) 200 500 μA IIDD Normal power supply current Worst case pattern‡ 200 250 mA † RT is the single-ended termination resistance at the receiver end of the DVI link. ‡ Black and white checkerboard pattern, each checker is one pixel wide. NOTE 3: Assumes all inputs to the transmitter are not toggling. ac specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(IDCK) IDCK frequency 25 165 MHz t(pixel) Pixel time period (see Note 4) 6.06 40 ns t(IDCK) IDCK duty cycle 30% 70% t(ijit) IDCK clock jitter tolerance 2 ns tr DVI output rise time (20-80%) (see Note5) 75 240 ps tf DVI output fall time (20-80%) (see Note 5) 75 240 ps tsk(D) DVI output intra-pair + to − differential skew (see Note 6) f(IDCK) = 165 MHz 50 ps tsk(CC) DVI output inter-pair or channel-to-channel skew (see Note 6) f(IDCK) 165 MHz 1.2 ns tojit DVI output clock jitter, max. (see Note 7) 150 ps tsu(IDF) Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge Single edge (BSEL 1 DSEL 0 1.2 ns th(IDF) Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge (BSEL=1, DSEL=0, DKEN=0, EDGE=0) 1.3 ns tsu(IDR) Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge Single edge (BSEL 1 DSEL 0 1.2 ns th(IDR) Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge (BSEL=1, DSEL=0, DKEN=0, EDGE=1) 1.3 ns tsu(ID) Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/rising edge Dual edge (BSEL=0, DSEL=1, DKEN=0) 0.9 ns th(ID) Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising edge Dual edge (BSEL=0, DSEL=1, DKEN=0) 1 ns t(STEP) De-skew trim increment DKEN = 1 350 ps NOTES: 4. t (pixel) is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t(pixel). 5. Rise and fall times are measured as the time between 20% and 80% of signal amplitude. 6. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger. 7. Relative to input clock (IDCK).

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Figure 1. Rise and Fall Time for DVI Outputs Figure 2. Control and Single-Edge-Data Setup/Hold Time to IDCK± Figure 3. Dual Edge Data Setup/Hold Times to IDCK+ Figure 4. Analog Output Intra-Pair ± Differential Skew Figure 5. Analog Output Channel-to-Channel Skew

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional description The TFP410 is a DVI-compliant digital transmitter that is used in digital host monitor systems to T.M.D.S. encode and serialize RGB pixel data streams. TFP410 supports resolutions from VGA to WUXGA (and 1080p) and can be controlled in two ways: 1) configuration and state pins or 2) the programmable I 2C serial interface (see the terminal functions section). The host in a digital display system, usually a PC or consumer electronics device, contains a DVI-compatible transmitter such as the TI TFP410 that receives 24-bit pixel data along with appropriate control signals. The TFP410 encodes the signals into a high speed, low voltage, differential serial bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a DVI compatible receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred (see the T.M.D.S. pixel data and control signal encoding, pixel data and control signal encoding, universal graphics contoller interface voltage signal levels, and universal graphics controller interface clock inputs sections). drivers. Data is driven to the TFP410 encoder across 12 or 24 data lines, along with differential clock pair and sync signals. The flexibility of the TFP410 allows for multiple clock and data formats that enhance system performance. The TFP410 also has enhanced PLL noise immunity, an enhancement accomplished with on-chip regulators and bypass capacitors. The TFP410 is versatile and highly programmable to provide maximum flexibility for the user. An I 2C host interface is provided to allow enhanced configurations in addition to power-on default settings programmed by pin-strapping resistors. The TFP410 offers monitor detection through receiver detection, or hot-plug detection when I2C is enabled. The monitor detection feature allows the user enhanced flexibility when attaching to digital displays or receivers (see terminal functions, hot-plug/unplug, and register descriptions sections). The TFP410 has a data de-skew feature allowing the users to de-skew the input data with respect to the IDCK± (see the data de-skew feature section).

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T.M.D.S. pixel data and control signal encoding given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent and transmits the character that minimizes the number of transitions and approximates a dc video interval (DE = High). These same three channels are also used to transmit HSYNC, VSYNC, and three user definable control signals, CTL[3:1], during the inactive display or blanking interval (DE = Low). The following table maps the transmitted output data to the appropriate T.M.D.S. output channel in a DVI-compliant system. INPUT PINS (VALID FOR DE = High) T.M.D.S. OUTPUT CHANNEL TRANSMITTED PIXEL DATA ACTIVE DISPLAY (DE = High) DATA[23:16] Channel 2 (TX2 ±) Red[7:0] DATA[15:8] Channel 1 (TX1 ±) Green[7:0] DATA[7:0] Channel 0 (TX0 ±) Blue[7:0] INPUT PINS (VALID FOR DE = Low) T.M.D.S. OUTPUT CHANNEL TRANSMITTED CONTROL DATA BLANKING INTERVAL (DE = Low) CTL3, CTL2 (see Note 8) Channel 2 (TX2 ±) CTL[3:2] CTL1 (See Note 8) Channel 1 (TX1 ±) CTL[1] HSYNC, VSYNC Channel 0 (TX0 ±) HSYNC, VSYNC NOTE 8: The TFP410 encodes and transfers the CTL[3:1] inputs during the vertical blanking interval. The CTL3 input is reserved for HDCP compliant DVI TXs and the CTL[2:1] inputs are reserved for future use. When DE = high, CTL and SYNC pins must be held constant. universal graphics controller interface voltage signal levels The universal graphics controller interface can operate in the following two distinct voltage modes: /C0068The high-swing mode where standard 3.3-V CMOS signaling levels are used. /C0068The low-swing mode where adjustable 1.1-V to 1.8-V signaling levels are used. To select the high-swing mode, the VREF input pin must be tied to the 3.3-V power supply. To select the low-swing mode, the VREF must be 0.55 to 0.95 V. In the low-swing mode, VREF is used to set the midpoint of the adjustable signaling levels. The allowable range of values for VREF is from 0.55 V to 0.9 V. The typical approach is to provide this from off chip by using a simple voltage-divider circuit. The minimum allowable input signal swing in the low-swing mode is V REF ±0.2 V. In low-swing mode, the VREF input is common to all differential input receivers. universal graphics controller interface clock inputs The universal graphics controller interface of the TFP410 supports both fully differential and single-ended clock input modes. In the differential clock input mode, the universal graphics controller interface uses the crossover point between the IDCK+ and IDCK− signals as the timing reference for latching incoming data (DATA[23:0], DE, HSYNC, and VSYNC). Differential clock inputs provide greater common-mode noise rejection. The differential clock input mode is only available in the low-swing mode. In the single-ended clock input mode, the IDCK+ input (Pin 57) should be connected to the single-ended clock source and the IDCK− input (Pin 56) should be tied to GND. The universal graphics controller interface of the TFP410 provides selectable 12-bit dual-edge, and 24-bit single-edge, input clocking modes. In the 12-bit dual-edge , the 12-bit data is latched on each edge of the input clock. In the 24-bit single-edge mode, the 24-bit data is latched on the rising edge of the input clock when EDGE = 1 and the falling edge of the input clock when EDGE = 0. DKEN and DK[3:1] allow the user to compensate the skew between IDCK ± and the pixel data and control signals. See the description of the CTL_3_MODE register for details.

in the low-swing mode as this decreases common-mode noise rejection. and by input pins when I2C is disabled (ISEL=0). Table 1. Universal Graphics Controller Interface Options (Tabular Representation)

1. The TFP410 does not support a 12-bit dual-clock, single-edge input clocking mode.
2. The TFP410 does not support a 24-bit single-clock, dual-edge input clocking mode.
3. In the high-swing mode (V REF = DVDD), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.

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Figure 6. Universal Graphics Controller Interface Options for 12-Bit Mode (Graphical Representation) Figure 7. Universal Graphics Controller Interface Options for 24-Bit Mode (Graphical Representation)

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12-bit mode data mapping PIN P0 P1 P2 PIN NAME P0L P0H P1L P1H P2L P2HNAME LOW HIGH LOW HIGH LOW HIGH 24-bit mode data mapping PIN NAME P0 P1 P2 PIN NAME P0 P1 P2

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Figure 8. A Graphical Representation of the De-Skew Function program the MSEN to output the HTPLG value, the RSEN value, an interrupt, or be disabled. resetting the bit back to 0. Writing 0 to the MDI bit has no effect.

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 device configuration and I2C RESET description The TFP410 device configuration can be programmed by several different methods to allow maximum flexibility for the user’s application. Device configuration is controlled depending on the state of the ISEL/RST pin, configuration pins (BSEL, DSEL, EDGE, V REF) and state pins (PD , DKEN). I2C bus select and I 2C RESET (active low) are shared functions on the ISEL/RST pin, which operates asynchronously. Holding ISEL/RST low causes the device configuration to be set by the configuration pins (BSEL, DSEL, EDGE, and VREF) and state pins (PD, DKEN). The I2C bus is disabled. Holding ISEL/RST high causes the chip configuration to be set based on the configuration bits (BSEL, DSEL, EDGE) and state bits (PD, DKEN) in the I2C registers. The I2C bus is enabled. Momentarily bringing ISEL/RST low and then back high while the device is operating in normal or power-down mode will RESET the I2C registers to their default values. The device configuration will be changed to the default power-up state with I2C enabled. After power up, the device must be reset. It is suggested that this pin be tied to the system reset signal, which is low during power up and is then asserted high after all the power supplies are fully functional. DE generator The TFP410 contains a DE generator that can be used to generate an internal DE signal when the original data source does not provide one. There are several I 2C programmable values that control the DE generator (see Figure 9). DE_GEN in the DE_CTL register enables this function. When enabled, the DE pin is ignored. DE_TOP and DE_LIN are line counts used to control the number of lines after VSYNC goes active that DE is enabled, and the total number of lines that DE remains active, respectively. The polarity of VSYNC must be set by VS_POL in the DE_CTL register. DE_DLY and DE_CNT are pixel counts used to control the number of pixels after HSYNC goes active that DE is enabled, and the total number of pixels that DE remains active, respectively. The polarity of HSYNC must be set by HS_POL in the DE_CTL register. The TFP410 also counts the total number of HSYNC pulses between VSYNC pulses, and the total number of pixels between HSYNC pulses. These values, the total vertical and horizontal resolutions, are available in V_RES and H_RES, respectively. These values are available at all times, whether or not the DE generator is enabled.

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Figure 9. DE Generator Register Functions 7 and 8 respectively) as shown below.

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 register map (continued) REGISTER RW SUB- ADDRESS BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 VEN_ID R 00 VEN_ID[7:0] R 01 VEN_ID[15:8] DEV_ID R 02 DEV_ID[7:0] R 03 DEV_ID[15:8] REV_ID R 04 REV_ID[7:0] RESERVED R 05-07 Reserved CTL_1_MODE RW 08 RSVD TDIS VEN HEN DSEL BSEL EDGE PD CTL_2_MODE RW 09 VLOW MSEL TSEL RSEN HTPLG MDI CTL_3_MODE RW 0A DK DKEN CTL RSVD CFG RW 0B CFG RESERVED RW 0C-31 Reserved DE_DLY RW 32 DE_DLY[7:0] DE_CTL RW 33 RSVD DE_GEN VS_POL HS_POL RSVD DE_DLY[8] DE_TOP RW 34 RSVD DE_DLY[6:0] RESERVED RW 35 Reserved DE_CNT RW 36 DE_CNT[7:0] RW 37 Reserved DE_CNT[10:8] DE_LIN RW 38 DE_LIN[7:0] RW 39 Reserved DE_LIN[10:8] H_RES R 3A H_RES[7:0] R 3B Reserved H_RES[10:8] V_RES R 3C V_RES[7:0] R 3D Reserved V_RES[10:8] RESERVED R 3E−FF register descriptions VEN_ID Sub-Address = 01 −00 Read Only Default = 0x014C 7 6 5 4 3 2 1 0 VEN_ID[7:0] VEN_ID[15:8] These read-only registers contain the 16-bit Texas Instruments vendor ID. VEN_ID is hardwired to 0x014C. DEV_ID Sub-Address = 03 −02 Read Only Default = 0x0410 7 6 5 4 3 2 1 0 DEV_ID[7:0] DEV_ID[15:8] These read-only registers contain the 16-bit device ID for the TFP410. DEV_ID is hardwired to 0x0410. REV_ID Sub-Address = 04 Read Only Default = 0x00 7 6 5 4 3 2 1 0 REV_ID[7:0] This read-only register contains the revision ID.

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register descriptions (continued) RESERVED Sub-Address = 07 −05 Read Only Default = 0x641400 7 6 5 4 3 2 1 0 RESERVED[7:0] RESERVED[7:0] RESERVED[15:8] CTL_1_MODE Sub-Address = 08 Read/Write Default = 0xFE 7 6 5 4 3 2 1 0 RSVD TDIS VEN HEN DSEL BSEL EDGE PD PD: This read/write register contains the power-down mode. 0: Power down (default after RESET) 1: Normal operation EDGE: This read/write register contains the edge select mode. 0: Input data latches to the falling edge of IDCK+ 1: Input data latches to the rising edge of IDCK+ BSEL: This read/write register contains the input bus select mode. 0: 12-bit operation with dual-edge clock 1: 24-bit operation with single-edge clock DSEL:This read/write register is used in combination with BSEL and VREF to select the single-ended or differential input clock mode. In the high-swing mode, DSEL is a don’t care since IDCK is always single-ended. HEN: This read/write register contains the horizontal sync enable mode. 0: HSYNC input is transmitted as a fixed low 1: HSYNC input is transmitted in its original state VEN: This read/write register contains the vertical sync enable mode. 0: VSYNC input is transmitted as a fixed low 1: VSYNC input is transmitted in its original state

TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 register descriptions (continued) CTL_2_MODE Sub-Address = 09 Read/Write Default = 0x00 7 6 5 4 3 2 1 0 VLOW MSEL[3:1] TSEL RSEN HTPLG MDI MDI: This read/write register contains the monitor detect interrupt mode. 0: Detected logic level change in detection signal (to clear, write one to this bit) 1: Logic level remains the same HTPLG: This read only register contains the hot plug detection input logic state. 0: Logic level detected on the EDGE/HTPLG pin (pin 9) 1: High level detected on the EDGE/HTPLG pin (pin 9) RSEN: This read only register contains the receiver sense input logic state, which is valid only for dc-coupled systems. 0: A powered-on receiver is not detected 1: A powered-on receiver is detected (i.e. connected to the DVI transmitter outputs) TSEL: This read/write register contains the interrupt generation source select. 0: Interrupt bit (MDI) is generated by monitoring RSEN 1: Interrupt bit (MDI) is generated by monitoring HTPLG MSEL: This read/write register contains the source select of the monitor sense output pin. 000: Disabled. MSEN output high 001: Outputs the MDI bit (interrupt) 010: Outputs the RSEN bit (receiver detect) 011: Outputs the HTPLG bit (hot plug detect) VLOW: This read only register indicates the V REF input level. 0: This bit is a logic level (0) if the VREF analog input selects high-swing inputs 1: This bit is a logic level (1) if the VREF analog input selects low-swing inputs CTL_3_MODE Sub-Address = 0A Read/Write Default = 0x80 7 6 5 4 3 2 1 0 DK[3:1] DKEN CTL[3:1] RSVD CTL[3:1]:This read/write register contains the values of the three CTL[3:1] bits that are output on the DVI port during the blanking interval. DKEN: This read/write register controls the data de-skew enable. 0: Data de-skew is disabled, the values in DK[3:1] are not used 1: Data de-skew is enabled, the de-skew setting is controlled through DK[3:1] DK[3:1]: This read/write register contains the de-skew setting, each increment adjusts the skew by t(STEP). 000: Step 1 (minimum setup/maximum hold) 001: Step 2 010: Step 3 011: Step 4 100: Step 5 (default) 101: Step 6 110: Step 7 111: Step 8 (maximum setup/minimum hold)

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register descriptions (continued) CFG Sub-Address = 0B Read Only 7 6 5 4 3 2 1 0 This read-only register contains the state of the inputs D[23:16]. These pins can be used to provide the user with selectable configuration data through the I2C bus. RESERVED Sub-Address = 0E −0C Read/Write Default = 0x97D0A9 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED These read/write registers have no effect on TFP410 operation. DE_DLY Sub-Address = 32 Read/Write Default = 0x00 7 6 5 4 3 2 1 0 DE_DLY[7:0] This read/write register defines the number of pixels after HSYNC goes active that DE is generated, when the DE generator is enabled. DE_CTL Sub-Address = 33 Read/Write Default = 0x00 7 6 5 4 3 2 1 0 Reserved DE_GEN VS_POL HS_POL Reserved DE_DLY[8] DE_DLY[8]: This read/write register contains the top bit of DE_DLY . HS_POL: This read/write register sets the HSYNC polarity. 0: HSYNC is considered active low. 1: HSYNC is considered active high. Pixel counts are reset on the HSYNC active edge. VS_POL: This read/write register sets the VSYNC polarity. 0: VSYNC is considered active low. 1: VSYNC is considered active high. Line counts are reset on the VSYNC active edge. DE_GEN: This read/write register enables the internal DE generator. 0: DE generator is disabled. Signal required on DE pin 1: DE generator is enabled. DE pin is ignored. DE_TOP Sub-Address = 34 Read/Write Default = 0x00 7 6 5 4 3 2 1 0 DE_TOP[7:0] This read/write register defines the number of pixels after VSYNC goes active that DE is generated, when the DE generator is enabled.

These read/write registers define the width of the active display, in pixels, when the DE generator is enabled. These read/write registers define the height of the active display, in lines, when the DE generator is enabled. These read-only registers return the number of pixels between consecutive HSYNC pulses. These read-only registers return the number of lines between consecutive VSYNC pulses. clock line and the SDA serial data line. The basic I2C access cycles are shown in Figure 10 and Figure 11. Figure 10. I2C Start and Stop Conditions

1. Any number of data cycles

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1. A slave write address cycle
2. A slave read address cycle
3. Any number of data cycles

device. Thus, each data/address cycle contains 9 bits as shown in Figure 11. Figure 11. I2C Access Cycles acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address. Figure 12. The sub-address is auto-incremented after each data cycle. high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 13. 0x77, 0x79, 0x7B, 0x7D, and 0x7F for read cycles. Figure 12. I2C Write Cycle

Figure 13. I2C Read Cycle designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. Soldering the backside of the device to the PCB ground plane is recommended for electrical considerations. to help improve EMI, ground bounce, and power supply noise performance. non-PowerPAD package is included only for reference. Table 2. TI 64-Pin TQFP (10 × 10 × 1,0 mm)/0,5 mm Lead-Pitch NOTES: 13. Specified with the PowerPAD bond pad on the backside of the package soldered to a 2-oz. Cu plate PCB thermal plane.

1. Airflow is at 0 LFM (no airflow)
2. Specified at 150 °C junction temperature and 80°C ambient temperature.

www.ti.com 6-May-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TFP410PAP ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TFP410PAPG4 ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TFP410 :

• Enhanced Product: TFP410-EP NOTE: Qualified Version Definitions:

www.ti.com 6-May-2011 Addendum-Page 2

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

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