SLD-3091FZ SIRENZA | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for in accuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Phone: (800) SMI-MMIC http://w ww.sirenza.com Broomfield, CO 80021 1 EDS-104668 Rev C Preliminary Sirenza Microdevices’ SLD-3091FZ is a robust 30 Watt high performance LDMOS transistor designed for operation from 10 to 2200MHz. It is an excellent solution for applications requiring high linearity and efficiency at a low cost. The SLD-3091FZ is typically used in power amplifiers, repeaters, and radio amplifier applications. The power transistor is fabricated using Sirenza’s high performance XeMOS IITM process. Key RF Specifications Symbol Parameter Units Min. Typ. Max. Frequency Frequency of Operation MHz 10 - 2200 Gain 30 Watt CW, 915 MHz dB 19 Efficiency Drain Efficiency at 30 Watt CW, 915 MHz % 45 IRL Input Return Loss, 30 Watt Output Power, 915 MHz dB -15 Linearity 3rd Order IMD at 30 Watt PEP (Two Tone), 915 MHz dBc -28 1dB Compression (P1dB), 915 MHz Watt 35 RTH Thermal Resistance (Junction-to-Case) ºC/W 2.4 SLD-3091FZ

30 Watt Discrete LDMOS FET in Ceramic

Applications

  • 30 Watt Output P1dB
  • Single Polarity Supply Voltage
  • High Gain: 18 dB at 915 MHz
  • High Efficiency: 45% at 30W CW
  • XeMOS II LDMOS
  • Integrated ESD Protection, 1B
  • Base Station PA driver
  • Repeaters
  • Radio Amplifier
  • Military Communication
  • GSM, CDMA, RFID, Point-to-Point Product Description Pb RoHS Compliant & Packag eGreen Functional Schematic Diagram Key DC Parameters Symbol Parameter Unit Min Typ. Max gm Forward Transconductance @ 425mA IDS mA / V 1650 VGSThreshold I DS=3mA Volt 3.3 VDS Breakdown 1mA I DS current Volt 65 Ciss Input Capacitance (Gate to Source) VGS=0V, VDS=28V pF 66 Crss Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V pF 1.4 Coss Output Capacitance (Drain to Source) VGS=0V, VDS=28V pF 30 RDSon Drain to Source Resistance, VGS=10V, VDS=250mV Ω 0.2 Test Conditions VDS = 28.0V, IDQ = 300mA, TFlange = 25ºC T Case Flange = Ground ESD Protection

303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 2 EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Note 1: Gate voltage must be applied to the device concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the tran- sistor unless it is properly terminated on both input and output. Note 2: The required V GS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in thresh- old voltage with LDMOS transistors. Note 3: The threshold voltage (V GSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Absolute Maximum Ratings Parameters Value Unit Drain Voltage (VDS )3 5 V Gate Voltage (VGS)2 0 V RF Input Power +36 dBm Load Impedance for Continuous Operation Without Damage 10:1 VSWR Output Device Channel Temperature +200 ºC Lead Temperature During Solder Reflow +270 ºC Operating Temperature Range -20 to +90 ºC Storage Temperature Range -40 to +100 ºC Operation of this device beyond any one of these limits may cause perma- nent damage. For reliable continuous operation see typical setup values specified in the table on page one. Quality Specifications Parameter Description Rating ESD Rating Human Body Model 1B Case Flange = Ground ESD Protection Pin Diagram Pin 1 Pin 2 Pin Description Pin # Function Description 1G a t e Transistor RF input and gate bias voltage. The gate bias voltage must be temperature compensated to maintain constant bias current over the operating temperature range. Care must be taken to protect against video transients that exceed the recommended maximum input power or voltage. 2 Drain Transistor RF output and drain bias voltage. Typical voltage is 28V. Flange Source, Gnd Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation.

303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 3 EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Typical Performance Curves in 900 MHz Application Circuit

2 Tone Gain, Efficiency, Linearity and IRL vs Frequency

Vdd=28V, Idq=0.3A, Pout=30W PEP, Delta F=1 MHz 885 895 905 915 925 935 945 Frequency (MHz) Gain (dB), Efficiency (%) -60 -50 -40 -30 -20 -10 IMD(dBc), IRL (dB) Gain Efficiency IM3 IM5 IM7 IRL

2 Tone Gain, Efficiency, Linearity vs Pout

Vdd=28V, Idq=0.3A, Freq=912 MHz, Delta F=1 MHz 0 5 10 15 20 25 30 Pout (W PEP) Gain (dB), Efficiency (%) -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 IMD (dBc) Gain Efficiency IM3 IM5 IM7 CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=0.3A, Pout=30W 885 895 905 915 925 935 945 Frequency (MHz) Gain (dB), Efficiency (%) -30 -25 -20 -15 -10 Input Return Loss (dB) Gain Efficiency IRL CW Gain, Efficiency vs Pout Vdd=28V, Idq=0.3A, Freq=912 MHz 0 1 02 03 04 05 0 Pout (W) Gain (dB) Efficiency (%) Gain Efficiency

303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 4 EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Typical Performance Curves in 900 MHz Application Circuit over Temperature IMD3 vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 0 5 10 15 20 Pout (W avg) IMD3 (dBc) t-=-25 t=25 t=-85 2 tone Efficiency vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz 0 5 10 15 20 Pout (W avg) Efficiency (%) t-=-25 t=25 t=-85 Efficiency vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=912 MHz 01 0 2 0 3 0 4 0 Pout (W) Efficiency (%) t-=85 t=25 t=-25 CW Gain vs Pout over Temperature Vdd=28V, Idq=300mA, Freq=920 MHz 0 1 02 03 04 0 Pout (W) Gain (dB) t-=85 t=25 t=-25

303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 5 EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Impedance Data Frequency (MHz) Zsource Zload 850 0.9 - j 0.7 2.6 - j 0.5 895 0.8 - j 0.7 2.4 - j 0.4 960 0.7 - j 0.9 2.3 - j 0.1 Zsource and Zload are the optimal impedances presented to the SLD-3091FZ when operating at 28V, Idq=300mA, Pout=30 W PEP Impedances Referenced to Wirebond/PCB Interface. ZloadsourceZ Input Matching Network Output Matching Network Device under test

303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 6 EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET Bill of Materials - 900 MHz Application Circuit

900 MHz Application Circuit Pin Descriptions - 900 MHz Application Circuit

Connector Pin # Function Description J1 Coax RF in RF input to test fixture (50 Ohm system) J2 Coax RF out RF output to test fixture (50 Ohm system) J3 1 Gnd DC ground for D package mod- ule. Also connected to RF ground. J3 2 Gnd DC ground for D package mod- ule. Also connected to RF ground. J3 3 V GS Gate voltage for the SLD3091FZ. Nominally +4Vdc. J3 4 V DS Drain voltage for the SLD3091FZ. Nominally +28Vdc. J3 5 V DS Drain voltage for the SLD3091FZ. Nominally +28Vdc. Component Description Manufacturer PCB Rogers 4350, er=3.5 Thickness=30 mils Rogers J1, J2 Connector, SMA END 0.037” Johnson J3 MTA Post Header, 5 Pin, Rectan- gle, Polarized, Surface Mount AMP C2 Capacitor, Lytic 22F, 35V Panasonic C3, C11 Cap, 0.1 mF, 100V, 10%, 1206 Johanson C5, C13 Cap, 1000pF, 100V, 10%, 1206 Johanson C7 Capacitor, Lytic 220uF, 50V Panasonic C1,C4,C6, C8,C19 CAP , 68PF,250V,5%,0603 ATC C10,C12, C14 CAP , 12PF,250V,1%,0603 ATC C15,C16 CAP , 10PF,250V,1%,0603 ATC C17 CAP, 7.5 PF, 250V,0603 ATC C18 CAP , 27PF,250V,5%,0603 ATC C2 CAP , 0.22UF, 50V, CERAMIC, X7R, 1206, Kemet C9 CAP, 4.3 PF, 250V,

0603 ATC

R2 RES, 560, 1/16W, 5%, 0402 Panasonic R1 RES, 0.0, 1/16W, 5%, 0402 Panasonic Mounting Screws 4-40 X 0.250” Various

303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 7 EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET

900 MHz Application Circuit Heatsink

To receive Gerber files, DXF drawings, and assembly recommendations for the test board with fixture, contact applications support at support@sirenza.com.

303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 8 EDS-104668 Rev C Preliminary SLD-3091FZ 30 Watt LDMOS FET PIN 1. DRAIN PIN 2. GATE PIN 3. SOURCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. ADHESIVE FROM LID MAY EXTEND A MAXIMUM OF 0.020" BEYOND EDGE OF LID. 4. LID MAY BE MISALIGNED TO THE BODY OF THE PACKAGE BY A MAXIMUM OF 0.008" IN ANY DIRECTION. DIM A B C D E F G H J INCHES MIN MINMAX MAX 0.225 0.004 0.149 0.077 0.355 0.210 0.795 0.697 DIA 3.30 17.70 20.19 5.33 9.02 1.96 3.78 0.102 5.720.235 0.006 0.178 0.087 0.365 0.220 0.805 0.703 17.86 20.45 5.59 9.27 2.21 4.52 0.152 5.97 DIA 0.130 MILLIMETERS Package Outline