SLD-2000 SIRENZA | Alldatasheet

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The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for in accuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Phone: (800) SMI-MMIC http://ww w.sirenza.com Broomfield, CO 80021 1 EDS-104292 Rev C Sirenza Microdevices’ SLD2000 is a robust 12 Watt, high performance LDMOS transistor die, designed for operation from 10 to 2700MHz. It is an excellent solution for applications requiring high linearity and effi- ciency. The SLD2000 is typically used as a driver or output stage for power amplifier, or transmitter applications. These robust power tran- sistors are fabricated using Sirenza’s high performance XEMOS IITM process. RF Specifications Symbol Parameter Unit Min Typ Max Frequency Frequency of Operation MHz 10 - 2700 Gain 10 Watt CW, 902 - 928MHz dB - 19 - Efficiency Drain Efficiency at 10 Watt CW, 915MHz % - 47 - Linearity 3 rd Order IMD at 10 Watt PEP (Two Tone), 915MHz dBc - -32 - Linearity 1dB Compression (P 1dB)W - 1 2 - RTH Thermal Resistance (Junction-to-Case, mounted in package) ºC/W - 4 - Functional Schematic Diagram SLD-2000

12 Watt Discrete LDMOS FET -Bare Die

Applications

  • 12 Watt Output P1dB
  • Single Polarity Operation
  • 19dB Gain at 900 MHz
  • XeMOS IITM LDMOS
  • Integrated ESD Protection, Class 1B
  • Aluminum Topside Metallization
  • Gold Backside Metallization
  • Base Station PA Driver
  • Repeaters
  • Military Communications
  • RFID
  • GSM, CDMA, Edge, WDCDMA Product Description Drain Manifold Gate Manifold Source - Backside Contact ESD Protection Test Conditions: Mounted in ceramic package and tested in Sirenza Evaluation Board VDS = 28.0V, IDQ = 150mA, TMounting Surface = 25ºCT DC Specifications Symbol Parameter Unit Min Typical Max gm Forward Transconductance @ 125mA IDQ, VDS=28V mA / V 590 VGS Threshold I DS=3mA V 3.0 3.8 5.0 VDS Breakdown 1mA V DS current V 65 70 Ciss Input Capacitance (Gate to Source) VGS=0V, VDS=28V pF 27.5 Crss Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V pF 0.8 Coss Output Capacitance (Drain to Source) VGS=0V, VDS=28V pF 14.7 RDSON Drain to Source Resistance, VGS=10V VDS=250mV R 0.6 0.75

SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 2 EDS-104292 Rev C Pad #3 Backside Source = Ground ESD Protection Pad #1 Gate Manifold Pad #2 Drain Manifold Contact Description Pad # Function Description 1 Gate Aluminum metallized manifold MOSFET Gate wi th ESD protection structure. (Topside contact) 2 Drain Aluminum metallized manifold MOSFET Drain. (Topside contact) 3 Source Chrome Gold metallized MOSFET Source contact. Appropriate electrical, mechanical and thermal connection required for proper operation. (Backside contact) Absolute Maximum Ratings Parameters Value Unit Drain Voltage (VDS )3 5 V o l t s Gate Voltage (VGS), VDS =0 20 Volts RF Input Power +33 dBm Load Impedance for Continuous Operation Without Damage 10:1 VSWR Output Device Channel Temperature +200 ºC Storage Temperature Range -40 to +150 ºC Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one.Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Quality Specifications Parameter Description Unit Typical ESD Rating Human Body Model Volts 750 MTTF 200oC Channel Hours 1.2 X 106 Pad Diagram Note 1: Gate voltage must be applied to to the device concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly termi- nated on both input and output. Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in thresh- old voltage with LDMOS transistors. Note 3: The threshold voltage (V GSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation.

SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 3 EDS-104292 Rev C De-embedding Information Description Gate Drain Number of Bond Wires 6 9 Length of Bond Wires 0.037 0.040 Height of Bond Wires 0.006 0.007 Pitch of Bond Wires 0.012 0.008 Bond Wire Diameter 0.002 0.002 Impedance Data Frequency (MHz) Zsource Zload 880 0.5 + j 2.5 3.9 + j 4.9 960 0.8 + j 1.3 4.5 + j 3.6 1840 0.7 - j 0.4 1.3 + j 0.0 1960 0.5 -j 1.3 1.3 + j 0.1 2140 0.7 - j 2.3 1.2 + j 0.2 Impedances Referenced to Wirebond/PCB Interface. All Dimensions in Inches. Wirebond Heights Referenced to Top Surface of Die. ZloadsourceZ Input Matching Network Output Matching Network Device under test Zsource and Zload are the optimal impedances presented to the SLD- 2000 when operating at 28V, Idq=150mA, Pout=10 W PEP.

SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 4 EDS-104292 Rev C Typical Performance Curves for packaged die tested in SLD-2083CZ 900 MHz Application Circuit

2 Tone Gain, Efficiency, Linearity vs Pout

Vdd=28V, Idq=125mA, Freq=915 MHz, Delta F=1 MHz 1 3 5 7 9 11 13 Pout (W PEP) Gain (dB), Efficiency (%) -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 IMD (dBc) Gain Efficiency IM3 IM5 IM7 CW Gain, Efficiency vs Pout Vdd=28V, Idq=125mA, Freq=915 MHz 0 2 4 6 8 10 12 14 16 Pout (W) Gain (dB) Efficiency (%) Gain Efficiency CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=125mA, Pout=10W 900 905 910 915 920 925 Frequency (MHz) Gain (dB), Efficiency (%) -24 -20 -16 -12 Input Return Loss (dB) Gain Efficiency IRL

2 Tone Gain, Efficiency, Linearity and IRL vs Frequency

Vdd=28V, Idq=125mA, Pout=10W PEP, Delta F=1 MHz 900 905 910 915 920 925 Frequency (MHz) Gain (dB), Efficiency (%) -60 -50 -40 -30 -20 -10 IMD(dBc), IRL (dB) Gain Efficiency IM3 IM5 IM7 IRL

SLD-2000 10-2700 MHz 12 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 5 EDS-104292 Rev C Die Map AuSi, AuSn, or AuGe eutectic die attach is recommended. AlSi bond wires are recommended. Part Number Ordering Information Die are screened prior to dicing to DC parameters and are shipped per Sirenza application note AN-039 Visual Criteria of Unpackaged Die. Part Number Gel Pack SLD-2000 100 pcs. per pack Dimensions Inches [mm] 0.0850 [2.16] 0.0450 [1.14] GATE DRAIN SOURCE - BACKSIDE CONTACT - NOT SHOWN DIE THICKNESS - 0.004 [0.10]