SLD-1000 SIRENZA | Alldatasheet

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The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for in accuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Phone: (800) SMI-MMIC http://ww w.sirenza.com Broomfield, CO 80021 1 EDS-104291 Rev C Sirenza Microdevices’ SLD-1000 is a robust 4 Watt high performance LDMOS transistor die, designed for operation from 10 to 2700MHz. It is an excellent solution for applications requiring high linearity and effi- ciency. The SLD-1000 is typically used as a driver or output stage for power amplifier, or transmitter applications. These robust power tran- sistors are fabricated using Sirenza’s high performance XEMOS IITM process. RF Specifications Symbol Parameter Unit Min Typ Max Frequency Frequency of Operation MHz 10 - 2700 Gain 3.5 Watts CW, 900 MHz dB - 19 - Efficiency Drain Efficiency at 3.5 Watts CW, 900 MHz % - 43 - Linearity 3rd Order IMD at 3.5 Watts PEP (Two Tone) 900 MHz dBc - -30 - 1dB Compression (P1dB) 900 MHz Watts - 4 - RTH Thermal Resistance (Junction-to-Case, mounted in package) ºC/W - 11 - Functional Schematic Diagram SLD-1000

4 Watt Discrete LDMOS FET -Bare Die

Applications

  • 4 Watt Output P1dB
  • Single Polarity Operation
  • 19dB Gain at 900 MHz
  • XeMOS IITM LDMOS
  • Integrated ESD Protection, Class 1B
  • Aluminum Topside Metallization
  • Gold Backside Metallization
  • Base Station PA Driver
  • Repeaters
  • Military Communications
  • RFID
  • GSM, CDMA, Edge, WDCDMA Product Description Test Conditions: Mounted in ceramic package and tested in Sirenza Evaluation Board VDS = 28.0V, IDQ = 30mA, TMounting Surface = 25ºCT DC Specifications Symbol Parameter Unit Min Typical Max gm Forward Transconductance @ 30mA IDS mA / V 150 VGS Threshold I DS=3mA Volts 3.0 4.2 5.0 VDS Breakdown 1mA I DS Current Volts 65 70 Ciss Input Capacitance (Gate to Source) VGS=0V, VDS=28V pF 5.2 Crss Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V pF 0.2 Coss Output Capacitance (Drain to Source) VGS=0V, VDS=28V pF 3.2 RDSon Drain to Source Resistance, VGS=10V VDS=250mV Ω 3.0 3.5 Drain Manifold Gate Manifold Source - Backside Contact ESD Protection

SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 2 EDS-104291 Rev C Pad #3 Backside Source = Ground ESD Protection Pad #1 Gate Manifold Pad #2 Drain Manifold Contact Description Pad # Function Description 1 Gate Aluminum metallized manifold MOSFET Gate wi th ESD protection structure. (Topside contact) 2 Drain Aluminum metallized manifold MOSFET Drain. (Topside contact) 3 Source Chrome Gold metallized MOSFET Source contact. Appropriate electrical, mechanical and thermal connection required for proper operation. (Backside contact) Absolute Maximum Ratings Parameters Value Unit Drain Voltage (VDS )3 5 V o l t s Gate Voltage (VGS), VDS =0 20 Volts RF Input Power +30 dBm Load Impedance for Continuous Operation Without Damage 10:1 VSWR Output Device Channel Temperature +200 ºC Storage Temperature Range -40 to +150 ºC Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Quality Specifications Parameter Description Unit Typical ESD Rating Human Body Model Volts 750 MTTF 200oC Channel Hours 1.2 X 106 Note 1: Gate voltage must be applied to to the device concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly termi- nated on both input and output. Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in thresh- old voltage with LDMOS transistors. Note 3: The threshold voltage (V GSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Pad Diagram

SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 3 EDS-104291 Rev C De-embedding Information Description Gate Drain Number of Bond Wires 2 3 Length of Bond Wires 0.040 0.040 Height of Bond Wires 0.006 0.006 Pitch of Bond Wires 0.005 0.005 Bond Wire Diameter 0.002 0.002 Zsource and Zload are the optimal impedances presented to the SLD-1000 when operating at 28V, Idq=30mA, Pout=3.5 W PEP. Impedance Data Frequency (MHz) Zsource Zload 880 2.7 + j 13.1 12.5 + j 22.5 960 1.9 + j 10.6 11.8 + j 18.3 1840 1.7 + j 3.4 1.0 + j 4.7 1960 1.3 + j 2.0 1.2 + j 5.7 2140 1.2 + j 0.7 1.7 + j 6.4 ZloadsourceZ Input Matching Network Output Matching Network Device under test Impedances Referenced to Wirebond/PCB Interface. All Dimensions in Inches. Wirebond Heights Referenced to Top Surface of Die.

SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 4 EDS-104291 Rev C Typical Performance Curves for packaged die tested in SLD-1083CZ 900 MHz Application Circuit CW Gain, Efficiency vs Pout Vdd=28V, Idq=50mA, Freq=915 MHz 012345 Pout (W) Gain (dB) Efficiency (%) Gain Efficiency

2 Tone Gain, Efficiency, Linearity vs Pout

Vdd=28V, Idq=50mA, Freq=915 MHz, Delta F=1 MHz 0123456 Pout (W PEP) Gain (dB), Efficiency (%) -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 IMD (dBc) Gain Efficiency IM3 IM5 IM7

2 Tone Gain, Efficiency, Linearity and IRL vs Frequency

Vdd=28V, Idq=50mA, Pout=3W PEP, Delta F=1 MHz 900 905 910 915 920 925 Frequency (MHz) Gain (dB), Efficiency (%) -60 -50 -40 -30 -20 -10 IMD(dBc), IRL (dB) Gain Efficiency IM3 IM5 IM7 IRL CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=50mA, Pout=3W 900 905 910 915 920 925 Frequency (MHz) Gain (dB), Efficiency (%) -20 -16 -12 Input Return Loss (dB) Gain Efficiency IRL

SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 5 EDS-104291 Rev C Die Map 0.030 [0.76] 0.045 [1.14] GATE DRAIN SOURCE - BACKSIDE CONTACT - NOT SHOWN DIE THICKNESS - 0.004 [0.10] Dimensions Inches [mm] AuSi, AuSn, or AuGe eutectic die attach is recommended. AlSi bond wires are recommended. Part Number Ordering Information Die are screened prior to dicing to DC parameters and are shipped per Sirenza application note AN-039 Visual Criteria of Unpackaged Die. Part Number Gel Pack SLD-1000 100 pcs. per pack