DS90C2501 NSC | Alldatasheet
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Features
n Complies with Open LDI and GMCH DVO specification for digital display interfaces n 25 to 65 MHz clock in single pixel in to single pixel out operation. n 50 to 130 MHz clock in single pixel in to dual pixel out operation. n Support 24bit/48bit color TFT LCD with Conventional and Non-Conventional Color Mappings. n Support 16bit/32bit color TFT LCD. n Single pixel transmitter inputs support single pixel GUI interface. n Up scaling/panel fitting supports VGA to SXGA+ output in single pixel input mode at 640x480 @60Hz, 800x600@60Hz, 1024x768@60Hz, 1280x1024@60Hz, 1400x1050@60Hz. n Independent horizontal and vertical scaling. n Support dithering (available for 6-bit color only), programmable smoothing and anti-aliasing filter. n Programmable digital sharpness, edge enhancement and contrast control via gamma correction. n Allow 2% at 200KHz spread spectrum clocking, rejects cycle-to-cycle jitter (+/− 20% of input data bit time). n Programmable LCD panel power sequencing. n Support low voltage swing signal level (1V to 1.8V), 2.5V and 3.3V LVTTL level on CLKINP, CLKINM, D0 to D23, DE, HSYNC and VSYNC pins n Support 2.5V/3.3V LVTTL level on configuration pins n Support 3.3V LVTTL level on GPIO pins n Available in 10mm x 10mm x 1mm 128pin thermally enhanced CSP package. n Two-wire serial communication interface is active during normal as well as power down mode and support data rates up to 400KHz. n TIA/EIA-644, Open LDI, DVO compliance. TRI-STATE® is a registered trademark of National Semiconductor Corporation. DVO is a registered trademark of Intel Corporation. AGP or 4x AGP is a registered trademark of Intel Corporation. October 2003 DS90C2501 Transmitter with built-in scaler for LVDS Display Interface (LDI) © 2003 National Semiconductor Corporation DS200045 www.national.com
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Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC) −0.3V to +2.8V Supply Voltage (VCC3V) −0.3V to +3.6V CMOS/TTL Input Voltage −0.3V to V CC3V CMOS/TTL Output Voltage −0.3V to (V CC + 0.3V) LVDS Driver Output Voltage −0.3V to (V CC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 sec.) +260˚C Typical Package Power Dissipation Capacity @ 70˚C and Max VCC DS90C2501 1.8W Maximum Operating Case Temperature: 97˚C (measured at top center of package) ESD Rating: DS90C2501 (HBM, 1.5kΩ, 100pF) > 2k V (EIAJ, 0Ω, 200pF) > 250 V Recommended Operating Conditions Min Nom Max Units All Supply Voltage except (VCC3V) 2.250 2.5 2.750 V VCC3V Supply Voltage 3.0 3.3 3.6 V Operating Free Air Temperature (TA) 0 +25 +70 ˚C Supply Noise Voltage (V CC) up to 33Mhz 100 mVP-P DC Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS (All input pins when operate in LVTTL level except DUAL pin. Note: On ID0, ID1 pins have typical 30K ohm internal pull-down, and ID2 and ID3 pins have typical 3K ohm internal pull-down.) VIH High Level Input Voltage V REF =V CC3V 2.0 V CC3V V VIL Low Level Input Voltage V REF =V CC3V -0.3 0.8 V VCL Input Clamp Voltage I CL = 18 mA -0.9 -1.5 V IIN Input Current V IN = 0.4V, or V CC +1.8 +15 µA VIN = GND −15 0 µA LVCMOS/LVTTL DC SPECIFICATIONS for DUAL pin, pin35 V IH DUAL High Level Input Voltage (for dual pixel in to dual pixel out). P D=V CC3V 2.0 V CC V VIM DUAL High Level Input Voltage (for single pixel in to dual pixel out). P D=V CC3V 1⁄2VCC−0.1 1⁄2VCC 1⁄2VCC+0.1 V VIL DUAL High Level Input Voltage (for single pixel in to single pixel out). P D=V CC3V 0 0.4 V VCL Input Clamp Voltage I CL = 18 mA -0.9 -1.5 V IIN Input Current V IN = 0.4V, VCC 1.8 15 µA VIN = Gnd -15 0 µA LVCMOS/LVTTL DC SPECIFICATIONS for MSEN, pin 98 V OL Low level Open Drain Output Voltage IOL = 2 mA 0.1 0.3 V LVCMOS/LVTTL DC SPECIFICATIONS (Pin 62 to pin 69 when operate in 3.3V LVTTL level) VOH High Level Input Voltage I OL = 2 mA 2.2 2.95 V VOL Low Level Input Voltage 0.055 0.4 V IOS Output Short Circuit Current V OUT = 0V -50 −120 mA DS90C2501 www.national.com3
Two-Wire Serial Communication Interface Unless otherwise noted, below specifications apply for V CC3V pin = 3.0V to 3.6V. Symbol Parameter Conditions Min Typ Max Units VIN(1) Logica l“1” input voltage 2.1 V VIN(0) Logica l“0” input voltage 0.8 V VOL Serial Bus Low level output voltage IOL = 3mA 0.1 0.4 V IOL = 6mA 0.15 0.6 V Recommended DVO Port Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units TCIT TxCLK IN Transition Time ( Figure 4) DUAL = Gnd 0.8 1.2 2.4 ns TCIP TxCLK IN Period ( Figure 5) DUAL = Gnd 5.9 T 40 ns TCIH TxCLK in High Time ( Figure 5) 0.35T 0.5T 0.65T ns TCIL TxCLK in Low Time ( Figure 5) 0.35T 0.5T 0.65T ns TXIT D0 to D23 Transition Time 1 ns VDDQ Low Swing Voltage Amplitude from GMCH 1.0 1.8 V DS90C2501 www.national.com5
AC Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time ( Figure 3). (Note 7) 0.14 0.8 ns LHLT LVDS High-to-Low Transition Time ( Figure 3). (Note 7) 0.11 0.8 ns TBIT Transmitter Output Bit Width DUAL pin = V CC or Gnd 1/7 TCIP ns DUAL pin = 1⁄2VCC 2/7 TCIP ns TCCS TxOUT Channel to Channel Skew 100 ps TPPOS0 Transmitter Output Pulse Position for Bit 0 (previous cycle) from CLK1P rising edge (Note 7). f = 65 MHz, DUAL pin CC −0.49 0 +0.49 ns TPPOS1 Transmitter Output Pulse Position for Bit1 (previous cycle) from CLK1P rising edge. (Note 7) f = 65 MHz, DUAL pin CC (1/7)TCIP −0.49 (1/7)TCIP (1/7)TCIP +0.49 ns TPPOS2 Transmitter Output Pulse Position for Bit2 from CLK1P rising edge. (Note 7) f = 65 MHz, DUAL pin =V CC (2/7)TCIP −0.49 (2/7)TCIP (2/7)TCIP +0.49 ns TPPOS3 Transmitter Output Pulse Position for Bit3 from CLK1P rising edge. (Note 7) f = 65 MHz, DUAL pin =V CC (3/7)TCIP −0.49 (3/7)TCIP (3/7)TCIP +0.49 ns TPPOS4 Transmitter Output Pulse Position for Bit4 from CLK1P rising edge. (Note 7) f = 65 MHz, DUAL pin =V CC (4/7)TCIP −0.49 (4/7)TCIP (4/7)TCIP +0.49 ns TPPOS5 Transmitter Output Pulse Position for Bit5 from CLK1P rising edge. (Note 7) f = 65 MHz, DUAL pin =V CC (5/7)TCIP −0.49 (5/7)TCIP (5/7)TCIP +0.49 ns TPPOS6 Transmitter Output Pulse Position for Bit6 from CLK1P rising edge. (Note 7) f = 65 MHz, DUAL pin =V CC (6/7)TCIP −0.49 (6/7)TCIP (6/7)TCIP +0.49 ns TSTC DxIN Setup to CLKINP ( Figure 6) (Note 7) 0.8 ns THTC DxIN Hold to CLKINP ( Figure 6) (Note 7) 0.8 ns TJCC Transmitter Jitter Cycle-to-cycle (Note 4) f = 85 MHz, DUAL pin = Gnd 114 ps f = 54 MHz, DUAL pin =V CC 114 ps TPLLS Transmitter Phase Lock Loop Set ( Figure 7) (Note 7) 10 ms TPDD Transmitter Powerdown Delay ( Figure 8) (Note 7) 100 ns Transmitter Input to Output Latency for single in-to-dual out mode. Figure 9 f = 170 MHz (Note 6) 1.5 TCIP +4.1 ns DS90C2501 www.national.com 6
ing relationship between SCL and SDA signals related to the DS90C2501. should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for V CC = 2.5V and V CC3V = 3.3V at T A = +25˚C. specified (except VOD and ∆VOD). calculating system margin as described in AN-1059. interference (both dependent on type/length of cable) and clock jitter. RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle). Note 6: From V = 1.25V of CLKINP to V DIFF = 0V of CLK1P when EDGE pin = Gnd, DUAL pin = Gnd or V CC or 1⁄2VCC , BAL pin= Gnd. FIGURE 1. “Alternate High/Low” Test Pattern in 12-bit Input Mode(Note 8)
Note 8: The “Alternate High/Low” test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. to produce groups of 16 vertical stripes across the display. FIGURE 2. “16 Grayscale” Test Pattern in 12-bit Input Mode(Note 9)
Pin Name Pin No. I/O Type Description DVO INTERFACE D0–D23 17, 16, 15, 14, 13, 12, 9, 8, 7, 6, 5, 4, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21 I-LVTTL/ Low Swing (See V REF signal
description
Swing) DVO Port RGB input data When DUAL pin = GND inputs D0–D11 correspond to LVDS ports A0–A3. When DUAL pin = 1⁄2VCC, 1st pixel from D0–D11 corresponds to LVDS ports A0–A3, 2nd pixel from D0–D11 corresponds to LVDS ports A4–A7. When DUAL pin = V CC, 1st pixel from D0–D11 corresponds to LVDS ports A0–A3, 2nd pixel from D12–D23 corresponds to LVDS ports A4–A7. Note: Ports refer to the corresponding differential LVDS pin pairs. The port A nomenclature should not be confused with the serial interface slave address pins AO-A2. DE 3 I-LVTTL/ Low Swing Display Data Enable. When High, input pixel data is valid to DS90C2501 when R_FDE bit = High (default). See RFDE register field for more information . HSYNC 2 I-LVTTL/ Low Swing Display Horizontal Sync input control signal. VSYNC 1 I-LVTTL/ Low Swing Display Vertical Sync input control signal. CLKINP 10 I-LVTTL/ Low Swing Differential “Positive” differential pixel clock input. A differential clock is recommended for applications 65 MHz or higher. CLKINM 11 I-LVTTL/ Low Swing Differential “Minus” differential pixel clock input. A differential clock is recommended for applications 65 MHz or higher. HOST INTERFACE RESETN 61 I-LVTTL 2.5 Active low RESET signal. Asserting RESETN will reset all internal logic and clear the Host Interface registers. S2CCLK 72 I-LVTTL3V This is the clock line for the two-wire serial communication interface. Normally a pull-up resistor is required in the system. S2CDAT 71 I/O-LVTTL3V This is the data line for two-wire serial communication interface. A Pull-up resistor is normally required in the system. MSEN 98 O-LVTTL 2.5 Interrupt signal. This is an open drain output, a pull-up resistor is required. Please refer to MDI, RSEN, TSEL and MSEL register fields in Register Field Definitions for more information. This signal requires support from host software. PD 99 I-LVTTL 2.5 Power Down Signal. A logic “0” will place the device in power down mode per Table 1below. When maximum power savings is desired, the PD pin or soft power down bit (Reg 08h bit 0) should be used to power down the DS90C2501. LVDS outputs of the device will be in TRI-STATE. Scaling engine will be powered down, and retain all register values. PLL will be powered down. All data input pads will be powered down. V REF circuit is powered down. The two-wire serial communication interface remains active and all register contents will be retained. All GPIO pins will be disabled (tri-state if programmed as an output). ENAVDD, ENABKL, PWM, VSTALL and HIRQ pins remain active and can be accessed through the two-wire serial communication interface. CLOCK REFCLK1 18 I-LVTTL3V Reference clock, — A 3V, 14.318 MHz clock is required for internal control and timing. This clock must be stable when the DS90C2501 is powered-up. DS90C2501 www.national.com 12
DS90C2501 Pin Description (Continued) Pin Name Pin No. I/O Type Description OPTION SELECTION BAL 97 I-LVTTL 2.5 Tie this pin to GND. DUAL 35 I-LVTTL 2.5 LVTTL level input. Input = GND for single pixel in-to-single pixel out mode. LVDS output channels A0 to A3 are enabled, A4 to A7 are CLK2 are disable. Input = V CC for dual pixel in-to-dual pixel out mode. LVDS output channel A0 to A7, CLK1 and CLK2 are enable. Use a 10K typ. pull-up resistor. Input = 1⁄2VCC for single pixel in-to-dual pixel out mode. LVDS output channel A0 to A7, CLK1 and CLK2 are enabled. See register CFG1 (08h) BPASS field for more information. See Figure 11for example interface circuit. COLOR 34 I-LVTTL 2.5 LVTTL level input to select RGB to LVDS color mapping. Tie to GND for 18-bit/36-bit LCD. Tie to GND to select conventional color mapping for 24-bit/48-bit LCD. Tie to Logic “1” to select non-conventional color mapping for 24-bit/48-bit LCD. A0, A1, A2 115, 116, 117 I-LVTTL 2.5 These are input pins to select the 2-wire Serial Communication Slave Device Address Lower Bits. EDGE 36 I-LVTTL 2.5 Selects primary clock edge E1. Tie to Logic “1” to select Rising edge for E1. Tie to ground to select Falling edge for E1. PANEL INTERFACE A0P, A1P, A2P, A3P 55, 53, 51, 47 O-LVDS Positive LVDS differential data output. When DUAL pin = GND, input to D0–D11 will be coming out of A0P to A3P. For 6-bit color application, no connect for channel A3P. When DUAL pin = 1⁄2VCC, the first pixel going in D0–D11 will be coming out of A0P to A3P, and the second pixel going in D0–D11 will come out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. When DUAL pin = V CC, the first pixel going in D0–D11 will be coming out of A0P to A3P, the second pixel going in D12–D23 will be coming out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. A0M, A1M, A2M, A3M 56, 54, 52, 48 O-LVDS Negative LVDS differential data output. When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M. For 6-bit color application, no connect for channel A3M. When DUAL pin = 1⁄2VCC, the first pixel going in D0–D11 will be coming out of A0M to A3M, and the second pixel going in D0–D11 will come out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. When DUAL pin = V CC, the first pixel going in D0–D11 will be coming out of A0M to A3M, the second pixel going in D12–D23 will be coming out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. A4P, A5P, A6P, A7P 45, 43, 41, 39 O-LVDS Positive LVDS differential data output for second pixel. When DUAL pin = GND, input to D0–D11 will be coming out of A0P to A3P. For 6-bit color application, no connect for channel A3P. When DUAL pin = 1⁄2VCC, the first pixel going in D0–D11 will be coming out of A0P to A3P, and the second pixel going in D0–D11 will come out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. When DUAL pin = V CC, the first pixel going in D0–D11 will be coming out of A0P to A3P, the second pixel going in D12–D23 will be coming out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. DS90C2501 www.national.com13
DS90C2501 Pin Description (Continued) Pin Name Pin No. I/O Type Description OPTION SELECTION A4M, A5M, A6M, A7M 46, 44, 42, 40 O-LVDS Negative LVDS differential data output for second pixel. When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M. For 6-bit color application, no connect for channel A3M. When DUAL pin = 1⁄2VCC, the first pixel going in D0–D11 will be coming out of A0M to A3M, and the second pixel going in D0–D11 will come out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. When DUAL pin = V CC, the first pixel going in D0–D11 will be coming out of A0M to A3M, the second pixel going in D12–D23 will be coming out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. CLK1P 49 O-LVDS Positive LVDS differential clock output. CLK1M 50 O-LVDS Negative LVDS differential clock output. CLK2P 37 O-LVDS Additional positive LVDS differential clock output pin. Identical to CLK1P. No connect if not used. CLK2M 38 O-LVDS Additional negative LVDS differential clock output pin. Identical to CLK1M. No connect if not used. ID0, ID1, ID2, ID3 57, 58, 59, 60 I-LVTTL 2.5 These four pins are used to select one out of 16 pre-determined LCD display timing information. The values are from 0 to 15. This function requires support from VBIOS or display driver. Tie these pins to GND when not in use. Tie these four pins [ID3, ID2, ID1, ID0] to High or Low for selecting LCD panel. ID0 is the LSB, and ID3 is the MSB. For example: 1000 will select the 9th LCD panel. A 4-bit register field [3:0] will be used to store the selected value for the host to read. See PANEL field for more information. ENAVDD 69 O-LVTTL 2.5 Output to control LCD panel power under software control. Typically, this output is used with a power switch such as a FET circuit to control LCD panel V CC (Note 11). ENABKL 68 O-LVTTL 2.5 Output to control LCD panel back light power under software control. Typically, this output is used to control the enable on a backlight inverter (Note 11). MISCELLANEOUS/TEST GPIO1, GPIO2, GPIO3 64, 63, 62 I/O-LVTTL 3V General purpose inputs or outputs referenced to GND. When the device is powered up, this pin defaults to an input. When the scaler is in the power down state these signals are tri-state if programmed as outputs (Note 11). CLK_INV 114 I-LVTTL 2.5 This pin is used to invert the polarity of the incoming pixel CLK (CLKINP/CLKINM). A logic 0 = Normal, Logic 1 = Invert. RES2 70 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal operation. RES3 113 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal operation. RES4 100 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal operation. PWM 67 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This pin should be left open in normal operation. VSTALL 66 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This pin should be left open in normal operation. HIRQ 65 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This pin should be left open in normal operation. DS90C2501 www.national.com 14
DS90C2501 Pin Description (Continued) Pin Name Pin No. I/O Type Description OPTION SELECTION V REF 83 I-ANALOG This pin is never to be left floating and never tie to GND. For LVTTL level data input, tie V REF to VCC3V. When VREF > 1.8V, input data is set to LVTTL level. For low voltage swing level data input, tie V REF to 1⁄2VDDQ (VDDQ provided by host interface) VDDQ is from the host. When V REF <=1.0V, indicates input data is in low voltage swing mode. Input data = logic High = V REF +100 mV in low voltage swing level. Input data = logic Low = V REF −100 mV in low voltage swing level. TST1, TST2, TST3 19, 20, 85 I-LVTTL 2.5 These pins are used in production testing and should be tied to GND in normal operation. POWER (See Application Information for power supply decoupling requirements) V CC/DVCC 81, 82, 75, 77, 96, 119, 123, 125 PWR Power supply pins (pin 75, 77, 81, 82, 96, 119, 123, and 125) for 2.5V LVTTL inputs and digital circuitry. GND/DGND 33, 73, 74, 76, 78, 79, 80, 84, 118, 122, 124 PWR GND or DGND reference for 2.5V TTL inputs and digital circuitry. V CC3V 121, 127 PWR The V CC3V is required for internal logic and certain 3V I/O. During power up stage, voltage readings on these pins must be higher than 2.5V pins. GND3V 120, 126, 128 PWR Ground return pins for V CC3V powered logic. SPLLVCC 87, 89 PWR 2.5V power supply pins for scaler PLL circuitry. It is not recommended to share this power with PLLV CC. SPLLGND 86, 88, 90 PWR Ground returns for scaler PLL circuitry. PLLV CC 92, 94 PWR 2.5V power supply pins for Tx PLL circuitry. It is not recommended to share this power with SPLLV CC. PLLGND 91, 93, 95 PWR Ground returns for Tx PLL circuitry. LVDSV CC 105, 109 PWR Power supply pins for LVDS output drivers. LVDSGND 104, 108 PWR Ground return pins for LVDS output drivers. LVDSV CC3V 101, 103, 107, 111 PWR 3V power supply pins for LVDS output drivers. During power up stage, voltage readings on these pins must be higher than 2.5V pins. LVDSGND3V 102, 106, 110, 112 PWR Ground return pins for 3V LVDS outputs. Note 11: When device power is applied, it is possible for these outputs to switch to a logic “1” momentarily as the 3.3V is rising and before 2.5V reaches at least 0.8V. During this brief period, the pad control logic could be non-deterministic, RESETN will have no effect. It is recommended these outputs are gate d externally if the system design requires them to remain in the inactive logic “0” state during power-on. DS90C2501 www.national.com15
TABLE 1. scaler is powered down under these conditions All registers are predefined as read only, or read and write. address byte, data register address byte, a data byte.
- If the location latched in the data register addresses is
address byte, followed by retrieving the data byte.
- If the data register address needs to be set, then a slave
byte and receive data byte to accomplish a read.
Host Control Register Descriptions(Continued) Bit Description 7:0 Vendor ID Low Byte Register Name: VND_IDH Address Offset: 01h Default Value: 13h Access Method: Read Only Bit Description 7:0 Vendor ID High Byte Register Name: DEV_IDL Address Offset: 02h Default Value: 26h Access Method: Read Only Bit Description 7:0 Device ID Low Byte Register Name: DEV_IDH Address Offset: 03h Default Value: 67h Access Method: R/W Bit Description 7:0 Device ID High Byte Register Name: DEVICE REVISION Address Offset: 04h Default Value: 01h Access Method: R/W Bit Description 7:0 Device Revision Value Register Name: RESERVED Address Offset: 05h Default Value: A5h Access Method: Read Only Bit Description 7:0 Reserved Register Name: FRQ_LOW Address Offset: 06h Default Value: 19h Access Method: Read Only Bit Description 7:0 Minimum LVDS Output Frequency (25 MHz) Register Name: FRQ_HIGH Address Offset: 07h Default Value: See Description Access Method: Read Only Bit Description 7:0 Maximum LVDS Output Frequency If DUAL = GND or V CC value is A2h (162 MHz) If DUAL = 1⁄2VCC value is 55h (85 MHz) DS90C2501 www.national.com 18
Host Control Register Descriptions(Continued) Register Name: CFG1 Address Offset: 08h Default Value: 39h Access Method: R/W Bit Description
0 Soft Power Down; 0 = Power Down, 1 = Normal Operation
1 Reserved
2 BPASS (1 = bypass, 0 = non-bypass)
This field is valid only when DUAL pin is 0V or 1⁄2VCC. Note: When image scaling is not required power savings can be achieved in bypass mode.
3 DSEL
0= Input clock is differential (recommended for clocks above 65 MHz), 1= input clock is single-ended
4 HEN (HSYNC enable)
0= HSYNC is transmitted as a fixed low, 1= HSYNC is same as input
5 VEN (VSYNC enable)
0= VSYNC is transmitted as a fixed low, 1= VSYNC is same as input 7:6 Reserved DS90C2501 www.national.com19
Host Control Register Descriptions(Continued) Register Name: CFG2 Address Offset: 09h Default Value: 95h Access Method: R/W Bit Description
0 MDI (read only)
2 RSEN (read only) — Receiver Sense
0= LVDS receiver connected to transmitter output, 1= No receiver connected Note: this function is valid only with DC coupled systems
3 TSEL — Interrupt generation
0= Interrupt bit (MDI) is generated by monitoring RSEN, fixed valve 4:6 MSEL (R/W) — Selects source for MSEL output pin 000= MSEN disabled 001= Output the MDI bit - interrupt 010= Output the RSEN bit - receiver detect 011–111= Reserved
7 VLOW (read only)
1= V REF set for low swing, 0= V REF set for LVTTL Register Name: CFG3 Address Offset: 0Ah Default Value: 81H Access Method: R/W Bit Description
0 R_FDE- Input DE strobe Polarity Select
0 = DE active Low, 1 = DE active High 3:1 Reserved 7:4 Reserved Register Name: CFG Address Offset: 0Bh Default Value: See Description Access Method: Read Only Bit Description 7:0 Contains state of input data bits 23:16 Register Name: PANEL Address Offset: 0Ch Default Value: See Description Access Method: R/W Bit Description 0:3 System defined Panel ID values set on ID0:3 pins (Read Only) 4:7 System defined Panel ID field which can be written/ read from host DS90C2501 www.national.com 20
2 PLLOCK (Read Only)
3 Reserved (Read Only)
TABLE 2. LVDS data bit naming convention
TABLE 3. Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-single pixel out application
TABLE 4. Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-dual pixel out application
TABLE 4. Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-dual pixel out application
TABLE 5. Conventional Data Mapping for two 12-bit (two data per clock)dual pixel in-to-dual pixel out
TABLE 5. Conventional Data Mapping for two 12-bit (two data per clock)dual pixel in-to-dual pixel out
TABLE 6. Non-Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-single pixel out
TABLE 7. Non-Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-dual pixel out
TABLE 7. Non-Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-dual pixel out
TABLE 8. Non-Conventional Data Mapping for two 12-bit (two data per clock)dual pixel in-to-dual pixel out application
TABLE 8. Non-Conventional Data Mapping for two 12-bit (two data per clock)dual pixel in-to-dual pixel out application
Note 12: The lower half of the pixel is latched by the primary clock edge E1. Note 13: E3 and E4 only apply when DUAL pin = 1/2 V CC. Note 14: Above figure only valid when R_FDE bit = V CC, DE signal from GUI is set to be active HIGH. Note 16: Single-ended clock is not recommended for operation above 65MHz by GMCH vendor. TABLE 9. 12-bit (two data per clock) input application data mapping with GMCH. Note 17: Color notation: R = RED, G = GREEN, B = BLUE. Note 18: Bit significance within a color: [7:0] = [MSB:LSB]. FIGURE 14. How Data is Latched in the DS90C2501
FIGURE 15. 24bit/48bit Conventional Data Inputs Mapped to LVDS Outputs
FIGURE 16. 24bit/48bit Conventional Data Inputs Mapped to LVDS Outputs
FIGURE 17. 24bit/48bit Non-Conventional Data Inputs Mapped to LVDS Outputs
FIGURE 18. 24bit/48bit Non-Conventional Data Inputs Mapped to LVDS Outputs
DVO Input and Bypass Mode: The input single port DVO data is translated into 18bit/24bit RGB data for scaling. Single port data over 108MHz or dual port data will be bypassed and not scaled. The LVDS output can be single or dual port. Input Timing Control: The DS90C2501 input timing control can detect the input timing information such as horizontal and vertical sync width, pixel-total and line-total count and the active video starting and ending positions. Such information can be provided to the host through two-wire serial communication Interface to help determine the input mode. Display Synchronization The DS90C2501 synchronizes the display timing with input graphics timing so that no external frame buffer is needed. There are three operation modes: Free-run mode: No synchronization. Output timing is gener- ated from external 14.318MHz reference clock. Line lock mode: the display Hsync is synchronized with the input line rate. Frame lock mode: the display Vsync is synchronized with the input frame rate. In free-run mode, the display timing is decided by the values programmed into the various timing registers. In line-lock mode, the display line rate is a function of the selected input clock, forcing the output frame rate to be locked to input frame rate. Timing management is more complicated The frame-lock mode is used more often. The output pixel clock and Hsync are generated from the external 14.318MHz ref- erence clock and the embedded PLL, but the Vsync is refreshed at the input frame rate. Gamma Look-up Table (LUT): The DS90C2501 provides an 8-bit look-up-table (LUT) for each input color channel in case gamma correction is needed. The LUT is user programmable to provide an arbi- trary transfer function. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for rising edge strobe or falling edge strobe through a dedicated pin. A rising edge transmitter will inter-operate with a falling edge receiver without any translation logic. Output Timing Control: The DS90C2501 output timing is fully programmable through two-wire serial communication Interface for different panel requirements. When 6-bit color LCD is used, dithering (FRC) can be turned on via two-wire serial communication pro- gramming interface. The least two LSB of each color are default to be logic low all the time. When 8-bit color LCD is used, dithering (FRC) is not needed, and can be turned off via two-wire serial communication programming interface. See DS90C2501 guide for further information on program- ming these features. DS90C2501 www.national.com37
1 Vertical Scaling Region Start
2 Vertical Scaling Region End
3 Horizontal Scaling Region Start
4 Horizontal Scaling Region End
FIGURE 19. Input Timing of DS90C2501 scaler 1of 2 FIGURE 20. Input Timing of DS90C2501 scaler 2 of 2
3 Vertical action region start. 4 Vertical action region end. 5 Total vertical scan-lines in a frame. 8 Horizontal active region start. 9 Horizontal active region end. 10 Total horizontal pixels in a scan-line. FIGURE 21. Display Signal Timing of DS90C2501 scaler 1of 2
- To configure for single pixel in to single pixel out applica-
- Programmable Primary Edge E1: The transmitter is
must agree with the GUI to generate the correct display. TABLE 10. Connection for SISO Operation
TABLE 10. Connection for SISO Operation(Continued)
- To configure for single pixel in to dual pixel out application
mode, outputs A0-to-A7, and CLK1, CLK2 are enabled. TABLE 11. Connection for SIDO Operation
- To configure for dual pixel in to dual pixel out application
note that scaler will be shut down in this configuration. tions were the cooling method is free-air convection. the package to maintain safe operating die temperatures. system components into consideration. center of the case (T CASE) should not exceed 97˚C. FIGURE 24. Junction Temperature vs. Ground Plane Area
FIGURE 25. Recommended Land Pattern Component Side (1) and Wiring Side (2) of Board with Thermal Pads Connected to Ground Plane of PCB.
www.national.com 46
Physical Dimensions inches (millimeters) unless otherwise noted Dimensions show in millimeters Order Number DS90C2501SLB Refer to Application Note AN1125 for more information LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com DS90C2501 Transmitter with built-in scaler for LVDS Display Interface (LDI) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.
Tel: 81-3-5639-7560www.national.com DS90C2501 Transmitter with built-in scaler for LVDS Display Interface (LDI) National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.