SLB9673TPM2.0_V01 INFINEON | Alldatasheet
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Data Sheet Please read the Important Notice and Warnings at the end of this document Revision 1.2 www.infineon.com 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Data Sheet Devices
- SLB 9673XU2.0 FW26.xx
- SLB 9673AU2.0 FW26.xx Key features
- Optimized TPM device for IoT and ICT applications
- Compliant to TPM Main Specification, Family "2.0", Level 00, Revision 01.59
- Certifications: – CC, Version 3.1 Rev.5, level EA L4+, AVA_VAN.4 (moderate) according to TCG PC Client TPM Protection Profile (targeted) – FIPS 140-2 level 2 (physical se curity level 3) (targeted)
- I 2 C i n t e r f a c e
- Random Number Generato r (RNG) implemented according to NIST SP800-90A using entropy source according to NIST SP800-90B
- Full personalization with 4 Endorsement Keys (EK) an d 4 EK certificates (RSA 2048, RSA3072, ECC NIST P256, ECC NIST P384)
- Standard temperature range (- 40°C .. +85°C) or enhanced temperature range (-40°C .. +105°C)
- PG-UQFN-32-1,-2 package
- Optimized for battery operat ed devices: low standby power consumption (typ. 120 µA)
- 24 PCRs (SHA-1, SHA-256 or SHA384)
- 51 kByte NV memory
- Unlimited amount of NV counters (onl y depending on NV memory utilization)
- Up to 3 loaded sessions (TPM_PT_HR_LOADED_MIN)
- Up to 64 active sessions (TPM_PT_ACTIVE_SESSIONS_MAX)
- Up to 3 loaded transient Obje cts (TPM_PT_HR_TRANSIENT_MIN)
- Up to 7 loaded persistent Objects (TPM_PT_HR_PERSISTENT_MIN)
- Pre-generation of up to 7 RSA key pairs
- RSA key generation (1024, 2048, 3072 and 4096 bit)
- ECC (NIST P256, BN P256, NIST P384)
- SHA1, SHA256, SHA384
Data Sheet 2 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 About this document Scope and purpose This data sheet describes the OPTIGA™ TPM SLB 9673 FW 26.xx Trusted Platform Modu le together with its features, functionality and programming interface. Intended audience This data sheet is primarily intended for system developers.
Data Sheet 3 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Table of contents Table of contents
Data Sheet 5 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 List of tables List of tables
Data Sheet 6 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Overview
1 Overview
The OPTIGA™ TPM SLB 9673 is a Trusted Platform Module. It is available in PG-UQFN-32-1,-2 package. It supports an I2C interface with a transfer rate of up to 1 MHz. The OPTIGA™ TPM SLB 9673 is a TPM based on TCG family 2.0 specifications (see [1] and [2]). This TPM product is targeted to be certified, using the Comm on Criteria for Information Technology Security Evaluation (CC), Version 3.1 Rev.5, in the level EAL4+, AVA_VAN.4 (mod erate), ALC_FLR.1 according to the Protection Profile PC Client Specif ic TPM, TPM Library Specification Family "2.0" Level 0 Revision 1.59 (CERTIFICATE <tbd>1)).
1.1 Power management
In the OPTIGA™ TPM SLB 9673, power mana gement is handled internally; no explicit power-down or standby mode is available. The device automatically enters a low-power state after each successful command/response transaction. If a transaction is starte d on the I2C bus from the host platform, the device will wake immediately and will return to the low-power mode after the transaction has been finished.
1.2 Device address
The I2C interface uses 7-bit addressing. The default address of the device is 0x2E (also see [2]).
2 Device types and ordering information
The OPTIGA™ TPM SLB 9673 product family features devices using an UQFN package. Table 1 shows the available versions. 1) Exact reference not yet availabl e at document generation time Table 1 Device configuration Device Name Package Remarks SLB 9673XU2.0 FW26.xx PG-UQFN-32-1,-2 Stan dard temperature range -40°C - 85°C SLB 9673AU2.0 FW26.xx PG-UQFN-32-1,-2 Enha nced temperature range -40°C - 105°C
Data Sheet 7 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Pin description
3 Pin description
Figure 1 Pinout of the OPTIGA™ TPM SLB 9673 (PG-UQFN-32-1,-2 package, top view) Table 2 Buffer types Buffer type Description TS Tri-state pin ST Schmitt-trigger pin OD Open-drain pin Table 3 I/O Signals Pin number Name Pin type Buffer type Function PG-UQFN-32-1,-2
30 SCL I ST I2C bus clock signal
The clock signal of the I2C bus.
29 SDA I/O TS I2C bus data signal
The data signal of the I2C bus.
18 I2C_PIRQ# O OD Interrupt signal
This pin can be connected to the host interrupt controller to allow interrupt driven reads of the response data instead of polling. As soon as a response is available, the signal is asserted (low) and remains active until the complete response is read by the host.
17 RST# I ST Reset
External reset signal. Asserting this pin unconditionally resets the device. The signal is active low. This pin has a weak internal pull-up resistor. GND NCI NCI NCI NCI VDD NCI NCI/GND NC GND NCI SCL SDA NCI NCI NCI NCI TPM SLB 9673AU2.0 PG-UQFN-32-1,-2 10 15 2630 GND VDD NC TEST# NC I2C_PIRQ# RST# VDD GND GPIO_00 GPIO_01 NCI NC GPIO_02 NCI/VDD
Data Sheet 8 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Pin description
20 TEST# I ST Test
Test signal, must be externally connected to a static high level. 3G P I O _ 0 0 I / O T S General purpose IO This pin may be left unconnected; it has an internal pull-up resistor. It can be controlled via TPM NV GPIO functionality. 4G P I O _ 0 1 I / O T S General purpose IO This pin may be left unconnected; it has an internal pull-up resistor. It can be controlled via TPM NV GPIO functionality. 7G P I O _ 0 2 I / O T S General purpose IO This pin may be left unconnected; it has an internal pull-up resistor. It can be controlled via TPM NV GPIO functionality. Table 4 Power supply Pin number Name Pin type Buffer type Function PG-UQFN-32-1,-2 1, 14, 22 VDD PWR — Power supply All VDD pins must be connected externally and should be bypassed to GND via 100 nF capacitors. 2, 9, 23, 32 GND GND — Ground All GND pins must be connected externally. Table 5 Not connected Pin number Name Pin type Buffer type Function PG-UQFN-32-1,-2 6, 19, 21, 24 NC NU — No connect All pins must not be connected externally (must be left floating). 5, 10 - 13, 15, 25 - 28, 31 NCI — — Not connected internally All pins are not connected internally (can be connected externally). 8N C I / V D D — — Not connected internally/VDD This pin is not connected internally (can be connected externally). Note that pin 8 is defined as VDD in the TCG specification [2]. To be compliant, VDD can be connected to this pin.
16 NCI/GND — — Not connected internally/GND
This pin is not connected internally (can be connected externally). Note that pin 16 is defined as GND in the TCG specification [2]. To be compliant, GND can be connected to this pins. Table 3 I/O Signals (continued) Pin number Name Pin type Buffer type Function PG-UQFN-32-1,-2
Data Sheet 9 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Pin description
3.1 Typical schematic
Figure 2 shows the typical schematic for the OPTIGA™ TPM SLB 9673. The power supply pins should be bypassed to GND with capacitors located close to the device. Figure 2 Typical schematic SLB 9673 SCL SDA I2C_PIRQ# SDA I2C_PIRQ# VDD GND 3.3V (1.8V) 2x 100 nF (place close to device VDD/GND pins) GPIO_00 NC/NCI SCL 1 μF RST#RESET# GPIO_01 GPIO_02 TEST# 3.3V (1.8V) RPU* * Pull-up resistors are needed on I2C bus
Data Sheet 10 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 TPM properties
4 TPM properties
Properties defined within the TPM ca n be read with the command TPM2_G etCapability. The values are vendor dependent or determined by a platform-specific specific ation. The following proper ties are returned by the Infineon OPTIGA™ TPM SLB 9673 using the co mmand TPM2_GetCapability (capability = TPM_CAP_TPM_PROPERTIES):
4.1 TPM register polling
Processing of accesses to registers creates a load on the TPM. If registers are polled in quick succ ession, the time until the TPM reaches the target state is increased, which decreases performance and may even lead to violation of maximum timeout values. To prevent this, a minimum delay between register read accesses must be respected when polling:
- Minimum delay between TPM register reads for polli ng of TPM_STS_x during command execution: 1 ms
- Minimum delay between TPM register reads for po lling of TPM_STS_x after device reset before commandReady set: 1 ms
- Minimum delay between TPM register reads fo r all other TPM register polling, including TPM_STS_x.commandReady set between command, TPM_STS_x.valid and TPM_STS_x.burstCount: 100 µs Table 6 Infineon TPM property values TPM_PT_MANUFACTURER “IFX” TPM_PT_VENDOR_STRING_3 NULL TPM_PT_VENDOR_STRING_4 NULL TPM_PT_FIRMWARE_VERSION_1 Major and mi nor version (for instance, 0x001A000A indicates V26.10) 1) The build- and version numbers given he re are examples and do not necessarily match the numbers of the device this data sheet has been provided for. TPM_PT_FIRMWARE_VERSION_2 Build number and Common Criteria certification state (for instance, 0x00413000 or 0x00413002)1) Byte 1: reserved for future use (0x00) Byte 2 and 3: Build number (for instance, 0x4130)1) Byte 4: Common Criteria certification state/mode: 0x00 = TPM operational mode/TPM is CC certified 0x02 = TPM operational mode/TPM is not certified 0x60 = Manually entered TPM firmware recovery mode (triggered externally for testing purposes) 0x61 = TPM firmware recovery mode (triggered by code integrity failure detection) 0x62 = TPM firmware update mode TPM_PT_MODES Bit 0 (FIPS_140_2) = 1 Bits 1..31 = 0
Data Sheet 11 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0
Electrical characteristics
5 Electrical characteristics
This chapter lists the maximum and operating ranges for various electrical and timing parameters.
5.1 Absolute maximum ratings
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
5.2 Functional operating range
Table 7 Absolute maximum ratings Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Supply Voltage VDD -0.3 – 4.1 V – Voltage on any pin Vmax -0.5 – 4.1 V – Ambient temperature TA -40 – 85 °C Standard temperature SLB 9673XU2.0 devices Ambient temperature TA -40 – 105 °C Enhanced temperature SLB 9673AU2.0 devices Storage temperature TS -40 – 125 °C – ESD robustness HBM: 1.5 kΩ, 100 pF VESD,HBM – – 2000 V According to EIA/JESD22-A114-B ESD robustness VESD,CDM – – 500 V According to ESD Association Standard STM5.3.1 - 1999 Latchup immunity I latch 100 mA According to EIA/JESD78 Table 8 Functional operating range Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Supply Voltage VDD 3.0 3.3 3.6 V – 1.65 1.8 1.95 V – Ambient temperature TA -40 – 85 °C Standard temperature SLB 9673XU2.0 devices Ambient temperature TA -40 – 105 °C Enhanced temperature SLB 9673AU2.0 devices U s e f u l l i f e t i m e ––1 0 y Operating lifetime – – 10 y Average T A over lifetime – 55 – °C
Data Sheet 12 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0
5.3 DC characteristics
Note: Current consumption does not include any curren ts flowing through resistive loads on output pins! Note: Device sleep mode will be entered after 50 millis econds of inactivity after the last TPM command was executed. Table 9 Current consumption Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Current Consumption in Active Mode IVDD_Active 35 mA Current Consumption in Sleep Mode IVDD_Sleep 120 µA Pins GPIO, RST# and I2C_PIRQ# = VDD, no I2C bus activity Table 10 DC characteristics of interface pins (SCL, SDA, TEST#, RST#, I2C_PIRQ#) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Input voltage high V IH 0.7 VDD VDD+0.5 V — Input voltage low V IL -0.5 0.3 V DD V— Input leakage current I LEAK -2 2 µA 0 V < V IN < VDD Output high voltage V OH 0.9 VDD VI OH = -100 µA Output low voltage V OL 0.1 VDD VI OL = 1.5 mA Pad input capacitance C IN 10 pF Output load capacitance C LOAD 30 pF Table 11 DC characteristics of GPIO pins Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Input voltage high V IH 0.7 VDD VDD+0.3 V Pins GPIO Input voltage low V IL -0.5 0.3 V DD VP i n s G P I O Input leakage current I LEAK -2 2 µA 0 V < V IN < VDD Output high voltage V OH VDD-0.3 V I OH = -1 mA, pins GPIO Output low voltage V OL 0.3 V I OL = 1 mA, pins GPIO Pad input capacitance C IN 10 pF Pins GPIO
Data Sheet 13 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0
5.4 AC characteristics
5.4.1 I2C Interface Characteristics
The electrical characteristics are compliant to the NXP I 2C bus specification [1] for “standard-mode” (fSCL ≤ 100 kHz), “fast-mode” ( fSCL ≤ 400 kHz) and “fast-mode plus” ( fSCL ≤ 1000 kHz), with certain deviations stated in Table 14, Table 15, and Table 16 below. For printed circuit board design the reduced output fall time tOF compared to the NXP I2C bus specification needs to be considered! Table 12 Power supply Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Supply voltage rise time t VDDR 1.0 V/ns Table 13 Device reset Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Cold (Power-On) Reset t POR 80 µs Warm Reset t WRST 2µ s Table 14 I2C Standard Mode Interface Characteristics Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. SCL clock frequency fSCL 0 — 100 kHz — Input voltage low VIL -0.5 — 0.3 V DD V— Input voltage high VIH 0.7 VDD —V DD+0.5 or VDD,max VM a x i m u m = m i n ( V DD+0.5, VDD,max) Output low voltage VOL ——0 . 4 VI OL = 2 mA, VDD ≤ 2V RST# VDD tPOR tWRS T tWRS T RST_Timing.vsdx
Data Sheet 14 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Output low voltage VOL ——0 . 4 VI OL = 3 mA, VDD > 2 V Low level output current IOL 2— — m A V OL = 0.4 V, VDD < 2.7 V Low level output current IOL 3— — m A V OL = 0.4 V, VDD ≥ 2.7 V Output fall time from VIHmin to VILmax (at device pin) tOF — — 250 ns C b ≤ 200 pF, VDD < 2.7 V Output fall time from VIHmin to VILmax (at device pin) tOF — — 250 ns C b ≤ 400 pF, VDD ≥ 2.7 V Capacitive load for each bus line Cb — — 200 pF V DD < 2.7 V Capacitive load for each bus line Cb — — 400 pF V DD ≥ 2.7 V Table 15 I2C Fast Mode Interface Characteristics Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. SCL clock frequency fSCL 0 — 400 kHz — Input voltage low VIL -0.5 — 0.3 V DD V— Input voltage high VIH 0.7 VDD —V DD+0.5 or VDD,max VM a x i m u m = m i n ( V DD+0.5, VDD,max) Output low voltage VOL ——0 . 4 VI OL = 2 mA, VDD ≤ 2V Output low voltage VOL ——0 . 4 VI OL = 3 mA, VDD > 2 V Low level output current IOL 2— — m A V OL = 0.4 V, VDD < 2.7 V Low level output current IOL 3— — m A V OL = 0.4 V, VDD ≥ 2.7 V Output fall time from VIHmin to VILmax (at device pin) tOF 20*VDD/ 5.5 V — 250 ns C b,min< Cb ≤ 200 pF, VDD < 2.7 V Output fall time from VIHmin to VILmax (at device pin) tOF 20*VDD/ 5.5 V — 250 ns C b,min< Cb ≤ 400 pF, VDD ≥ 2.7 V Capacitive load for each bus line Cb 15 — 200 pF V DD < 2.7 V Capacitive load for each bus line Cb 15 — 400 pF V DD ≥ 2.7 V Table 14 I2C Standard Mode Interface Characteristics (continued) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max.
Data Sheet 15 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0
5.5 Timing
Some pads are disabled after deassertion of the reset signal for up to 500 µs. The OPTIGA™ TPM SLB 9673 features security mech anisms which detect and count all resets. Table 16 I2C Fast Mode plus Interface Characteristics Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. SCL clock frequency fSCL 0 — 1000 kHz — Input voltage low VIL -0.5 — 0.3 V DD V— Input voltage high VIH 0.7 VDD —V DD+0.5 or VDD,max VM a x i m u m = m i n ( V DD+0.5, VDD,max) Output low voltage VOL ——0 . 4 VI OL = 2 mA, VDD ≤ 2V Output low voltage VOL ——0 . 4 VI OL = 3 mA, VDD > 2 V Low level output current IOL 2— — m A V OL = 0.4 V, VDD < 2.7 V Low level output current IOL 3— — m A V OL = 0.4 V, VDD ≥ 2.7 V Output fall time from VIHmin to VILmax (at device pin) tOF 20*VDD/ 5.5 V — 120 ns C b,min< Cb ≤ 150 pF Capacitive load for each bus line Cb 15 — 150 pF
Data Sheet 16 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Package dimensions (UQFN)
6 Package dimensions (UQFN)
All dimensions are given in millimeters (mm) unless otherwise noted. The packages are “green” and RoHS compliant. Figure 4 Package dimensions PG-UQFN-32-1,-2
6.1 Packing type
PG-UQFN-32-1,-2: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel Figure 5 Tape & reel dimensions PG-UQFN-32-1,-2 5.25 5.25 0.3 0.8 ALL DIMENSIONS ARE IN UNITS MM THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ ] INDEX MARKING PIN 1
Data Sheet 17 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Package dimensions (UQFN)
6.2 Recommended footprint
Figure 6 shows the recommended footprint for the packag e. The exposed pad of the package is internally connected to GND. It shall be connected to GND externally as well. Figure 6 Recommended footprint PG-UQFN-32-1,-2
6.3 Chip marking
Line 1: SLB9673 Line 2: XU20 yy or AU20 yy (see Table 1), the <yy> is an internal FW indication (only at manufacturing due to field upgrade option) Line 3: <Lot number> H <datecode> Figure 7 Chip marking For details and recommendations regarding assembly of packages on PCBs, please refer to http://www.infineon.com/cms/en/product/technology/packages/ 1234567 Infineon Lot Co de Softwarecode ChipMarking_UQFN.vsd XXH AU20 YY
Data Sheet 18 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 References References [1] —, “Trusted Platform Module Libr ary (Part 1-4)”, Family 2.0, Level 00, Rev. 01.59, November 8, 2019, TCG [2] —, “TCG PC Client Platform TPM Profile (PTP) Sp ecification”, Family 2.0, Level 00, Rev. 01.05 v14, September 4, 2020, TCG [3] —, “Errata For TCG Trusted Platform Libary, Family 2.0, Level 00, Rev. 01.59, November 8, 2019”, Errata Version 1.1, June 18, 2020, TCG [4] —, “Errata for PC Client Platform TPM Profile for TPM 2.0 Version 1.05 Revision 14”, Errata Version 1.0, September 04, 2020, TCG [5] —, “Registry of reserved TPM 2.0 handles and locali ties”, Version 1.1, Rev. 1.00, February 6, 2019, TCG [6] —, “TCG EK Credential Profile”, Ve rsion 2.3, Rev. 2, July 23, 2020, TCG [7] —, "NIST Special Publication 800-193, Platform Fi rmware Resiliency Guidelines", May, 2018, NIST
Data Sheet 19 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Terminology Terminology ESW Embedded Software HMAC Hashed Message Authentication Code I2C Inter Integrated Circuit (bus) ICT Information and Communications Technology IoT Internet of Things PCR Platform Configuration Register PUBEK Public Endorsement Key SPI Serial Peripheral Interface (bus) TCG Trusted Computing Group TPM Trusted Platform Module TSS TCG Software Stack
Data Sheet 20 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0 Licenses and notices Licenses and notices The following license and notice statements are reproduced from [1]. Licenses and Notices 1. Copyright Licenses: Trusted Computing Group (TCG) grants to the user of the source code in this specification (the "Source Code") a worldwide, irrevocable, nonexclusive , royalty free, copyright license to reproduce, create derivative works, distribute, display and perform the Source Code and deri vative works thereof, and to grant others the rights granted herein.The TCG grants to the user of the other parts of the specification (other than the Source Code) the rights to reproduce, distribute, display, and perform the specification solely fo r the purpose of developing products based on such documents. 2. Source Code Distribution Conditions: Redistributions of Source Code must retain the above copyright licenses, this list of conditions and the following disclaimers. Redistributions in binary form must reproduce the abov e copyright licenses, this list of conditions and the following disclaimers in the documentation and/or other materials provided with the distribution. 3. Disclaimers: THE COPYRIGHT LICENSES SET FORTH ABOVE DO NOT REPRESENT ANY FORM OF LICENSE OR WAIVER, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, WITH RESP ECT TO PATENT RIGHTS HELD BY TCG MEMBERS (OR OTHER THIRD PARTIES) THAT MAY BE NECESSARY TO IMPLEMENT THIS SPECIFICATION OR OTHERWISE. Contact TCG Administration (admin@trustedcomputinggroup.org) for information on spec ification licensing rights available through TCG membership agreements. THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO EXPRESS OR IMPLIED WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ACCURACY, COMPLETENESS, OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Without limitation, TCG and its members and licensors disclaim all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification and to the implementation of this specification, and TCG disclaims all liab ility for cost of procurement of substi tute goods or services, lost profits, loss of use, loss of data or any incidental, consequentia l, direct, indirect, or special damages, whether under contract, tort, warranty or otherwise, arising in any way out of use or reli ance upon this specification or any information herein. Any marks and brands contained herein are the property of their respective owners.
Data Sheet 21 Revision 1.2 2022-08-24 OPTIGA™ TPM SLB 9673 TPM2.0
Revision history
Page or item Subjects (major ch anges since previous revision) Revision 1.2, 2022-08-24 Fixed package designation in Figure 1. Revision 1.1, 2022-07-08 Added Section 4.1 Revision 1.0, 2022-05-25 Initial version
All referenced product or service names and trademarks are the property of their respective owners. Edition 2022-08-24 Published by Infineon Technologies AG
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© 2022 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: csscustomerservice@infineon.com IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. Please read the Important Notice and Warnings at the end of this document