ISL91108 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Accepts input voltages above or below regulated output voltage
  • Automatic and seamless transitions between buck and boost modes
  • Input voltage range: 1.8V to 5.5V
  • Output current: up to 1.6A DC (PVIN = 2.8V, V OUT = 3.3V)
  • Burst current: up to 2.7A (PVIN = 3V, V OUT = 3.3V, tON <600µs, t = 4.6ms)
  • High efficiency: up to 95%
  • 27.5µA quiescent current maximizes light load efficiency
  • 2.6MHz switching frequency minimizes external component size
  • Selectable forced PWM mode and external synchronization
  • Fully protected for short-circuit, over-temperature, and undervoltage
  • Small 2.34mm x 1.72mm WLCSP

Applications

  • Smartphones and tablets
  • Wireless communication devices
  • 2G/3G/4G power amplifiers

FIGURE 1. TYPICAL FIXED OUTPUT APPLICATION FIGURE 2. ISL91108IINZ EFFICIENCY vs OUTPUT CURRENT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 FN8448.1 November 12, 2014 Submit Document Feedback Block Diagram Pin Configuration ISL91108 (20 BUMP WLCSP) TOP VIEW OSC ERROR AMP PVIN PWM CONTROL PVIN MONITOR LX1 VREF REF REVERSE CURRENT VOUTB1 B2 B4 LX2 GATE DRIVERS & ANTI- SHOOT THRU D1VIN THERMAL SHUTDOWN CURRENT DETECT VOUT MONITOR EN D5 FB B3 PGND GND EN EN EN EN EN EN VOUT CLAMP D3MODE VOLTAGE PROG. EN SOFT DISCHARGE C2A2 C4A4 Pin Descriptions PIN # PIN NAMES DESCRIPTION A5, B5, C5 VOUT Buck-boost output. Connect 2x22µF capacitor to PGND. A4, B4, C4 LX2 Inductor connection, output side. A3, B3, C3 PGND Power ground for high switching current. A2, B2, C2 LX1 Inductor connection, input side. A1, B1, C1 PVIN Power input. Range: 1.8V to 5.5V. Connect 2x 10µF capacitor to PGND. D1 VIN Supply input. Range: 1.8V to 5.5V. D2 EN Logic input, drive HIGH to enable device. D3 MODE/ SYNC Logic input, HIGH for auto PFM mode. LOW for forced PWM operation. Also, this pin can be used with an external clock sync input. Range: 2.75MHz to 3.25MHz. D4 GND Analog ground pin. D5 FB Voltage feedback pin.

3 FN8448.1 November 12, 2014 Submit Document Feedback

Ordering Information

(Notes 1, 2, 3) PART MARKING VOUT (V) TEMP RANGE (°C) PACKAGE Tape and Reel (Pb-free) PKG. DWG. # ISL91108IINZ-T GAZA 3.3 -40 to +85 20 Bump WLCSP W4x5.20F ISL91108IINZ-T7A GAZA 3.3 -40 to +85 20 Bump WLCSP W4x5.20F ISL91108IIAZ-T GAXA ADJ. -40 to +85 20 Bump WLCSP W4x5.20F ISL91108IIAZ-T7A GAXA ADJ. -40 to +85 20 Bump WLCSP W4x5.20F ISL91108IIN-EVZ Evaluation Board for ISL91108IINZ ISL91108IIA-EVZ Evaluation Board for ISL91108IIAZ NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL91108. For more information on MSL please see techbrief TB363.

4 FN8448.1 November 12, 2014 Submit Document Feedback Absolute Maximum Ratings Thermal Information ESD Rating Thermal Resistance (Typical)  JA (°C/W) JC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 6. LX1 and LX2 pins can withstand switching tran sients of -1.5V for 100ns, and 7V for 20ms. Analog Specifications VIN = PVIN = EN = 3.6V, VOUT = 3.3V, L1 = 1µH, C1 = 2x 10µF, C2 = 2x 22µF, TA = +25°C. Boldface limits apply across the recommended operating temperature range, -40°C to +85°C and input voltage ranges. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7)U N I T S POWER SUPPLY VIN Input Voltage Range 1.8 5.5 V VUVLO VIN Undervoltage Lockout Threshold Rising 1.725 1.775 V Falling 1.550 1.650 V IVIN VIN Supply Current PFM mode, no external load on V OUT (Note 8)2 7 . 5 60 µA ISD VIN Supply Current, Shutdown EN = GND 0.4 1.0 µA OUTPUT VOLTAGE REGULATION VOUT Output Voltage Range ISL91108IIAZ, I OUT = 100mA 1.00 5.20 V Output Voltage Accuracy I OUT = 0mA, PWM mode -2 +2 % IOUT = 1mA, PFM mode -3 +4 % VFB FB Pin Voltage Regulation For adjustable output version (ISL91108IIAZ) 0.788 0.80 0.812 V IFB FB Pin Bias Current For adjustable output version (ISL91108IIAZ) 0.2 µA VOUT / VIN Line Regulation, PWM Mode I OUT = 500mA, MODE = GND, VIN step from 2.3V to 5.5V ±0.005 mV/mV VOUT / IOUT Load Regulation, PWM Mode V IN = 3.7V, MODE = GND, IOUT step from 0mA to 500mA ±0.005 mV/mA VOUT/ VIN Line Regulation, PFM Mode I OUT = 100mA, MODE = VIN, VIN step from 2.3V to 5.5V ±12.5 mV/V VOUT/ IOUT Load Regulation, PFM Mode V IN = 3.7V, MODE = VIN, IOUT step from 0mA to 100mA ±0.4 mV/mA VCLAMP Output Voltage Clamp Rising 5.25 5.95 V Output Voltage Clamp Hysteresis 400 mV

5 FN8448.1 November 12, 2014 Submit Document Feedback DC/DC SWITCHING SPECIFICATIONS fSW Oscillator Frequency V IN = 3.6V 2.4 2.6 2.9 MHz tONMIN Minimum On Time 80 ns IPFETLEAK LX1 Pin Leakage Current -0.5 +0.5 µA INFETLEAK LX2 Pin Leakage Current -0.5 +0.5 µA SOFT-START and SOFT DISCHARGE tSS Soft-start Time Time from when EN signal asserts to when output voltage ramp starts. 1m s Time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in buck mode. V IN = 4V, IOUT = 200mA 1m s Time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in boost mode. VIN = 2V, IOUT = 200mA 2m s RDISCHG VOUT Soft-Discharge ON-Resistance EN < V IL 110 Ω POWER MOSFET RDSON_P P-Channel MOSFET ON-Resistance I OUT = 200mA 90 m Ω RDSON_N N-Channel MOSFET ON-Resistance I OUT = 200mA 75 m Ω IPK_LMT P-Channel MOSFET Peak Current Limit 3.7 4.2 4.7 A PFM/PWM TRANSITION Load Current Threshold, PFM to PWM 200 mA Load Current Threshold, PWM to PFM 75 mA External Synchronization Frequency Range ±2% 2.75 3.25 MHz Thermal Shutdown 150 °C Thermal Shutdown Hysteresis 35 °C LOGIC INPUTS ILEAK Input Leakage 0.03 0.5 µA VIH Input HIGH Voltage 1.4 V VIL Input LOW Voltage 0.4 V NOTES: 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. Quiescent current measurements are taken when the output is not switching. Analog Specifications VIN = PVIN = EN = 3.6V, VOUT = 3.3V, L1 = 1µH, C1 = 2x 10µF, C2 = 2x 22µF, TA = +25°C. Boldface limits apply across the recommended operating temperature range, -40°C to +85°C and input voltage ranges. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7)U N I T S

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8448.1 November 12, 2014 For additional products, see www.intersil.com/en/products.html Submit Document Feedback Inductor Selection An inductor with high frequency core material (e.g., ferrite core) should be used to minimize core losses and provide good efficiency. The inductor must be able to handle the peak switching currents without saturating. A 1µH inductor with ≥4.0A saturation current rating is recommended. Select an inductor with low DCR to provide good efficiency. In applications where radiated noise must be minimized, a toroidal or shielded inductor can be used. PVIN and VOUT Capacitor Selection The input and output capacitors should be ceramic X5R type with low ESL and ESR. The recommended input capacitor value is 2x 10µF. The recommended VOUT capacitor value is 2x22µF. Recommended PCB Layout Correct PCB layout is critical for proper operation of the ISL91108. The input and output capacitors should be positioned as closely to the IC as possible. The ground connections of the input and output capacitors should be kept as short as possible and should be on the component layer to avoid problems that are caused by high switching currents flowing through PCB vias. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support TABLE 1. INDUCTOR VENDOR INFORMATION TABLE 2. CAPACITOR VENDOR INFORMATION

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE November 12, 2014 FN8448.1 -2nd paragraph: Changed From "This device is capable of delivering up to 2.7A output current (PVIN = 3V, 3.3V) … -Features section (bullet point #4) : changed from Output current: up to 1.5A (PVIN = 3V, VOUT = 3.3V) to “Output current: Up to 1.6A DC (PVIN = 2.8V, VOUT = 3.3V)” -Updated Load Current (I OUT) Range (DC) spec under “Recommended Operating Conditions” on page 4 from “0A to 1.5A” to “0A to 1.6A”. -Figures 1, 4 and 5: Removed the text "UP TO 2.7A" that appears next to the VOUT pin November 6, 2013 FN8448.0 Initial Release

9 FN8448.1 November 12, 2014 Submit Document Feedback Package Outline Drawing W4x5.20F 20 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP 0.4mm PITCH) Rev 0, 5/13 NOTES: Dimensions and tolerance per ASME Y 14.5M - 1994. Dimension is measured at the maximum bump diameter parallel to primary datum Z . Primary datum Z and seating plane are defined by the spherical crowns of the bump. Bump position designation per JESD 95-1, SPP-010. There shall be a minimum clearance of 0.10mm between the edge of the bump and the body edge. BOTTOM VIEWTOP VIEW SIDE VIEWRECOMMENDED LAND PATTERN 1.72±0.030 2.335±0.030 PIN 1 (A1 CORNER) (4X) 0.10 X Y 1.200 0.400 20x 0.265±0.035 1.600 0.3675 0.2600.200 ABCD PACKAGE OUTLINE 0.290 0.400 0.240

0.040 BSC

(BACKSIDE COATING) SEATING PLANE Z 0.05 Z 0.265±0.035 x20 ZXY Z 0.10 0.05 M M 0.200±0.030 0.540±0.050