ISL8601 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Input Voltage Range: +1.8V to 13.2V
  • VBIAS Voltage Range: +4.5V to 13.2V
  • Minimum Output Voltage: +0.5V
  • ±1.0% System Accuracy Over the Range of -40°C to +85°C When Using the 0.8V Reference
  • Internal Reference Voltage Programmable from 0.4V to 0.9V in 4mV Steps
  • Integrated 2A to 4A MOSFET Drivers
  • External Frequency Synchronization
  • Selectable Phase Delay: 0°, 90°, 120°, 180°, 240°, or 270°
  • Precision MOSFET r DS(ON) or Inductor DCR Current Sensing
  • Voltage Feedforward Compensation
  • Extensive PMBus Compliance
  • Broad PMBus Programmability Including Output Voltage, Overvoltage Threshold, Overcurrent Threshold, Overtemperature Threshold, Switching Frequency, Turn- On and Turn-Off
  • PMBus Monitoring of Load Current, Input Voltage, Output Voltage and Temperature
  • PMBus Programming Via I 2C Interface
  • Resistor Programming of Select PMBus Parameters
  • Operating Frequency Range: 200kHz to 2MHz
  • Internal and External Temperature Measurement
  • Overvoltage, Undervoltage and Overtemperature Protection
  • Low-Side and High-Side Overcurrent Protection
  • Programmable Supply Sequencing and Tracking
  • Digital Soft-Start with Multiple Soft-Start Modes
  • Multiple Programmable Fault-Handling Modes
  • Multiple Prebiased Startup Options
  • Differential Remote Voltage Sensing
  • Power-Good Output wit h Programmable Delay

Applications

  • Ethernet Routers and Switches
  • Point-of-Load Modules
  • Industrial Power Management

Ordering Information

PART NUMBER TEMP RANGE (°C) PACKAGE PKG. DWG. # ISL8601IRZ -40 to +85 40 Ld 6x6 QFN L40.6x6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 THERM RADDR ROV RCONF2 RCONF1 C50A UVLO VBIAS VFF REG5V RGND PGND LGATE PVCC PHASE UGATE BOOT HSOC DGND PGOOD ROSC ISENSN ISENSP N/C N/C LSOC AGND C25A SS COMP FB VMON VSENSP VSENSN EN SMBALRT SMBDAT SMBCLK C25D SYNC GND BOTTOM SIDE PAD Data Sheet *All functional details and specifications are preliminary and subject to change March 23, 2007

2 FN6449.0 March 23, 2007 Functional Block Diagram INTERNAL TEMP SENSE EXTERNAL TEMP MEASUREMENT THERM RESISTOR DECODE RCONF1 RCONF2 ROSC ROV VSENSP VSENSN VMON AV = 1 EA PWM COMP FB COMP 1.024V REFERENCE SOFT-START CIRCUITSS DRIVER CONTROL UGATE LGATE PHASE BOOT PGND RADDR SMBDAT SMBCLK SMBALRT SERIAL INTERFACE REG5V C50A C25D C25A VBIAS LDO2 LDO1 LDO3 LDO4 MAIN CONTROL LOGIC CURRENT SENSE ISENSP ISENSN 8-BIT DAC PGOOD GENERATOR PGOOD PVCC OSCILLATOR VFF SYNC EN DGND DIFA UVLO UVLO DETECT AGND 8-BIT MEASUREMENT ADC RGND LSOC HSOC ISL8601

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6449.0 March 23, 2007 Typical Application Circuit COUT VOUT UGATE PHASE LGATE BOOT ISENSP ISENSN +4.5V to +13.2V VSENSP VSENSN COMP FB VMON RFB ROS CSEN RADDR RCONF1 RCONF2 ROSC ROV ROVROSCRCONF2RCONF0RADDR SMBDAT SMBCLK SMBALRT I2C Bus 3 THERM PGOOD SS CSS C25D C25D C25A C25A C50A C50A EN SYNC AGND REG5V PVCC VBIAS DBOOT CREG5V RREG5V CPVCC VFF RUVLO1 RUVLO2 UVLO RTHERMDGND RGND HSOC RHSOC CHSOC LSOC RLSOC CLSOC RBOOT RVFF CVFF RVBIAS CVBIAS PGND LOUT ISL8601

4 FN6449.0 March 23, 2007 ISL8601 Package Outline Drawing L40.6x6

40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 3, 10/06 located within the zone indicated. The pin #1 indentifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: (4X) 0.15 INDEX AREA PIN 1 A6.00 B6.00 36X 0.50 4.54X

40 PIN #1 INDEX AREA

40X 0 . 4 ± 0 . 1 B0.10 MAC 4 . 10 ± 0 . 15 0 . 90 ± 0 . 1 C SEATING PLANE BASE PLANE 0.08 0.10 SEE DETAIL "X" C C 0 . 00 MIN. DETAIL "X" 0 . 05 MAX. 0 . 2 REFC 5 SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN ( 5 . 8 TYP ) ( 4 . 10 ) ( 36X 0 . 5 ) ( 40X 0 . 23 ) ( 40X 0 . 6 ) TOP VIEW 0 . 23 +0 . 07 / -0 . 05