SL74HC597 SLS | Alldatasheet
Document overview
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Technical content
8-Bit Serial or Parallel -Input/ Serial-Output Shift Register with Input Latch High-Performance Silicon-Gate CMOS The SL74HC597 is identical in pinout to the LS/ALS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of an 8 -bit input latch which feeds parallel data to an 8 -bit shift register. Dat a can also be loaded serially (see Function Table).
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Re commended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 ≤125 Unit VIH Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit fmax Minimum Clock Frequency (50% Duty Cycle) (Figures 2 and 8) 2.0 4.5 6.0 6.0 4.8 4.0 MHz tPLH, tPHL Maximum Propagation Delay, Latch Clock to QH (Figures 1 and 8) 2.0 4.5 6.0 210 265 315 ns tPLH, tPHL Maximum Propagation Delay , Shift Clock to QH (Figures 2 and 8) 2.0 4.5 6.0 175 220 265 ns tPHL Maximum Propagation Delay , Reset to QH (Figures 3 and 8) 2.0 4.5 6.0 175 220 265 ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/ Parallel Load to QH (Figures 4 and 8) 2.0 4.5 6.0 175 220 265 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 8) 2.0 4.5 6.0 110 ns CIN Maximum Input Capacitance - 10 10 10 pF Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V CPD Used to determine the no -load dynamic power consumption: PD=CPDVCC 2f+ICCVCC 50 pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tsu Minimum Setup Time, Parallel Data Inputs A -H to Latch Clock (Figure 5) 2.0 4.5 6.0 100 125 150 ns tsu Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 6) 2.0 4.5 6.0 100 125 150 ns tsu Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 7) 2.0 4.5 6.0 100 125 150 ns th Minimum Hold Time, Latch Clock to Parallel Data Inputs A-H (Figure 5) 2.0 4.5 6.0 ns th Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 6) 2.0 4.5 6.0 ns trec Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 3) 2.0 4.5 6.0 100 125 150 ns tw Minimum Pulse Width, Latch Clock and Shift Clock (Figures 1 and 2) 2.0 4.5 6.0 100 120 ns tw Minimum Pulse Width, Reset (Figure 2.0 4.5 6.0 100 120 ns tw Minimum Pulse Width, Serial Shift/Parallel Load (Figure 4) 2.0 4.5 6.0 100 120 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
Operation Reset Serial Shift/ Parallel Load Latch Clock Shift Clock Serial Input SA Parallel Inputs A-H Latch
Contents
Reset shift register L X L,H, X X X U L L Reset shift register; load parallel data into data latch L X X X a-h a-h L L Load parallel data into data latch H H L,H, X a-h a-h U U Transfer latch contents to shift register H L L,H, X X X U LRN SRN LRH Contents of data latch and shift register are unchanged H H L,H, L,H, X X U U U Load parallel data into data latch an d shift register H L X X a-h a-h a-h h Shift serial data into shift register H H X D X * SRA=D; SRN SRN+1 SRG SRH Load parallel data into data latch and shift serial data into shift register H H D a-h a-h SRA=D; SRN SRN+1 SRG SRH SR = shift register contents X = don’t care LR = latch register contents a-h = data at parallel data inputs A -H D = data (L,H) at serial data input SA * = depends on Latch Clock input U = remains unchanged INPUTS: A, B, C, D, E, F, G, H - Parallel data inputs. Data on these inputs is stored in the input latch on the rising edge of the Latch Clock input. SA - Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input if Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/ Parallel Load is low. SERIAL SHIFT/PARALLEL LOAD - Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the input latch, and serial shifting is inhibited. RESET - Asynchronous, Active -low shift register reset. A low level applied to this input resets the shift register to a low level, but does not change the data in the input latch. SHIFT CLOCK - Serial shift register clock. A low-to- high transition on this input shifts data on the Serial Data Input into the shift register and data in stage H is shifted out Q H, being replaced by the dat a previously stored in stage G. LATCH CLOCK - A low-to-high transition on this input loads the parallel data on inputs A -H into the input latch. OUTPUT: QH - Serial data output. This pin is the output from the last stage of the shift register.