SL74HC323 SLS | Alldatasheet
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Technical content
8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS The SL74HC323 is identical in pinout to the LS/ALS323. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC323 features a multiplexed parallel input/output data port to active full 8 -bit handling in a 20 pin pac kage. Due to the large output drive capability and the 3 -state feature, this device is ideally suited for interface with bus lines in a bus -oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode - Select lines, S 1 and S 2, high. This places the outputs in the high - impedance state, which permits data applied to the data port t o be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active -low synchronous Reset overrides all other inputs.
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 20=VCC PIN 10 = GND
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maxim um rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 ≤125 Unit VIH Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN=VIH or VIL IOUT ≤ 6.0 mA (P/Q) IOUT ≤ 7.8 mA (P/Q) 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VIN=VIH or VIL IOUT ≤ 4.0 mA (Q’) IOUT ≤ 5.2 mA (Q’) 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN=VIH or VIL IOUT ≤ 6.0 mA (P/Q) IOUT ≤ 7.8 mA (P/Q) 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 VIN=VIH or VIL IOUT ≤ 4.0 mA (Q’) IOUT ≤ 5.2 mA (Q’) 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three-State Leakage Current (QA thru QH) Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85 ≤125 Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 5) 2.0 4.5 6.0 5.0 4.0 3.4 MHz tPLH, tPHL Maximum Propagation Delay, Clock to QA’ or QH’ (Figures 1 and 5) 2.0 4.5 6.0 170 215 255 ns tPLH, tPHL Maximum Propagation Delay, Clock to QA or QH (Figures 1 and 5) 2.0 4.5 6.0 160 200 240 ns tPLZ, tPHZ Maximum Propagation Delay , OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) 2.0 4.5 6.0 150 190 225 ns tPZL, tPZH Maximum Propagation Delay , OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) 2.0 4.5 6.0 150 190 225 ns tTLH, tTHL Maximum Output Transition Time, QA thru QH (Figures 1 and 5) 2.0 4.5 6.0 ns tTLH, tTHL Maximum Output Transition Time, QA’ or QH’ (Figures 1 and 5) 2.0 4.5 6.0 110 ns CIN Maximum Input Capacitance - 10 10 10 pF COUT Maximum Three-State Output Capacitance (Output in High-Impedance State), QA thru QH - 15 15 15 pF Power Dissipation Capacitance (Per Package), Outputs Enable Typical @25°C,VCC=5.0 V CPD Used to determine the no -load dynamic power consumption: PD=CPDVCC 2f+ICCVCC 240 pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to-55°C ≤85°C ≤125°C Unit tsu Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) 2.0 4.5 6.0 100 125 150 ns tsu Minimum Setup Time, Data Inputs SA, SH, PA thru PH to Clock (Figure 4) 2.0 4.5 6.0 100 125 150 ns th Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) 2.0 4.5 6.0 120 150 180 ns th Minimum Hold Time, Clock to Data Inputs, S A, SH, PA thru PH (Figure 4) 2.0 4.5 6.0 ns tw Minimum Pulse Width, Clock (Figure 2.0 4.5 6.0 100 120 ns tw Minimum Pulse Width, Reset (Figure 2.0 4.5 6.0 100 120 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
QA’ QH’ S2 S1 OE1 OE2 DA DH Reset L X L L L X X L L L L L L L L L L L L X L L X X L L L L L L L L L L L H H X X X X X QA through Q H=Z L L Shift Right H L H H X D X Shift Right: QA through Q H=Z; DA FA; FA FB; etc D QG H L H X H D X Shift Right: QA through Q H=Z; DA FA; FA FB; etc D QG H L H L L D X Shift Right: DA FA =QA; FA FB =QB; etc D QG Shift Left H H L H X X D Shift Left: QA through Q H=Z; DH FH; FH FG; etc QB D H H L X H X D Shift Left: QA through Q H=Z; DH FH; FH FG; etc QB D H H L L L X D Shift Left: DH FH =QH; FH FG =QG; etc QB D Parallel Load H H H X X X X Parallel Load:PN FN PA PH Hold H L L H X X X X Hold: QA through Q H=Z; FN=FN PA PH H L L X H X X X Hold: QA through Q H=Z; FN=FN PA PH H L L L L X X X Hold: QN =QH PA PH Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the high -impedance state; however, sequential operation or clearing of the register is not affected.