SL74HC193 SLS | Alldatasheet
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Technical content
Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS The SL74HC193 is identical in pinout to the LS/ALS193. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. This counter may be preset by entering the desired data on the P0, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.Both a Terminal Count Down (TC D) and Terminal Count Up (TC U) Outputs are provided to enable cascading of both up and down counting functions. The TC D output produces a negative going pulse when the counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TC U and TC D outputs of one device to the Count Up Clock and Count Down Clock input s, respectively, of the next device.
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 ≤125 Unit VIH Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA FUNCTION TABLE Inputs Mode MR PL CPU CPD H X X X Reset(Asyn.) L L X X Preset(Asyn.) L H H No Count L H H Count Up L H H Count Down L H H No Count X = don’t care The IN74HC193 is an UP/DOWN MODULO-16 Binary Counter. Logic equations For Terminal Count: TCU = Q0 • Q1 • Q2 • Q3 • CPU TCD = Q0 • Q1 • Q2 • Q3 • CPD
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit fmax Minimum Clock Frequency (50% Duty Cycle) (Figures 1 and 6) 2.0 4.5 6.0 3.2 2.6 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures 1 and 6) 2.0 4.5 6.0 215 270 325 ns tPLH, tPHL Maximum Propagation Delay, PL to Q (Figures 3 and 6) 2.0 4.5 6.0 215 270 325 ns tPLH, tPHL Maximum Propagation Delay, Clock to Terminal Count (Figures 2 and 6) 2.0 4.5 6.0 125 155 190 ns tTLH, tTHL Maximum Output Transition Time,Any Output (Figures 1 and 6) 2.0 4.5 6.0 110 ns CIN Maximum Input Capacitance - 10 10 10 pF Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V CPD Used to determine the no -load dynamic power consumption: P D=CPDVCC 2f+ICCVCC 60 pF TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tsu Minimum Setup Time, Pn to PL (Figure 4) 2.0 4.5 6.0 100 125 150 ns th Minimum Hold Time, Pn to PL (Figure 2.0 4.5 6.0 ns tw Minimum Pulse Width, Clock (Figure 2.0 4.5 6.0 150 190 225 ns tw Minimum Pulse Width, PL (Figure 3) 2.0 4.5 6.0 100 125 150 ns tw Minimum Pulse Width, MR (Figure 5) 2.0 4.5 6.0 100 125 150 ns tr, tf Minimum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 100 500 400 100 500 400 100 500 400 ns