ISL6208_13 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 13

Technical content

Features

  • Dual MOSFET Drives for Synchronous Rectified Bridge
  • Adaptive Shoot-Through Protection
  • 0 . 5Ω On-Resistance and 4A Sink Current Capability
  • Supports High Switching Frequency up to 2MHz - Fast Output Rise And Fall Time - Low Propagation Delay
  • Three-State PWM Input for Power Stage Shutdown
  • Internal Bootstrap Schottky Diode
  • Low Bias Supply Current (5V, 80µA)
  • Diode Emulation for Enhanced Light Load Efficiency and Pre-Biased Start-Up Applications
  • VCC POR (Power-On-Reset) Feature Integrated
  • Low Three-State Shutdown Holdoff Time (Typical 160ns)
  • Pin-to-Pin Compatible with ISL6207
  • QFN and DFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline DFN - Dual Flat No Leads - Package Outline - Near Chip Scale Package Footprint, which Improves PCB Efficiency and has a Thinner Profile
  • Pb-Free (RoHS Compliant)

Applications

  • Core Voltage Supplies for Intel® and AMD® Mobile Microprocessors
  • High Frequency Low Profile DC/DC Converters
  • High Current Low Output Voltage DC/DC Converters
  • High Input Voltage DC/DC Converters Related Literature
  • T e c h n i c a l B r i e f TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”
  • T e c h n i c a l B r i e f TB389 “PCB Land Pattern Design and Surface Mount Guidelines for MLFP Packages”
  • T e c h n i c a l B r i e f TB447 “Guidelines for Preventing Boot-to-Phase Stress on Half-Bridge MOSFET Driver ICs” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2004-2008, 2011, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. January 31, 2012 FN9115.6

ISL6208, ISL6208B 2 FN9115.6 January 31, 2012 Pin Configurations Block Diagram ti

Ordering Information

(Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL6208CBZ ISL62 08CBZ -10 to +100 8 Ld SOIC M8.15 ISL6208CRZ 208Z -10 to +100 8 Ld 3x3 QFN L8.3x3 ISL6208BCRZ 8BC -10 to +100 8 Ld 2x2 DFN L8.2x2D ISL6208IBZ ISL62 08IBZ -40 to +100 8 Ld SOIC M8.15 ISL6208IRZ 8IRZ -40 to +100 8 Ld 3x3 QFN L8.3x3 ISL6208BIRZ 8BI -40 to +100 8 Ld 2x2 DFN L8.2x2D NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6208, ISL6208B. For more information on MSL please see techbrief TB363. ISL6208CBZ, ISL6208IBZ (8 LD SOIC) TOP VIEW ISL6208CRZ, ISL6208IRZ (8 LD 3x3 QFN) TOP VIEW ISL6208BCRZ, ISL6208BIRZ (8 LD 2x2 DFN) TOP VIEW UGATE BOOT PWM GND PHASE FCCM VCC LGATE UGATE PHASE GND LGATE FCCM VCC BOOT PWM 5

6 VCC

6 PHASE

THERMAL PAD (FOR QFN AND DFN PACKAGE ONLY) FIGURE 1. BLOCK DIAGRAM

ISL6208, ISL6208B 3 FN9115.6 January 31, 2012 ti Absolute Maximum Ratings Thermal Information -0.3V to 9V (<10ns) GND - 8V (<20ns Pulse Width, 10µJ) VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 4. The Phase Voltage is capable of withstan ding -7V when the BOOT pin is at GND. 5. θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 8. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature range. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS VCC SUPPLY CURRENT Bias Supply Current I VCC PWM pin floating, VFCCM = 5V - 80 - µA POR VCC Rising -3 . 4 0 3.90 V VCC Falling 2.40 2.90 - V Hysteresis - 500 - mV BOOTSTRAP DIODE Forward Voltage V F VVCC = 5V, forward bias current = 2mA 0.50 0.55 0.65 V PWM INPUT Input Current I PWM VPWM = 5V - 250 - µA VPWM = 0V - -250 - µA PWM Three-State Rising Threshold V VCC = 5V 0.70 1.00 1.30 V PWM Three-State Falling Threshold V VCC = 5V 3.5 3.8 4.1 V Three-State Shutdown Hold-off Time t TSSHD VVCC = 5V, temperature = +25°C 100 175 250 ns FCCM INPUT FCCM LOW Threshold 0.50 --V FCCM HIGH Threshold -- 2.0 V SWITCHING TIME UGATE Rise Time (Note 9) t RU VVCC = 5V, 3nF load - 8.0 - ns LGATE Rise Time (Note 9) t RL VVCC = 5V, 3nF load - 8.0 - ns

ISL6208, ISL6208B 4 FN9115.6 January 31, 2012 UGATE Fall Time (Note 9) t FU VVCC = 5V, 3nF load - 8.0 - ns LGATE Fall Time (Note 9) t FL VVCC = 5V, 3nF load - 4.0 - ns UGATE Turn-Off Propagation Delay t PDLU VVCC = 5V, outputs unloaded - 18 - ns LGATE Turn-Off Propagation Delay t PDLL VVCC = 5V, outputs unloaded - 25 - ns UGATE Turn-On Propagation Delay t PDHU VVCC = 5V, outputs unloaded 10 20 30 ns LGATE Turn-On Propagation Delay t PDHL VVCC = 5V, outputs unloaded 10 20 30 ns UG/LG Three-State Propagation Delay t PTS VVCC = 5V, outputs unloaded - 35 - ns Minimum LG ON-TIME in DCM (Note9) t LGMIN - 400 - ns OUTPUT Upper Drive Source Resistance R U 500mA source current - 1 2.5 Ω Upper Driver Source Current (Note 9) I U VUGATE-PHASE = 2.5V - 2.00 - A Upper Drive Sink Resistance R U 500mA sink current - 1 2.5 Ω Upper Driver Sink Current (Note 9) I U VUGATE-PHASE = 2.5V - 2.00 - A Lower Drive Source Resistance R L 500mA source current - 1 2.5 Ω Lower Driver Source Current (Note 9) I L VLGATE = 2.5V - 2.00 - A Lower Drive Sink Resistance R L 500mA sink current - 0.5 1.0 Ω Lower Driver Sink Current (Note 9) I L VLGATE = 2.5V - 4.00 - A NOTES: 9. Limits established by characteriza tion and are not production tested. 10. Parameters with MIN and/or MAX limits ar e 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature range. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS

ISL6208, ISL6208B 5 FN9115.6 January 31, 2012 Typical Application with 2-Phase Converter +5V BOOT UGATE PHASE LGATE PWM FCCM VCC DRIVE VBAT +5V BOOT UGATE PHASE LGATE PWM VBAT +VCORE PGOOD VID FS GND ISEN2 ISEN1 PWM2 PWM1 VSEN MAIN FB VCC +5V COMP ISL6208 CONTROL VCC DRIVE ISL6208 +5V DACOUT FCCM FCCM THERMAL PAD THERMAL PAD

ISL6208, ISL6208B 6 FN9115.6 January 31, 2012 Timing Diagram Functional Pin Description UGATE The UGATE pin is the upper gate drive output. Connect to the gate of high-side power N-Channel MOSFET. BOOT BOOT is the floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap Diode” on page 8 for guidance in choosing the appropriate capacitor value. PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation. See “Three-State PWM Input” on page 8 for further details. Connect this pin to the PWM output of the controller. GND GND is the ground pin for the IC. LGATE LGATE is the lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET. VCC Connect the VCC pin to a +5V bias supply. Place a high quality bypass capacitor from this pin to GND. FCCM The FCCM pin enables or disables Diode Emulation. When FCCM is LOW, diode emulation is allowed. Otherwise, continuous conduction mode is forced. See “Diode Emulation” on page 8 for more detail. PHASE Connect the PHASE pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver.

Description

Designed for speed, the ISL6208 dual MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising edge on PWM initiates the turn-off of the lower MOSFET (see “Timing Diagram” above). After a short propagation delay PDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the “Electrical Specifications” section. Adaptive shoot- through circuitry monitors the LGATE voltage. When LGATE has fallen below 1V, UGATE is allowed to turn ON. This prevents both the lower and upper MOSFETs from conducting simultaneously, or shoot-through. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [t PDLU] is encountered before the upper gate begins to fall [tFU]. The upper MOSFET gate-to-source voltage is monitored, and the lower gate is allowed to rise after the upper MOSFET gate-to-source voltage drops below 1V. The lower gate then rises [tRL], turning on the lower MOSFET. This driver is optimized for converters with large step-down compared to the upper MOSFET because the lower MOSFET conducts for a much longer time in a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.5Ω ON-resistance and 4A sink current capability enable the lower gate driver to absorb the current injected to the lower gate through the drain-to-gate capacitor of the lower MOSFET and prevent a shoot-through caused by the high dv/dt of the phase node. PWM UGATE LGATE tPDLL tFL tPDHU tRU tPDLU tFU tPDHL tRL 2.5V tRU tFU tFL tPTS tTSSHD tTSSHD tPTS

ISL6208, ISL6208B 9 FN9115.6 January 31, 2012 Layout Considerations Reducing Phase Ring The parasitic inductances of the PCB and power devices (both upper and lower FETs) could cause increased PHASE ringing, which may lead to voltages that exceed the absolute maximum rating of the devices. When PHASE rings below ground, the negative voltage could add charge to the bootstrap capacitor through the internal bootstrap diode. Under worst-case conditions, the added charge could overstress the BOOT and/or PHASE pins. To prevent this from happening, the user should perform a careful layout inspection to reduce trace inductances, and select low lead inductance MOSFETs and drivers. D 2PAK and DPAK packaged MOSFETs have high parasitic lead inductances, as opposed to SOIC-8. If higher inductance MOSFETs must be used, a Schottky diode is recommended across the lower MOSFET to clamp negative PHASE ring. A good layout would help reduce the ringing on the phase and gate nodes significantly:

  • Avoid using vias for decoupling components where possible, especially in the BOOT-to-PHASE path. Little or no use of vias for VCC and GND is also recommended. Decoupling loops should be short.
  • All power traces (UGATE, PHASE, LGATE, GND, VCC) should be short and wide, and avoid using vias. If vias must be used, two or more vias per layer transition is recommended.
  • Keep the SOURCE of the upper FET as close as thermally possible to the DRAIN of the lower FET.
  • Keep the connection in between the SOURCE of lower FET and power ground wide and short.
  • Input capacitors should be placed as close to the DRAIN of the upper FET and the SOURCE of the lower FET as thermally possible. Note: Refer to Intersil Tech Brief TB447 for more information. Thermal Management For maximum thermal performance in high current, high switching frequency applications, connecting the thermal pad of the QFN and DFN parts to the power ground with multiple vias, or placing a low noise copper plane underneath the SOIC part is recommended. This heat spreading allows the part to achieve its full thermal potential.

ISL6208, ISL6208B Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN9115.6 January 31, 2012 For additional products, see www.intersil.com/product_tree Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL6208, ISL6208B To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE January 17, 2012 FN9115.6 Added limits for “UGATE Turn-On Propagat ion Delay” and “LGATE Turn-On Propagation Delay” on page 4. October 26, 2011 FN9115.5 Removed limits for “UGATE Turn-On Propagation Delay” and “LGATE Turn-On Propagation Delay” on page 4. July 12, 2011 FN9115.4 Added “Revision History” on page 10 and “Products” on page 10. Added ISL6208BCRZ and ISL6208BIRZ parts to “Ordering Information” on page 2. Removed leaded, obsolete devices (ISL6208CB, ISL6208CR, ISL6208IB, ISL6208IR). Updated Tape & Reel note in “Ordering Information” on page 2 from "Add "-T" suffix for tape and reel." to new standard "Add "-T*" suffix for tape and reel." The "*" covers all possible tape and reel options Added MSL note to “Ordering Information” on page 2 Added Pinout for ISL6208BIRZ and ISL6208BCRZ on page 2 Added “Thermal Information” on page 3 for new ISL6802B package, 8 Ld 2x2 DFN. Added Theta JC for SOIC package and Note 8. Removed "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested." from common conditions of spec table. Added as Note in MIN MAX columns of “Electrical Specifications” table. Added standard text "Boldface limits apply over the operating temp range" to common conditions of spec table. Bolded applicable specs. Updated “Package Outline Drawing” on page 13 (M8.15) as follows: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern

ISL6208, ISL6208B 11 FN9115.6 January 31, 2012 Package Outline Drawing L8.3x3

8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 3/07 located within the zone indicated. The pin #1 indentifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension b applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: BOTTOM VIEW DETAIL "X"TYPICAL RECOMMENDED LAND PATTERN TOP VIEW BOTTOM VIEW SIDE VIEW (4X) 0.15 INDEX AREA PIN 1 3.00 B A 3.00 8X 0.60 ± 0.15 C 8X 0.28 ± 0.05 M

0.10 B A

0.654X PIN #1 INDEX AREA 1 .10 ± 0 . 15 0 . 90 ± 0.1 SEE DETAIL "X" BASE PLANE SEATING PLANE 0.10 0.08 C C C C 0 . 05 MAX. 0 . 2 REF 0 . 00 MIN. ( 2. 60 TYP ) ( 1. 10 ) ( 8X 0 . 80) ( 8X 0 . 28 ) ( 4X 0 . 65 )

ISL6208, ISL6208B 12 FN9115.6 January 31, 2012 Package Outline Drawing L8.2x2D

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD

Rev 0, 3/11 BOTTOM VIEW DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW PIN #1 B0.10M AC C SEATING PLANE BASE PLANE 0.08 0.10 SEE DETAIL "X" C C 0 . 00 MIN. 0 . 05 MAX. 0 . 2 REFC INDEX AREA PIN 1 (4X) 0.15 A B PACKAGE 2.00 2.00 1.55±0.10 0.90±0.10 0.22 ( 6x0.50 ) ( 8x0.22 ) 2.00 2.00 ( 8x0.30 ) ( 8x0.20 ) ( 8x0.30 ) 0.50 0.90 1.55 0.90±0.10 INDEX AREA OUTLINE located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance: Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. Dimension applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES:

ISL6208, ISL6208B 13 FN9115.6 January 31, 2012 Package Outline Drawing M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 3, 3/11 DETAIL "A" TOP VIEW INDEX AREA 12 3 -C- SEATING PLANE x 45° NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Co nverted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. SIDE VIEW “A SIDE VIEW “B” 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 4 5 TYPICAL RECOMMENDED LAND PATTERN 2.20 (0.087) 0.60 (0.023)